KR20100056218A - Low-temperature recoverable electronic component - Google Patents

Abstract

PURPOSE: An electronic component is provided to be used for a process including resin underfill and embedded chip technology by preventing an interconnected structure or chip of a package from being damaged. CONSTITUTION: A base insulation layer(10) includes a first surface(12) and a second surface(14). An electronic device includes a first surface(20) and a second surface(22) and is fixed to the base insulation layer. An adhesive layer(16) is arranged between the first surface of the electronic device and the second surface of the base insulation layer. A removable layer(26) is arranged between the first surface of the electronic device and the second surface of the base insulation layer. The base insulation layer is fixed to the electronic device through the removable layer. The removable layer releases the base insulation layer from the electronic device at a low temperature.

Description

Electronic component {LOW-TEMPERATURE RECOVERABLE ELECTRONIC COMPONENT}

The present invention includes embodiments relating to the manufacture of interconnect structures. The present invention includes embodiments relating to a method of recovering chips or other electrical components from interconnect structures.

Bonding electronic devices, such as semiconductor chips, individual passives, BGA carriers, or other electrical components, onto printed circuit boards, substrates, interconnect structures, or flex circuits, is generally performed using solder or adhesives. In the area array solder attachment assembly, the electrical connections are made by raising the temperature so that the solder that solidifies by cooling reflows. In applications where the thermal expansion coefficient (CTE) of the electronic device does not closely match the thermal expansion coefficient of the substrate when the electronic device is attached, thermal cycling can stress the solder bonds and cause solder weakening defects. One way to overcome this problem is to encase the solder bonds with a polymer resin underfill such as filled epoxy to eliminate the stress of the solder bonds. Such underfill can be applied by spraying liquid resin on one or more sides of the component and causing the resin to flow under the component by capillary action.

Electronic devices that are sensitive to exposure to high temperatures, such as 200 ° C., should not use high temperature thermoplastic bonding materials. In addition, the low temperature thermoplastic material may not be exposed to subsequent processing steps, such as curing, or any assembly step above its melting or softening temperature. As a result, thermosetting resin adhesives are used for the processing of such electronic devices, since the thermosetting adhesives can be cured at relatively low temperatures (> 200 ° C.) and are still stable at higher temperatures in subsequent processing steps or use environments. Also, lower temperature adhesion and bonding is desirable because zero stress points are established at the bonding temperature and lower bonding temperatures lower the stress in the interconnect assembly at normal operating temperatures.

If multiple electronic devices are attached to a common substrate and one of the devices is found to be defective after solder attachment and underfill hardening, it is generally located on the substrate and the substrate by removing the defective device and replacing it with a new part. It is desirable to find another electronic device. Thermoset underfill resins cannot be remelted at normal processing temperatures, so that defective electronic devices are not removed and the entire circuit must be discarded. Thus, the use of low processing temperature low stress thermoset adhesives results in a non-repairable processing step. Remeltable, reworkable thermoplastic resins also require high temperature processing, resulting in high stress structures that are incompatible with many planned applications.

Similar problems also occur in embedded chip applications where the interconnect structure is directly attached to the surface of the electronic component. In such applications, the use of thermoplastic adhesives to bond electronic components to interconnect structures may result in extreme stresses on the structure due to high thermoplastic melting temperatures or to increase component operating and / or assembly temperatures due to low thermoplastic melting temperatures. Severely restrict. In addition, the thermoplastic adhesive turns into a liquid while bonding the chip to the film, allowing the chip to move during processing. The use of thermoplastic adhesives in such applications reduces stress and improves operating and assembly temperature ranges, but makes it extremely difficult to recover electronic components if this is not possible.

In the current embedded chip process, referred to as embedded chip build-up (ECBU) or chips first build-up (CFBU) technology, bare chips can be used as a boundary or peripheral I / O pad or high density without solder bonding or wirebonding. Packaged with an array of I / O pads distributed over the top surface within the interconnect structure. The ECBU or CFBU process can be used to form chip carriers that interconnect complex semiconductor chips to larger contact pads that are compatible with board level assemblies such as printed circuit boards. Such a high-end chip may be worth hundreds of dollars, but a carrier formed to interface the chip to a circuit board may be less valuable. Since all complex interconnect structures have processing defects due to electrical shorts and / or openings, they have inherent output losses. In conventional flip chip or wire bonded chip carrier assemblies, the interconnect structure has been fully fabricated and electrically inspected prior to assembling expensive chips. Thus, a defective interconnect structure did not result in expensive chip losses. In the ECBU process, since chips are bonded to the interconnect structure prior to fabricating the interconnect structure, it can potentially generate a case where a good chip has to be discarded with a bad package.

In one embodiment, the present invention provides an electrical component. The electrical component includes a base insulating layer having a first surface and a second surface, an electronic device having a first surface and a second surface and fixed to the base insulating layer, and a first surface of the electronic device and a base insulating layer. An adhesive layer disposed between the two surfaces and a removable layer disposed between the first surface of the electronic device and the second surface of the basic insulating layer. The base insulating layer is secured to the electronic device through the removable layer. The removable layer releases the basic insulating layer from the electronic device at a sufficiently low temperature.

The present invention includes embodiments relating to the manufacture of electronic devices or interconnect structures. The present invention includes an embodiment of a method of recovering a chip or other electrical component from the device. The method may provide for intact electronic device recovery, such as chips from defective interconnect structures or packages. This method may be useful in processes involving resin underfills and other embedded chip technologies. However, this method can be used in applications where electronic device retrieval from interconnect structures or packages is required.

In one embodiment, the method may provide an interconnect structure or electrical component. The method includes applying a removable layer to an electronic device or base insulating layer, applying an adhesive layer to the electronic device or base insulating layer, and fixing the electronic device to the base insulating layer using the electronic adhesive layer. Can be.

The electrical component may include a base insulating layer having a first surface and a second surface, and an electronic device having a first surface and a second surface and secured to the base insulating layer. In the space defined between the electronic device and the opposing surface of the basic insulating layer, there is an adhesive layer and a removable layer. In particular, the adhesive layer may be disposed between the first surface of the electronic device and the second surface of the base insulating layer, and the removable layer is disposed between the first surface of the electronic device and the second surface of the base insulating layer.

Suitable materials for use as the base insulating layer may include one or more of polyimide, polyetherimide, benzocyclobutyne (BCB), liquid polymer, bismaleimidetriazine resin (BT resin), epoxy or silicone. Commercially available suitable materials for use as the base insulating layer include KAPTON H polyimide or KAPTON E polyimide (manufactured by EI du Pont de Nemours & Co.), APICAL AV polyimide (Kanegafugi Chemical Industry Company). Manufactured by UPILEX polyimide (manufactured by UBE Industries, Ltd.) and ULTEM polyetherimide (manufactured by General Electric Co.). In the illustrated embodiment, the base insulating layer is fully cured as KAPTON H polyimide.

The base insulating layer may form an interconnect structure, a flex circuit, a circuit board, or other structure. The interconnect structure may be mounted and interconnected with one or more electronic devices. In connection with one embodiment, the optional properties for the base insulating layer include modulus of elasticity and thermal and humidity expansion coefficients that provide a minimum length change during processing. In order to maintain elasticity, the thickness of the base insulating layer can be minimized. The base insulating layer must have sufficient strength to selectively support the metallization layer on both the first and second surfaces (due to thickness, support structure, or material properties) and maintain size stability during subsequent processing steps.

With regard to the thickness of the base insulating layer, an appropriate thickness may be selected based on the end use application, the number and type of electronic devices, and the like. The thickness may be greater than about 10 μm. The thickness may be less than about 50 μm. In one embodiment, the base insulating layer is in a range greater than about 10 μm to about 20 μm, about 20 μm to about 30 μm, about 30 μm to about 40 μm, about 40 μm to about 50 μm, or about 50 μm. Has a thickness. With respect to one embodiment where the basic insulating layer is a circuit board, the appropriate thickness thereof may be based on the number of layers inside the circuit board. The number of circuit board layers generally ranges from about 2 to about 50 and each layer has a thickness of about 100 μm.

The adhesive layer is a thermosetting resin adhesive. Examples of suitable adhesives may include thermosetting resin polymers. Suitable thermosetting resin polymers may include epoxies, silicones, acrylates, urethanes, polyetherimides, or polyimides. Suitable thermosetting resins commercially available include CIBA GEIGY 412 (manufactured by Ciba Geigy), AMOCO AI-10 (manufactured by Amoco Chemicals Corporation) and PYRE-MI ^® (EI du Pont de Nemours & Co. Polyimide). CIBA GEIGY 412 has a glass transition temperature of about 360 degrees Celsius. Other suitable adhesives may include thermoplastic adhesives, water cure adhesives, air drying adhesives, and radiation treating adhesives.

In one embodiment, the low temperature sensitive adhesive layer secures or bonds the electronic device to the basic insulating layer, and within this capacity the low temperature sensitive adhesive layer can serve as both the adhesive layer and the removable layer. The adhesive releases or loses tack at the specified low release temperature.

Suitable low temperature sensitive adhesives may be thermosetting resin adhesives. Examples of suitable low temperature sensitive adhesives include epoxy or polyimide. The properties of most commercial adhesives are available, and the choice of adhesive material is based on the curing temperature, cryofracture temperature (if applicable), out-gassing, thermal and oxidative stability and temperature of interest. It may be based on factors such as bonding strength in the range. The selection of the cold sensitive adhesive can include matching the coefficient of thermal expansion of the cold sensitive adhesive to one or more components of the interconnect device. In one embodiment, the low temperature sensitive adhesive may have a coefficient of thermal expansion (CTE) in the range of about 15 ppm / ° C to about 20 ppm / ° C. Low temperature sensitive adhesives must lose adhesion at temperatures below the operating temperature of the interconnect device. In addition, low temperature sensitive adhesives should be chosen that do not chemically interact with the electronic device.

The adhesive layer can be applied to form a layer having a thickness greater than about 5 μm on the base insulating layer surface. In one embodiment, the adhesive layer is about 5 μm to about 10 μm, about 10 μm to about 20 μm, about 20 μm to about 30 μm, about 30 μm to about 40 μm, about 40 μm to about 50 μm, or about It has a thickness in the range larger than 50 mu m.

The adhesive layer may be applied to the basic insulating layer by spin coating, spray coating, roller coating, meniscus coating, screen printing, stencil, pattern print deposition, jetting, or other spraying methods. In one embodiment, the adhesive is applied by dry film lamination. The adhesive layer may be applied to partially or completely cover the second surface of the basic insulating layer. For example, the adhesive layer may be applied to an optional area on the base insulating surface, such as an electronic device mounting area, while other areas on the base insulating layer surface, such as an electrical contact pad or electrical test pad, may be left uncoated. . This may be accomplished by a direct injection system such as jetting, or by a stencil or screen printing standard assembly processing step used to selectively apply solder mask resin to a board, substrate or component. The direct spray process may deposit a layer having a thickness less than about 50 μm, and screen-printing techniques may form a deposited layer having a thickness greater than about 50 μm.

In one embodiment, the adhesive layer may be deposited on the electronic device in a liquid state and then dried. The adhesive layer may itself be applied in liquid form or may be deposited as part of a liquid solution mixed with a solvent. In one example, a suitable liquid thermoset resin polymer is N-mp 66.4% by weight in a liquid solution, 0.59% by weight 0.1% of FC 430® (surfactant commercially available from 3M) and 8.3% by weight of DMAC. It may comprise 24.8% by weight of CIBA GEIGY 412 in a liquid solution comprising a. Droplets of such materials may be sprayed onto the electronic device in sufficient volume to produce a coating of about 200 μm to about 1000 μm. After the adhesive layer solution has been deposited, the material may be dried in a sequential series of heat treatment steps, for example, 10 to 20 minutes at about 150 ° C., 10 to 20 minutes at about 220 ° C., and 10 to 20 at about 300 ° C. Can be dried for a minute. The number and duration of heat treatment steps as well as the temperature used will depend on the particular thermosetting polymer or other material used. This drying sequence removes the solvent from the thermosetting resin adhesive solution and leaves a completely dried layer of adhesive layer on the electronic device. Thermosetting polymers are fully crosslinked and are no longer soluble in solvent solutions and will not soften unless exposed to extreme high temperatures.

The adhesive layer can be fully cured if necessary to bond or secure the electronic device to the basic insulating layer. Curing temperatures below the melting temperature of the removable layer should be used.

In one embodiment, the removable layer comprises a thermoplastic polymer. Suitable thermoplastic polymers to be used to form the removable layer include, but are not limited to, thermoplastic resins including polyolefins, polyimides, polyetherimides, polyether ether ketones, polyether sulfones, silicones, siloxanes, or epoxies. It is not limited. Examples of suitable thermoplastic polymers are XU 412 (commercially available from Ciba Geigy), ULTEM 1000 and ULTEM 6000, polyetherimide resins made by GE Plastics, VITREX, Ciba Geigy, a polyether ether ketone commercially available from Victrex Polyether sulfone XU 218 commercially available from and UDEL 1700® polyether sulfone commercially available from Union Carbide.

Suitable methods of applying the removable layer to the electronic device include spray coating, spin coating, roll coating, meniscus coating, dip coating, transfer coating, jetting, drop spraying, pattern print deposition, or dry film lamination. do. The removable layer can have a thickness greater than about 5 μm. In one embodiment, the removable layer is about 5 μm to about 10 μm, about 10 μm to about 20 μm, about 20 μm to about 30 μm, about 30 μm to about 40 μm, about 40 μm to about 50 μm, or Have a thickness within a range greater than about 50 μm.

A removable layer can be applied to the electronic device when the electronic device is in the form of a single component or when the electronic device is in the form of a panel or wafer. For example, if the electronic device is a semiconductor chip, the removable layer may be applied at the wafer level, or after wafer processing and wafer sawing is complete. The wafer may be sawed into two or more individual chips using semiconductor wafer dicing equipment. Chips may be rinsed to remove sawing residue. Alternatively, the removable layer can be applied directly onto the singulated chip after wafer sawing. If a removable layer is applied at the wafer level, it can be deposited onto the chip by spin coating or spray coating. If a removable layer is applied to the unified chip, a spray coating or drop spray will apply the removable layer. In small packaged electronic devices that can be fabricated in a panel with a plurality of devices with which the electronic device is processed together, such as an array chip scale component region, the removable layer may be roll coated, meniscus coated or other batches. Can be applied by an application method.

The removable layer can be applied to partially or fully cupper the first surface of the electronic device. For example, the removable layer material may be applied to an optional area of the electronic device, such as a device mounting area, leaving the I / O contact or other desirable area on the electronic device uncoated. This may be accomplished by a direct injection system such as jetting or by a stencil or screen printing standard assembly processing step used to selectively apply solder mask resin onto a boat, substrate or component.

If the removable layer partially covers the first surface of the electronic device, then the adhesive layer must partially cover the second surface of the basic insulating layer. In particular, the adhesive layer is not coated with a removable layer of an area on the first surface of the electronic device, and the electronic device on the base insulating layer is not in contact with the adhesive when the electronic device is disposed opposite the base insulating layer and bonded to the base insulating layer. It should only be applied to selective areas of the mounting area.

The removable layer may consist of a soluble or solvent-swellable polymer. Thus, a solvent or solvent mixture may be applied to the interconnect structure to dissolve, soften or swell the removable layer. This will release the electronic device from the base insulating layer and the interconnect structure. In this electronic device recovery method, the interconnect structure and the attached device can be immersed in a solvent bath. The solvent in the bath contacts at least a portion of the removable layer and is dissolved, softened or swelled. This solvation allows the interconnect structure to be removed from the first surface of the electronic device. Low temperature sensitive electronic devices, or other components, do not suffer from unwanted high temperatures such as those used in heat recovery processes. Soluble or solvent-swellable polymers may be thermoplastic polymers.

Suitable solvents include those capable of dissolving, softening or swelling the removable layer. Specific solvents may be selected with reference to the material composition of the removable layer. Depending on the material of the removable layer, suitable solvents are acetone, anisole, acetophenone, benzene, toluene, alcohol, g-butyllactone, N-methyl pyrrolidone, methylene chloride and dimethyl sulfoxide (DMSO). And the like. Other suitable solvents include acids and bases for pH sensitive removable layer materials such as sulfuric acid.

In one example, a first solvent mixture of 4 parts meta-cresol and 16 parts orthodichlorobenzene (ODCB) in weight percent and a second of 4 parts metacresol and 16 parts acetophenone in weight percent The solvent mixture dissolves a soluble removable layer comprised of ULTEM 6000. The proportion of these materials can be varied as needed. In addition, soluble polymers comprising PEEK® can be dissolved in concentrated sulfuric acid, and soluble polymers comprising XU 218 thermoplastic materials include g-butyllactone, N-methyl pyrrolidone, methylene chloride, acetone and aceto Can be dissolved in a solvent such as phenone.

If a functional electronic device is recovered from a poor interconnect structure, a solvent that does not chemically react with or damage the electronic device should be used. Alternatively, if it is desired to remove a poor electronic device from a functioning interconnect structure, a solvent that does not chemically react with or damage the interconnect structure components other than the electronic device and the removable layer should be used. In addition, a wet etchant may be used in combination with heat to dissolve the removable layer to recover the electronic device.

Low temperature sensitive adhesives may be affected for loss of adhesion or loss of mechanical strength at sufficiently low threshold temperatures. In one embodiment, the removable layer may be exposed to low temperatures at which the adhesive material loses tack and releases the electronic device. In other embodiments, the removable layer may be exposed to low temperatures that release the electronic device by breaking or breaking the adhesive material. The holding device can secure the electronic device and hold it on the interconnect structure. Interconnect structures comprising a low temperature sensitive adhesive may be cooled to temperatures below about -75 ° C. The temperature is selected based on the properties of the removable layer.

If a functioning electronic device is to be separated from the poor basic insulating layer and recovered from the interconnect structure, the interconnect structure must be cooled to a temperature above the minimum damage threshold temperature of the electronic device. The minimum damage threshold temperature of an electronic device is the minimum temperature at which the electronic device can be exposed without damaging the active components of the device. Alternatively, if a bad electronic device is to be removed from a functionally insulating insulation layer and recovered from the interconnect structure, the interconnect structure must be cooled to a temperature above the minimum damage threshold temperature of the functional insulation layer. . The minimum damage threshold temperature of the base insulation layer that can function is the minimum temperature at which the base insulation layer that can function can be exposed without damaging the components.

After the electronic device is removed from the interconnect structure, residual adhesive layers and electrically conductive materials located within the vias may remain on the electronic device. The electrically conductive material or excess residual adhesive layer remaining on the electronic device surface and in the vias may be removed by wet etching, plasma etching, chemical etching or reactive ion etching, and the remaining adhesive material may be removed by plasma etching, chemical etching or Can be removed by reactive ion etching. Also, if the electrically conductive material is made of metal, some of the conductive material remaining on the electronic device may be removed by metal etching. If the electrically conductive material comprises a Cu or Ti: Cu bimetal structure, Cu may be etched with nitric acid to leave the thin Ti metallized in place.

After removing any remaining residual adhesive layer and electrically conductive material from the electronic device, the device is in an almost initial state and ready to be assembled to another interconnect structure.

In one embodiment of forming the removable layer, the thermoplastic polymer is deposited on the electronic device in liquid form and then dried. The thermoplastic polymer may be applied in liquid form or may be deposited, for example, as part of a liquid solvent mixed with a solvent. In one embodiment, a suitable solution is CIBY GEIGI, such as 4.1% by weight of a solution of 2.5% DMAC (dimethyl acetamide) by weight, 27.3% by weight anisole and 66.1% by weight γ-butyrolactone (GBL) It is formed by adding XU 412 together. Droplets of such materials can be sprayed onto the electronic device in sufficient volume to produce a coating having a thickness in the range of about 100 μm to about 1000 μm. After the liquid thermoplastic polymer is deposited, the material may be dried in a series of subsequent heat treatment steps. Examples of suitable heat treatment steps may be drying at about 150 ° C. for 10-20 minutes, at about 220 ° C. for 10-20 minutes, and at about 300 ° C. for 10-20 minutes. The number and duration of heat treatment steps as well as the temperature used will depend on the specific thermoplastic polymer used. This drying sequence removes the solvent from the thermoplastic polymer solution to form a removable layer by leaving a completely dried layer of thermoplastic polymer on the electronic device.

Another factor to consider is the pressure applied in part during curing. In essence, higher pressures create thinner bonding lines. If a higher pressure is needed than to enable a sufficiently thick bonding line, spacer material may be added to the adhesive to control the bonding line thickness. The spacer material may be selected to have additional functionality as long as it can have desirable thermal conductivity and electrical resistance, such as inherent properties.

If the removable layer is a curable material, it can be cured after the removable layer is formed. The removable layer can be cured thermally, by radiation, or by a combination of heat and radiation. Suitable radiation can include ultraviolet (UV), electron beams, and / or microwaves. The cured removable layer must be sufficiently transparent within visible wavelengths so that the automated vision system can distinguish wafer saw lanes and I / O contact features in wafer sawing and chip pick and place. do. Such transparency enables sawing alignment during wafer sawing and alignment of chips or other electronic devices during placement. In addition, the cured removable layer must be laser drillable at the wavelength used to remove the vias through the underlying insulating layer. For example, the cured removable layer is preferably laser drillable.

After application of the adhesive layer, the adhesive layer can be cured. The adhesive layer is partially cured until the adhesive is at the B-step point, which is not fully cured but is sufficiently stable for further operation. The adhesive layer can be cured by heat treatment or a combination of heat or radiation. Suitable radiation can include UV light and / or microwaves. If partial vacuum is present, it can be used to promote removal of volatiles from the adhesive during curing.

Referring to FIG. 1A, in one embodiment of the present invention, the basic insulating layer 10 has a first surface 12 and a second surface 14. The base insulating layer was fixed to the frame structure (not shown in this figure) to provide dimensional stability to the insulating layer during processing. The base insulating layer was formed of an electrically insulating material. In addition, the base insulating layer may be a polymer film to which an electrically conductive material can be fixed.

As shown in FIG. 1B, an adhesive layer 16 may be applied to the second surface of the basic insulating layer. The adhesive layer may be bonded to the electronic device 18 (see FIG. 1C). Thus, the adhesive layer can fix or bond the electronic device to the basic insulating layer.

As shown in FIG. 1C, the electronic device has a first surface 20 and a second surface 22. The first surface of the electronic device can be the active surface of the device where one or more I / O contacts 24 are located. Examples of I / O contacts that may be located on an electronic device include pads, pins, bumps, and solder balls. In the embodiment shown, the I / O contact is an I / O pad. Other suitable electronic devices include packaged or unpackaged semiconductor chips such as microprocessors, microcontrollers, video processors, or application specific integrated circuits (ASICs); Individual passive; Or a ball grid array (BGA) carrier. In one embodiment, the electronic device is a semiconductor silicon chip having an array of I / O contact pads disposed on its first surface.

With further reference to FIG. 1C, a removable layer 26 is applied to the first surface of the electronic device. Subsequently, the electronic device and the removable layer subassembly can be coupled onto the base insulating layer.

In one embodiment, the active surface or the first surface of the electronic device may be arranged to contact the second surface of the base insulating layer, such that the active surface of the electronic device having a removable layer thereon is brought into contact with the adhesive layer. It is arranged (see Fig. 1 (d)). For example, the base insulating layer may be an automated pick and place system that picks up each electronic device from the tray of a single chip, such as a diced wafer or a waffle pack. Can be placed in a heated stage of the pick and place system. The partially cured adhesive layer is heated to soften the adhesive and become tacky but not cured. The chip is then placed with its first surface facing down so that the active surface of the chip faces the second surface of the base insulating layer, so that the I / O contacts of each chip are along the baseline on the base insulating layer. Aligned (see FIG. 1 (d)).

In one embodiment shown in FIG. 2A, a removable layer is applied to the first surface of the electronic device. The removable layer can be applied to the electronic device and cured as described above in the first embodiment. An adhesive layer can be applied to the first surface of the electronic device on top of the removable layer, which is used to bond the electronic device to the basic insulating layer as shown in FIG. Appropriate application methods are the same as described above.

Referring to FIG. 2C, the active surface or first surface of the electronic device having a removable layer and an adhesive layer thereon may be placed in contact with the second surface of the basic insulating layer. The base insulating layer was fixed to the frame structure to provide dimensional stability to the insulating layer during processing. In an automated system, the base insulating layer may be placed in the heated stage of an automated pick and place system that picks up each electronic device, in this case a chip from a tray of unified chips, such as a diced wafer or waffle pack. Can be. The chip is heated to soften the partially cured adhesive layer and develop stickiness, but not to cure. The chips are then arranged so that the electronic device first surface faces the second surface of the base insulating layer, such that the I / O contacts of each chip are aligned along the baseline on the base insulation layer. The adhesive layer can be fully cured as described above.

Referring to FIG. 3A, in one embodiment, the base insulating layer is secured to the frame structure (not shown) to provide dimensional stability for the insulating layer during processing. In this embodiment, as shown in FIG. 3 (b), the removable layer is applied to the second surface of the basic insulating layer instead of being applied to the electronic device. The removable layer can be applied by the manner described above.

If the removable layer is removed from a selected area of the base insulating layer, the patterned removable layer can be used as the solder mask material so that it can be used to define the metal area to be protected from the solder during solder adhesion reflow. have. The patterned removable layer, when used as a solder mask, is used in a solder mask defined method where the solder mask material covers the edges of the solder contact pads and defines the areas where the solder will form bonding. Alternatively, the patterned removable layer can be used in a non-solder mask defined way in which the metal pad defines the solder area, instead of the solder mask generally not overlapping the edge of the solder contact pad. The non-solder mask prescribed method is less preferred because it may remain in a small area around each solder pad, where an underfill adhesive may create a permanent bond that can interfere with subsequent electronic device removal. . Solder masks are used to cover traces that follow from solder pads and other adjacent metal features.

Solder adhesion to a eutectic tin: lead solder undergoes thermal exposure of about 220 ° C., lead-rich tin: lead solder undergoes thermal exposure of about 300 ° C., and lead-free solder from about 240 to about It is exposed to a temperature of about 260 ° C. In this embodiment the removable layer material must be chosen such that the melting point is higher than the solder reflow temperature of the selected solder system. The removable layer is the same as described above.

The adhesive layer is applied to the first surface of the electronic device and used to bond the electronic device to the basic insulating layer (see FIG. 3 (c)). The adhesive layer is applied to the electronic device as described above. However, in this embodiment, an adhesive layer is applied directly on the first surface of the electronic device instead of being applied on the outer opposing surface of the removable layer pre-coupled with the electronic device.

If the removable layer is applied to partially cover the area of the electronic device-mounting region on the base insulating layer, the adhesive layer should be applied to partially cover the first surface of the electronic device. In particular, the adhesive layer is selective on the electronic device such that the area on the second surface of the base insulating layer that is not coated with the removable layer does not contact the adhesive when the electronic device is disposed with respect to the base insulating layer and bonded to the base insulating layer. Should be applied to the area. The adhesive layer can be partially cured until the adhesive is in the B-stage.

The active surface or first surface of the electronic device may be disposed in contact with the second surface of the basic insulating layer. The active surface of the electronic device has an adhesive layer disposed thereon and contacts the removable layer (see FIG. 3 (d)). An automated pick and place system can be used to place the electronic device on the basic insulating layer. The adhesive layer can be cured to bond the electronic device to the basic insulating layer. A curing temperature lower than the melting temperature of the removable layer should be used.

In one embodiment, the base insulating layer has a first surface and a second surface (see FIG. 4 (a)). The base insulating layer is fixed to the frame structure (not shown) to provide dimensional stability to the insulating layer during processing. In this embodiment, the removable layer is applied to the base insulating layer and cured as described above (see Figure 4 (b)).

As shown in Fig. 4C, the adhesive layer is applied to the second surface of the base insulating layer on the outer opposing surface of the removable layer. The adhesive layer can be applied as described above.

The active surface or first surface of the electronic device may be disposed in contact with the second surface of the base insulating layer, whereby the active surface of the electronic device is arranged in adhesive contact with the adhesive layer on the base insulating layer (see FIG. 4 (d)). ). An automated pick and place system can be used to place the electronic device on the basic insulating layer.

5A-5B, a low temperature sensitive adhesive layer 28 is applied to a second surface of the base insulating layer to bond at least one electronic device to the base insulating layer. Low temperature sensitive adhesives may be useful for the adhesive to effectively bond the electronic device to the underlying insulating layer during processing and service life.

The active surface or the first surface of the electronic device may be disposed in contact with the second surface of the base insulating layer, whereby the active surface of the electronic device is disposed in contact with the low temperature sensitive adhesive (see FIG. 5 (b)). . For example, the base insulating layer may be placed in the heating stage of an automated pick and place system that picks up each electronic device, in this case a chip, from a tray of unified chips, such as a diced wafer or waffle pack. have. If only the partially cured low temperature sensitive adhesive is heated, the adhesive will therefore soften and become tacky. The chips are then arranged with their first surface facing down so that the active surface of the chip faces the second surface of the base insulating layer, so that the I / O contacts of each chip are placed on the baseline on the base insulating layer. Are aligned along. The low temperature sensitive adhesive is fully cured to bond the electronic device to the base insulating layer.

In one embodiment, the low temperature sensitive adhesive is applied to the first surface of the electronic device instead of the basic insulating layer as shown in FIG. 6 (a). The low temperature sensitive adhesive can be partially cured until the adhesive is in the B-stage. The cold sensitive adhesive can be handled, processed and combined as described above. Subsequently, the low temperature sensitive adhesive is fully cured.

The active or first surface of the electronic device having a low temperature sensitive adhesive thereon may contact the second surface of the basic insulating layer (see FIG. 6 (b)). The base insulating layer can be secured to the frame structure to provide dimensional stability to the insulating layer during processing.

In order to recover the electronic device from the interconnect structure and the base insulating layer, the encapsulation step can be postponed until the final processing step. However, if the electronic device remains unencapsulated on the base insulating layer during processing, the base insulating layer suffers from patterning problems due to the non-planarity of the unencapsulated surface. Will be.

The base insulating layer is fixed to the frame structure to provide dimensional stability to the base insulating layer during processing. In one embodiment, the frame panel 30 has a first surface 32 and a second surface 34. The frame has a surface defining an opening or opening 38 for the electronic device region on each of the basic insulating layers (see FIGS. 7A and 7B).

As shown in FIG. 8, the basic insulating layer may be fixed to the frame panel. The frame panel may stabilize the base insulating layer instead of or in addition to the frame structure (shown above) during fabrication of the interconnect structure. In addition, the frame panel can improve the planarity of the unencapsulated surface of the base insulating layer during processing. The frame panel may be a relatively permanent component of the interconnect structure. As shown in Figure 7 (a), the frame panel may be large enough to include a plurality of openings 38, each opening for a different electronic device region on the base insulating layer, and thus the frame The panel provides stabilization and provides improved planarity for multiple electronic device regions. Alternatively, the frame panel can include a single opening and can be sized to provide improved planarity and stability for one electronic device region on the base insulating layer.

Suitable frame panels may be formed from metal, ceramic or polymeric materials. Suitable polymeric materials may include polyimides, or epoxy or epoxy mixtures. The polymeric material may include one or more reinforcing fillers. Such a bloom may include fibers or small inorganic particles. Suitable fibers can be glass fibers or carbon fibers. Suitable particles can include silicon carbon, boron nitride, or aluminum nitride. The frame panel may be a molded polymer structure. In one embodiment, the frame panel is a metal selected from titanium, iron, copper or tin. Alternatively, the metal may be an alloy or metal mixture such as stainless or Cu: Invar: Cu. The particular material from which the frame panel is formed may be selected for a particular design based on the desired coefficient of thermal expansion, hardness or other desirable mechanical properties. The frame panel may have a metal coating. Suitable metals for the coating may include nickel. The frame panel may have a polymer coating. Suitable polymer coating materials can include polyimides that can improve tack.

The frame structure and / or frame panel may stabilize the basic insulating layer during processing. However, the use of a frame structure or frame panel may not be necessary. For example, roll-to-roll processing may not require the use of a frame structure or frame panel.

The frame panel may have a coefficient of thermal expansion (CTE) greater than about 10 ppm / ° C. The frame panel may have a coefficient of thermal expansion (CTE) of less than about 20 ppm / ° C. In one embodiment, the frame panel may have a thickness equal to or close to the thickness of the electronic device.

In one embodiment, the first surface of the frame panel is fixed to the first surface of the base insulating layer (see FIGS. 8 (a) and 8 (b)). The basic insulating layer may be bonded to the frame panel using the adhesive layer 40. Suitable adhesives for bonding the frame panel to the base insulating layer include at least the materials listed above as suitable adhesive materials. Appropriate application methods include those listed above.

In addition, if the adhesive layer used to bond the frame panel to the base insulating layer is the same as the adhesive layer used to bond the electronic device to the base insulating layer, the electronic device and the frame panel are disposed on the base insulating layer and simultaneously Can be cured. This may simplify the processing steps or reduce the number of steps. For example, as shown in FIG. 9, the second surface of the base insulating layer 14 is coated with a thermosetting resin adhesive layer 16, and the adhesive material is cured in a B-step. The second surface of the basic insulating layer is laminated to the first surface of the frame panel 30 as shown in FIG. 9 (b). An already cured electronic device 18 with a removable layer is disposed on the second surface of the basic insulating layer in the opening in the frame panel 30 (see FIGS. 9 (a) and 9 (b)). The adhesive layer is fully cured to bond the frame panel and the electronic device to the basic insulating layer.

Each opening in the frame panel may range from about 0.2 mm to about 5 mm larger in the x and y dimensions than the electronic device. This increase in size may facilitate subsequent placement of the electronic device on the base insulating layer. Alternatively, the frame panel may be disposed on the base insulating layer after the electronic device is placed and / or bonded on the base insulating layer.

Referring to Figure 10 (a), for example, the second surface of the basic insulating layer is coated with an adhesive layer and the adhesive is cured in a B-step. An electronic device having a removable layer thereon is disposed on the second surface of the basic insulating layer as shown in FIG. 10 (b). The second surface of the basic insulating layer is laminated to the first surface of the frame panel as shown in FIGS. 10 (c) and 10 (d). The electronic device is disposed in the opening in the frame panel. Finally, the adhesive layer is fully cured to bond the frame panel and the electronic device to the basic insulating layer.

In one embodiment, the sub-assembly comprises a removable layer and an adhesive layer and a barrier coating disposed therebetween to form a sandwich. The barrier coating can block the migration of reactive species from the adhesive layer and can prevent the adhesive layer from reacting with the removable layer during processing. If this reaction occurs, it may create a weak interface or defect point between the removable layer and the adhesive layer. For example, the thermosetting resin adhesive layer may react with the thermoplastic material of the removable layer during high temperature processes such as curing.

The barrier coating may be applied to the opposite outer surface (on top of the removable layer) after the removable layer is applied to the electronic device, or after the base insulating layer and the removable layer are cured. The barrier coating can be an organic or inorganic layer. In embodiments in which an organic barrier coating is used, the barrier coating may be applied to the basic insulating layer or electronic device by a method described herein as suitable for the application of a barrier layer or a removable layer, which is chemical vapor deposition, plasma Includes but is not limited to deposition or reactive sputtering. In embodiments where an inorganic barrier coating is used, the barrier coating can be deposited by, for example, CVD, vapor deposition or sputtering. If a barrier coating is applied to the surface of the electronic device, the barrier coating may be applied at the wafer level after wafer processing is completed and before wafer sawing. Alternatively, the barrier coating may be applied on the singulated chip after wafer sawing.

The barrier coating may comprise one or more organic materials selected from polyolefins, polyesters, or porous hydrogenated carbons. Other suitable barrier coatings may be formed from inorganic materials such as Ta ₂ O ₅ , Al ₂ O ₃ , Sb ₂ O ₃ , Bi ₂ O ₃ , WO ₃ or ZrO ₂ .

In one embodiment, the electrical connection between the electronic device and the base insulating layer is formed after the electronic device is bonded to the base insulating layer. In particular, the electrical connections are made between the I / O contact (s) located on the electronic device and the electrical conductor (s) located on the basic insulating layer.

Referring to FIG. 11, a suitable electrical conductor 40 that can be positioned on the base insulating layer includes pads, pins, bumps, and solder balls. The electrical connection between the base insulating layer and the electronic device may be a structure selected based on the application specific parameters. For example, openings, holes, or vias 42 may be formed through the base insulating layer, the adhesive layer, and the removable layer to one or more I / O contacts on the electronic device (see FIG. 11). In one embodiment, the vias can be sized such that they are micro-vias. Laser ablating, mechanical drilling, punching, wet chemical etching, plasma etching, or reactive ion etching can form vias.

If the laser ablation technique forms vias, the underlying insulating layer can be supported by the frame structure and can be turned over and placed on an automated laser system. The laser system can be programmed so that the laser removes the basic insulating layer at the selected location. This process forms blind vias through the basic insulating layer, the adhesive layer, and the removable layer to the plurality of I / O contacts 24 on the electronic device 18. If desired, laser ablation may lead to a de-smear or de-scum process that removes residual ash and residual adhesive layers in the vias to expose I / O contacts on the electronic device. Can be. This step can be performed by reactive ion etching (RIE), plasma cleaning or wet chemical etching. If desired, a trace, power plane or ground plane may be formed on the first surface of the base insulating layer.

Referring to FIG. 11B, an electrically conductive material, denoted by reference numeral 44, may be disposed on the first surface of the base insulating layer 10 and inside the via that extends to the I / O contact on the electronic device. have. The electrically conductive material may be an electrically conductive polymer and may be deposited by jetting or screening. Examples of suitable electrically conductive materials may include epoxy, polysulfone, or polyurethane in combination with metal particle fillers. Suitable metal particles include silver and gold. Other suitable metals may include Al, Cu, Ni, Sn and Ti. Rather than being filled with polymeric materials, inherent conductive polymers can be used. Suitable conductive polymers include polyacetylene, polypyrrole, polythiophene, polyaniline, polyfluorine, poly-3-hexylthiophene, polynaphthalene, poly-p-phenyline sulfide and poly-p-phenyline vinyline do. If the viscosity and stability problems are solved, the inherently conductive polymer can be filled with an electrically conductive filler to further enhance the electrical conductivity.

If the conductive material is a metal, the conductive material may be deposited by a method comprising one or more of sputtering, evaporation, electroplating or nonelectroplating. In one embodiment, the first surface of the base insulating layer and the exposed surface of the vias extending to the I / O contacts on the electronic device are metallized using a combined sputter plating and electroplating sequence. The base insulating layer is disposed in the vacuum sputter system with exposed vias to the first surface of the base insulating layer and the sputter system. The backsputter step sputter-etches the exposed device I / O contact to remove residual sticky material and native metal oxide. In addition, the back sputtering step etches up to the surface of the basic insulating layer. Sputter etching of metal I / O contacts may reduce the contact resistance of subsequent metallization steps while etching of the base insulating layer may increase metal adhesion to the first surface of the base insulating layer.

As shown in FIG. 11 (b), the seed metal layer 44 is sputter deposited on the first surface of the base insulating layer, on sidewalls defining vias, and on exposed I / O contacts. Dual-metal systems can be used that include barrier metals such as Ti or Cr and non-barrier metals such as Cu or Au. The barrier metal may be plated to a thickness in the range of about 1000 mm to about 3000 mm and the non-barrier metal may be plated to a thickness in the range of about 0.2 μm to about 2.0 μm. The metal deposition step may form a metal interconnect on the first surface or on the non-component side of the base insulating layer.

Following the sputtering step, a relatively thicker layer of the non-barrier seed metal layer is electroplated on the primary insulating layer first surface as shown in Fig. 11 (c). Suitable metallization patterning processes may include semi-additives or pattern plate-up processes as shown in FIG. 11. The metallized surface of the base insulating layer comprising via sidewalls is electroplated with metal to form a layer having a thickness in the range of about 2 μm to about 20 μm. Referring to FIG. 11 (c), a photomask material is deposited on the first surface of the basic insulating layer and photo-patterned to expose selected areas of the surface. The areas on the first surface of the base insulating layer to retain the metal, such as traces, I / O contacts, and vias, remain covered with photoresist, and the areas of the surface of the base insulating layer desired to have the metal removed are not covered. Without exposure. The plurality of wet metal etch baths remove the plated and sputtered metal in the exposed underlying insulating layer surface areas, while the remaining areas are protected from the wet etchant by the masking material. Following completion of the etching step, the remaining photoresist material is removed. Removal of the photoresist material exhibits the desired metallization pattern as shown in FIG. 11 (d).

In one sequence, a depleted metal patterning process is used. In this method, the photomask material is disposed on the first surface of the base insulating layer and photo-patterned to expose selected areas of the surface. The area on the first surface of the base insulating layer to retain the metal, such as interconnect traces, I / O contacts, and vias, remains covered with photoresist while the area of the base insulating layer surface on which the metal is to be removed is shown. It remains uncovered as shown in 11 (c). The exposed metallized regions of the first surface of the base insulating layer including the via sidewalls are electroplated to a thickness in the range of about 4 μm to about 20 μm. Since the plated metal will have sidewalls along the straight sidewalls of the patterned photoresist, the photoresist thickness should be greater than the thickness of the metal to be plated. Following completion of the plating process step, the remaining photoresist material is removed, showing the metallized regions on the first surface of the base insulating layer without seed metal plating as shown in FIG. 11 (d). A plurality of standard wet metal etch baths can remove the exposed seed metal to leave the desired metallization pattern. Electrical connections between the base insulating layer and the electronic device can be formed using a solder process.

The process steps described above complete the electrical connection of the first interconnect layer 48 to the I / O contacts of the electronic device. Interconnection to one or more complex electronic devices, including semiconductor chips such as microprocessors, video processors and ASICs, may require additional interconnect layers to completely route out all desired chip I / O contacts. have. For such electronic devices, one or more additional interconnect layers may be formed on the first surface of the base insulating layer. For simpler electronic devices with less routing complexity, only one interconnect layer may be needed.

In one embodiment, an additional interconnect layer is formed by bonding an additional insulating layer 50 to the first interconnect layer. In one embodiment shown in FIG. 12A, the additional insulating layer comprises a first surface 52 and a second surface 54, coated with an adhesive layer 56. Suitable adhesives for use in the present invention include the materials described above as suitable adhesive materials. If the adhesive layer comprises a thermosetting resin material, after applying the adhesive layer to the additional insulating layer, the adhesive is cured in a B-step.

Suitable methods of applying the adhesive layer to the additional interconnect layer include spray coating, spin coating, roll coating, meniscus coating, dip coating, transfer coating, jetting, drop spraying, pattern print deposition or dry film laminate. The adhesive layer may have a thickness greater than about 5 μm. In one embodiment, the removable layer is about 5 μm to about 10 μm, about 10 μm to about 20 μm, about 20 μm to about 30 μm, about 30 μm to about 40 μm, about 40 μm to about 50 μm, or Have a thickness within a range greater than about 50 μm. In another embodiment, the adhesive layer may be a prefabricated self-adhesive film applied to the surface of the additional insulating layer.

Referring to FIG. 12 (b), the second surface of the additional insulating layer is arranged to contact the basic insulating layer first surface (non-component side). The adhesive layer is fully cured to bond additional insulating layers to the base insulating and interconnect layers 48. In one embodiment, the additional insulating layer is laminated on the first surface of the base insulating layer using a heated vacuum lamination system.

The electrical conductor (s) 40 on the additional insulating layer is electrically connected to the electrical conductor (s) 40 on the basic insulating layer. For example, as shown in FIG. 12 (c), vias can be formed through additional insulating layers and through adhesive layers to selected electrical conductors on the base insulating layer. The same process steps as used to form the vias and deposit the electrically conductive material in the first interconnect layer, as described above, are used to form the electrically conductive vias in the additional insulating and contact layers. Can be used (see FIG. 12 (d)).

In one embodiment, the first surface of the additional insulating layer may be metallized to complete the second interconnect layer using the metallization and patterning steps described above for the first interconnect layer. Multiple additional interconnect layers may be formed in the same manner.

As shown in FIGS. 12D and 13, a plurality of interconnect layers are combined to define interconnect assembly 60. The interconnect assembly has a first surface 62 and a second surface 64. The interconnect assembly may be completed by coating a first surface of the assembly with dielectric or solder masking material 68 to define the contact pads used for assembly or package I / O contacts and to passivate any metal traces. Package I / O contacts may have additional metal deposition, such as Ti: Ni: Au, applied to exposed contact pads to provide more robust I / O contacts. Additional metal deposition can be applied by nonelectroplating. I / O contact pads may have pins, solder spheres, or lead attached thereto, or remain to create a pad array. FIG. 13 shows an interconnect assembly 60 having an array of solder spheres, such as a ball grid array. Other interconnect structures may be used. For example, the interconnect assembly may have an array of pins, such as a pin grid array.

In completing the interconnect structure, which may be an interconnect layer or an interconnect assembly comprising a plurality of interconnect layers, a standard electrical inspection station determines if all interconnections are correct. If correct, it means no open or short circuit. If the inspection indicates that the interconnect structure is defective, or that other components on the interconnect structure are defective, good electronic devices can be recovered from the defective package. Alternatively, if the electronic device is determined to be defective, the defective device may be removed from the interconnect structure and replaced with a new one.

In one embodiment, the removable layer can have a softening temperature or melting point. The electronic device may be recovered from the interconnect structure by heating the removable layer to its softening temperature or melting point. At this temperature, the electronic device to be released or removed from the base insulating layer and interconnect structure can be recovered. The removable layer is exposed to a heat source that softens or melts the removable layer. Using this technique, the interconnect structure can be peeled off from the electronic device because the electronic device is firmly fixed by the holding device. Suitable holding devices may use vacuum or mechanical clamps. The claim can hold the edge of the interconnect structure and remove or fill the interconnect structure from the electronic device.

The removable layer allows the electronic device to recover without damaging the electronic device or the device on its active surface. This is particularly useful in emerging semiconductor devices that use low K (dielectric constant) interlayer dielectrics because they are damaged with low mechanical forces.

In another removal method, the interconnect structure can be mounted in the heating step, where the secondary heating source provides localized heating to the electronic device and the area surrounding the device. The removable layer is heated to its softening temperature or to its melting point. If the removable layer comprises a thermoplastic or thermoset polymer, the removable layer can be softened or melted by exposing the removable layer to a temperature determined by the material properties of the polymer. Suitable temperature ranges may be in the range of about 250 ° C to about 350 ° C.

If a functional and intact electronic device is separated from the poor basic insulating layer, the melting point of the removable layer should be lower than the maximum damage threshold temperature of the electronic device. The maximum damage threshold temperature of an electronic device is the maximum temperature at which the electronic device can be exposed without damage (including any circuits above it). Alternatively, if one wishes to remove a poor electronic device from a functional and undamaged base insulating layer, the melting point temperature of the removable layer should be lower than the maximum damage threshold temperature of the base insulating layer. The maximum damage threshold temperature of the base insulation layer (including any of the above circuits above) is the maximum temperature at which the base insulation layer can be exposed without damaging the components. Thus, from the interconnect structure, the defective electronic device or any defective remaining components can be removed.

In one embodiment, the interconnect structure uses an array of solder spheres having a relatively fine pitch (about 50 μm to about 1000 μm) to electrically connect the electronic device to the base insulating layer to define and form the interconnect structure. Flip chip or chip size electronic devices. The removable layer must be applied prior to underfill application, otherwise the solder attached to the electronic device cannot be easily removed after underfill curing when defects are found prior to underfill curing and must be removed. The underfill can encapsulate the solder spheres after they reflow, and electrically connect the electronic device to the interconnect structure solder pads. Thus, the underfill is bonded to the removable layer rather than the substrate. Application of the removable layer below the electronic device mounting area allows removal of the electronic device after underfill curing has occurred.

In one embodiment, the interconnect structure may be mounted in the heating step. The secondary heating source provides local heating for the electronic device and the area surrounding the device. Solder connections that attach the removable layer and electronic device to the interconnect structure are heated to their softening or melting point. This releases the removable layer and the electronic device and allows the thermosetting resin underfill to remain completely intact while the electronic device is removed from the mounting area. The previous mounting area can be cleaned to remove residue or debris. Finally, new electronic devices with solder spheres can be mounted on the interconnect structure, soldered and underfilled to complete the replacement of the defective component.

If the electronic device is electrically attached to the interconnect structure by solder connections such as solder balls or electrically conductive polymer lead, the electrical connections and removable layers are heated to the melting or softening point to remove the electronic device from the interconnect structure. Should be. The physical connection between the electronic device and the interconnect structure formed by the electrically conductive polymer material may be heated to melt or soften the conductive material to release the electronic device. Alternatively, if possible, such electrical connections may be physically destroyed after the removable layer has melted or softened.

Chip-on-Flex, plastic high density interconnect (HDI), and high I / O count processor chips may benefit from using the embodiments disclosed herein. In a chip-on-flex process, complex interconnect structures must be fabricated after the electronic device is bonded to the base insulating layer. This is complicated by the number of layers required to route multiple chip I / O pads and the complexity required by each interconnect layer. It may have a defect rate per interconnect structure of about 2% to about 10%. Unless a rework process is possible, the resulting loss of complex interconnect structure risks increasing the manufacturing cost of the process chip. Recovery by one or more of the disclosed methods can be stable at normal operating temperatures and withstand high solder reflow temperatures, but can provide a relatively low stress process for removable bonding if electronic components must be recovered from the interconnect structure. have.

In one embodiment, encapsulation may be postponed until the final processing step to remove the electronic device from the interconnect structure. Inspection of the interconnect structure is performed after the interconnect layer is completed. If it is determined that the interconnect structure and electronic device are free of defects, the area surrounding the electronic device may be encapsulated to further protect the electronic device and interconnect structure from moisture and thermo-mechanical stress. The base insulating layer and the exposed electronic device may be encapsulated using the encapsulation material 70 to fully enclose the base insulating layer and the electronic device (see FIG. 13). In another embodiment, the base insulating layer and the exposed electronic device may be partially encapsulated to embed the base insulating layer and the electronic device (see FIG. 13). In one embodiment, a potting or molding process is used for encapsulation. Suitable molding processes may include pour molding, transition molding or compression molding. Preferably, a dam and fill encapsulation method is used.

Encapsulation materials that can be used include thermoplastic polymers and thermosetting resin polymers. Suitable aliphatic and aromatic polymers include polyetherimide, acrylate, polyurethane, polypropylene, polysulfone, polytetrafluoroethylene, epoxy, benzocyclobutene (BCB), room temperature vulcanizable (RTV) silicone and urethane, polyimide, polyether Mid, polycarbonate, silicone, and the like. In one embodiment, the encapsulation material is a thermoset resin polymer having a relatively low curing temperature. The encapsulation material may comprise a filler material. The type, size and amount of the fatigue material can be used to adjust various molding material properties such as thermal conductivity, coefficient of thermal expansion, viscosity and adsorption amount. For example, these materials may include glass, silica, ceramics, silicon carbide, alumina, aluminum nitride, boron nitride, gallium or other metals, metal oxides, metal carbides, metal nitrides, or metal silicides. have. Other suitable filler materials may include carbon-based materials.

If a frame panel is used, it may be applied before the attachment of the electronic device (see FIG. 9), after the attachment of the electronic device (see FIG. 10), or after completion of the interconnect assembly (see FIG. 14). In the latter method, the adhesive is applied to the main surface of the frame panel and bonded to the second surface of the interconnect assembly. In all such frame panel-attachment methods, a cap or moat region can exist between the inner edge of each frame panel opening and the outer edge of an electronic device disposed within the opening. This gap may be left unfilled or partially filled using encapsulation material. The gap between the inner edge of the frame panel opening and the outer edge of the electronic device may be partially filled to fill about 10% to about 90%. The encapsulation material can be cured. In certain embodiments, it may be desirable to simultaneously cure the encapsulation material and the adhesive layer.

After the basic insulating layer and the exposed electronic device are encapsulated, a lid / thermal spreader 72 may be bonded to the second surface of the electronic device to provide thermal protection for the electronic device. The lead / thermal injector may be bonded with a thermal interface material (TIM) 74. The lead / thermal injector may be bonded to the second surface of the frame panel using adhesive 76. Alternatively, for higher power devices having between about 5 watts and about 100 watts, the backside of the electronic device may remain exposed to facilitate heat removal or heat dissipation during device operation.

The embodiments described herein are examples of compositions, structures, systems, and methods having devices corresponding to the devices of the invention described in the claims. The described description may enable those skilled in the art to implement and use embodiments having other devices that correspond to the devices of the invention described in the claims. Thus, the scope of the present invention includes compositions, structures, systems and methods that do not differ from the description of the claims, and further includes other structures, systems and methods that differ slightly from the representations of the claims. Although only certain features and embodiments are shown and described herein, various modifications and changes will be apparent to those skilled in the art. The appended claims cover all such changes and modifications.

1A-1D are side cross-sectional views of an electronic device bonded to a base insulating layer in accordance with an embodiment of the present invention.

2 (a) to 2 (c) are side cross-sectional views of an electronic device bonded to a base insulating layer according to another embodiment of the present invention.

3 (a) to 3 (d) are side cross-sectional views of an electronic device bonded to a base insulating layer according to another embodiment of the present invention.

4A-4D are side cross-sectional views of an electronic device bonded to a base insulating layer in accordance with another embodiment of the present invention.

5A and 5B are cross-sectional side views of an electronic device bonded to a base insulating layer according to another embodiment of the present invention.

6 (a) and 6 (b) are side cross-sectional views of an electronic device bonded to a base insulating layer according to another embodiment of the present invention.

Figure 7 (a) is a plan view of the frame panel.

Figure 7 (b) is a side cross-sectional view of the frame panel.

8 (a) and 8 (b) are side cross-sectional views of a frame panel bonded to a base insulating layer according to another embodiment of the present invention.

8C is a side cross-sectional view of an electronic device disposed in a frame panel on a basic insulating layer according to another embodiment of the present invention.

9A-9D are side cross-sectional views of an electronic device bonded to a base insulating layer and disposed within a frame panel in accordance with another embodiment of the present invention.

10 (a) to 10 (d) are side cross-sectional views of an electronic device and a frame panel bonded to a base insulating layer according to another embodiment of the present invention.

11A-11D are side cross-sectional views of via formation and metallization of a base insulating layer in accordance with an embodiment of the present invention.

12 (a) and 12 (b) are side cross-sectional views of additional basic insulating layers bonded to interconnect layers in accordance with another embodiment of the present invention.

12 (c) and 12 (d) are side cross-sectional views of via formation and metallization of additional basic insulating layers in accordance with another embodiment of the present invention.

13 is a side cross-sectional view of an interconnect assembly made in accordance with another embodiment of the present invention.

Claims (10)

As an electronic component, A basic insulating layer having a first surface and a second surface, An electronic device having a first surface and a second surface and secured to said base insulating layer, An adhesive layer disposed between the first surface of the electronic device and the second surface of the basic insulating layer; A removable layer disposed between the first surface of the electronic device and the second surface of the basic insulating layer, The base insulating layer is secured to the electronic device through the removable layer, the removable layer being capable of releasing the base insulating layer from the electronic device at a sufficiently low threshold temperature. Electronic component. The method of claim 1, The removable layer loses sufficient mechanical force at the threshold temperature so that the electronic device can be retrived from the base insulating layer without damaging the electronic device. Electronic component. The method of claim 1, I / O contacts on the first surface or the second surface of the electronic device, Further comprising an electrical conductor positioned on the first surface or the second surface of the basic insulating layer, The I / O contact is in electrical communication with the electrical conductor Electronic component. The method of claim 1, The removable layer includes a plurality of sub-layers that can be delaminated from each other to remove the electronic device from the basic insulating layer. Electronic component. The method of claim 1, The removable layer was released at a temperature below about -50 ° C. Electronic component. The method of claim 1, The adhesive layer may be b-stage (b-stageable), The adhesive layer has a curing temperature lower than the melting temperature of the removable layer. Electronic component. The method of claim 1, Further comprising a barrier coating disposed between the removable layer and the adhesive layer. Electronic component. The method of claim 1, Further comprising an electrical connection structure, The electrical connection structure, At least one via extending from the first surface of the basic insulating layer to an I / O contact on the first surface of the electronic device, An electrically conductive material disposed within at least a portion of the via and extending through the via to the I / O contact on the electronic device; Electronic component. The method of claim 1, Further comprising a frame panel having a first surface, a second surface and at least one opening for an electronic device region on the base insulating layer, The first surface of the frame panel is fixed to the second surface of the basic insulating layer Electronic component. The method of claim 1, The electronic device is a semiconductor chip Electronic component.

Images