KR20100051933A - Vertical light emitting diode and manufacturing method of the same - Google Patents

Abstract

PURPOSE: A vertical light emitting diode for improving external quantum efficiency and a method for manufacturing the same are provided to reduce a leakage current by forming a plurality of passivation layers with different insulating materials. CONSTITUTION: A p-type electrode(250) is formed on a silicon substrate(300). A first passivation layer(220) is formed on the both end of the p-type electrode. A second passivation layer(221) is formed on the inner side of the first passivation layer. A light emitting unit(240) is formed by successively depositing an n-type semiconductor layer, an active layer and a p-type semiconductor layer on the p-type electrode. An n-type electrode(260) is formed on a part of the n-type semiconductor layer. The first passivation layer and the second passivation layer are based on different insulating materials.

Description

Vertical Light Emitting Diode and Manufacturing Method for Improving External Quantum Efficiency

The present invention relates to a vertical structure light emitting diode, and more particularly, to form a plurality of passivation layers made of different series materials to reduce the leakage current as much as possible to improve the external quantum efficiency to improve the external quantum efficiency vertical The present invention relates to a structured light emitting diode and a method of manufacturing the same.

A light emitting diode (LED) is a semiconductor light emitting device that converts electrical energy into light energy, and emits light by flowing current through a compound semiconductor terminal and combining light with electrons and holes in a p-n junction or in an active layer.

The light emitting diode can realize various colors by adjusting the composition ratio of the compound semiconductor. The light conversion efficiency is low, the power consumption is low, and the lifespan reaches 10,000 to 50,000 hours, and the response time when the light is turned on and off is fast. In addition, it can be integrated in various forms as a point light source, and can be made in a small size, so that it is possible to design elaborately and be environmentally friendly. Currently, light emitting diodes are expanding their application range to large outdoor billboards and backlights of liquid crystal displays.

The light emitting diodes are mainly made of III-V compound semiconductors. Since gallium nitride compound semiconductor (GaN) has high thermal stability and wide band gap, it has attracted much attention in the development of high power electronic component devices including LEDs.

1 shows a general structure of a conventional vertical light emitting device.

Referring to FIG. 1, a conventional vertical light emitting device includes a p-type electrode 60, a p-type semiconductor layer 20, an active layer 30, and an n-type semiconductor layer 40 on a metal or silicon support layer 10. ) Are sequentially stacked, and the n-type electrode 70 is in electrical contact with a portion of the surface of the n-type semiconductor layer 40. In addition, a passivation layer 50 made of an insulating material is formed on the sidewall of the light emitting device to prevent leakage of current through the sidewall.

When a voltage is applied between the p-type electrode 60 and the n-type electrode 70, electrons are injected from the n-type electrode 70 to the n-type semiconductor layer 40, and the p-type semiconductor from the p-type electrode 60. Holes are injected into layer 20. Electrons and holes meet and recombine in the active layer 30 to generate light, and the generated light passes through the n-type semiconductor layer 40 and is emitted to the outside through its surface.

In a conventional process, an undoped gallium nitride (GaN) layer is epitaxially grown on a sapphire substrate using a method such as LPE, MBE, MOVPE, and the like to sequentially n-type semiconductor layer 40, active layer 30 and After stacking the p-type semiconductor layer 20, a trench is formed by dry etching or wet etching the grown layers using a photolithography process.

Due to such an etching process, each layer of the etched cutting surface causes serious lattice damage, and is subjected to several photolithography and etching processes, resulting in a high process cost and a reduction in production yield. In addition, in order to solve this problem, a heat treatment process may be performed during the process, but not all of the lattice damages can be recovered by this method.

In addition, in the conventional process, the silicon substrate is bonded after undergoing various processes. At this time, each layer grown on the sapphire substrate forms a structure having a step of several micrometers in thickness. At the level, there were problems in that portions where bonding was not made well. As a result, the chip yield in the wafer is remarkably degraded after the laser lift-off (LLO) process of removing the sapphire substrate with a laser. In addition, the process yield between wafer-wafer (wafer to wafer) is also very irregular, there is a disadvantage that the production is not good.

The present invention devised to solve the problems of the prior art as described above for improving the external quantum efficiency to improve the external quantum efficiency by reducing the leakage current to the maximum by forming a plurality of passivation layer made of a different series of materials An object of the present invention is to provide a vertical light emitting diode and a method of manufacturing the same.

In addition, the present invention forms a passivation layer on both ends of the substrate before forming the light emitting portion first to prevent the lattice defects of the light emitting portion, increase the external quantum efficiency to obtain a high luminous efficiency, improve the external quantum efficiency simple manufacturing process Another object is to provide a vertical structure light emitting diode and a method of manufacturing the same.

The object of the present invention is a silicon substrate; A p-type electrode formed on the silicon substrate; First passivation layers formed at both ends of the upper portion of the p-type electrode; A second passivation layer formed by coating on an inner surface of the first passivation layer; A light emitting part formed by sequentially depositing an n-type semiconductor layer, an active layer, and a p-type semiconductor layer on a p-type electrode in a space between the second passivation layers; And it is achieved by a vertical structure light emitting diode for improving the external quantum efficiency including an n-type electrode formed on a portion on the n-type semiconductor layer.

In addition, the first passivation layer and the second passivation layer of the present invention is preferably made of a different series of insulating materials.

In addition, another object of the present invention is a silicon substrate; A p-type electrode on which the metal material is deposited in a plurality of layers, the p-type electrode being formed such that only a predetermined region of both ends of the metal layer positioned at the top thereof is vertically higher in length; First passivation layers formed at both ends of the internal space of the p-type electrode and formed to have the same height as that of both ends of the metal layer positioned at the top; A light emitting part formed by sequentially depositing an undoped n-type semiconductor layer, an n-type semiconductor layer, an active layer and a p-type semiconductor layer on the p-type electrode in the space between the first passivation layer; And it is achieved by a vertical structure light emitting diode for improving the external quantum efficiency including an n-type electrode formed on a portion on the n-type semiconductor layer.

In addition, the inner surface of the first passivation layer of the present invention preferably comprises a second passivation layer is coated with a different series of insulating materials.

In addition, the refractive index of the second passivation layer of the present invention is preferably larger than the refractive index of the first passivation layer.

In addition, the leakage current at the interface of the second passivation layer of the present invention is preferably smaller than the leakage current at the interface of the first passivation layer.

In addition, the first passivation layer or the second passivation layer of the present invention is any one selected from silicon oxide (SiO _x ), silicon nitride (SiN _x ), titanium dioxide (TiO ₂ ) and tantalum oxide film (Ta _x O _y ). It is preferably made of an insulating material.

In addition, the thickness of the first passivation layer of the present invention is preferably 4 to 20㎛, the width is 20 to 500㎛.

In addition, the width of the second passivation layer of the present invention is preferably 1000mm to 10㎛.

In addition, the p-type electrode of the present invention is formed by depositing any one or more metal materials selected from nickel, platinum, silver, and gold in a plurality of layers, and preferably comprises an ohmic contact layer and a reflective film.

In addition, another object of the present invention is a first step of depositing a passivation layer on the sapphire substrate; A second step of patterning the passivation layer by photolithography to form only at both ends of the sapphire substrate; A third step of forming a second passivation layer by coating a material of a different series from the first passivation layer on an inner surface of the first passivation layer; Forming a light emitting part by sequentially depositing an undoped n-type semiconductor layer, an n-type semiconductor layer, an active layer, and a p-type semiconductor layer in a space between the second passivation layers; A fifth step of forming a p-type electrode by depositing a plurality of metal materials on the p-type semiconductor layer; Bonding a silicon substrate to the p-type electrode and removing the sapphire substrate using a laser lift-off process; Removing the undoped n-type semiconductor layer by removing the sapphire substrate; And an eighth step of forming an n-type electrode on the n-type semiconductor layer of the light emitting unit, to achieve a vertical structure light emitting diode for improving external quantum efficiency.

In addition, the first passivation layer or the second passivation layer of the present invention is any one selected from silicon oxide (SiO _x ), silicon nitride (SiN _x ), titanium dioxide (TiO ₂ ) and tantalum oxide film (Ta _x O _y ). It is preferably made of an insulating material of.

In addition, the p-type electrode of the fifth step of the present invention, after depositing nickel and gold sequentially, heat treatment at a temperature of 400 to 900 ℃ to form an ohmic contact layer; Depositing silver on the ohmic contact layer to a thickness of 1000 to 5000 kV to form a reflective film; Sequentially depositing nickel and platinum on the reflective film; And depositing nickel and gold sequentially on the platinum.

In addition, after the fourth step of the present invention, a step of forming a first passivation layer etched and remaining on the sapphire substrate by etching a predetermined region of the opposite surface of the first passivation layer in contact with the light emitting portion. It is preferable to further include.

In addition, the p-type electrode of the fifth step of the present invention, after sequentially depositing nickel and gold to cover the etched region of the upper portion of the light emitting portion and the first passivation layer and the first passivation layer, 400 to 900 Heat treating at a temperature of about 0 ° C. to form an ohmic contact layer; Depositing silver on the ohmic contact layer to a thickness of 1000 to 5000 kV to form a reflective film; Sequentially depositing nickel and platinum on the reflective film; And after depositing nickel on the platinum layer, depositing gold.

In addition, the nickel, gold, platinum of the present invention is preferably deposited to a thickness of less than 10nm.

In addition, the metal material of the present invention is preferably deposited by any one selected from the e-beam deposition, thermal deposition, electroplating deposition and electroless plating deposition.

In addition, after the third step of the present invention, it is preferable to further include the step of adjusting the step by wet or dry etching the extra passivation layer in accordance with the height of the light emitting portion.

In addition, the eighth step of the present invention preferably uses an etching process using plasma.

Accordingly, the vertical light emitting diode and its manufacturing method for improving the external quantum efficiency according to the present invention are remarkably improved by reducing the leakage current as much as possible by forming a plurality of passivation layers made of different materials. It has a beneficial effect.

In addition, the vertical light emitting diode and its manufacturing method for improving the external quantum efficiency of the present invention by forming a passivation layer on both ends of the substrate before forming the light emitting portion can prevent the lattice defects of the light emitting portion to increase the luminous efficiency of the chip There is a remarkable and advantageous effect.

In addition, the vertical structure light emitting diode and its manufacturing method for improving the external quantum efficiency of the present invention can reduce the number of photoresist film used in the manufacturing process can reduce the manufacturing cost, can increase the production yield of the chip by a simple manufacturing process That has a significant and beneficial effect.

The terms or words used in this specification and claims are not to be construed as being limited to their ordinary or dictionary meanings, and the inventors may appropriately define the concept of terms in order to best describe their invention. It should be interpreted as meaning and concept corresponding to the technical idea of the present invention based on the principle that the present invention.

Therefore, the embodiments described in the specification and the drawings shown in the drawings are only the first preferred embodiment of the present invention and do not represent all of the technical idea of the present invention, which can be replaced at the time of the present application It should be understood that there may be various equivalents and variations.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Vertical structure light emitting diode for improving external quantum efficiency according to the first embodiment of the present invention is a silicon substrate 300, the first passivation layer 220, the second passivation layer 221, the light emitting unit 240, p-type And an electrode 250 and an n-type electrode 260.

The silicon substrate 300 uses a high-doped conductive substrate, and a gold / tin alloy containing less than 30% of nickel (Ni) and tin (Sn) having a thickness of 5 to 10 nm is deposited thereon.

In the first embodiment of the present invention, the silicon substrate 300 is used, but the present invention is not limited thereto, and other hetero substrates such as GaAs, GaP, AlGaINP, Ge, SiSe, GaN, AlInGaN, and InGaN may be used instead of the silicon substrate. .

The first passivation layer 220 and the second passivation layer 221 may be any one selected from silicon oxide (SiO _x ), silicon nitride (SiN _x ), titanium dioxide (TiO ₂ ), and tantalum oxide layer (Ta _x O _y ). It is made of an insulating material and is formed at both ends of the silicon substrate to protect the light emitting part. At this time, the thickness (h) of the passivation layer 220 is 4 to 20㎛, the width (a) is formed to 20 to 500㎛, the width (b) of the second passivation layer 221 is formed to 1000 ~ 10㎛ This is preferred.

The first passivation layer 220 and the second passivation layer 221 are made of different series of insulating materials. The refractive index of the second passivation layer 220 should be relatively larger than that of the first passivation layer 220, and the leakage current of the second passivation layer 220 at the interface with other materials will be higher than that of the first passivation layer. It should be relatively small compared to 220). For example, when the first passivation layer 220 is formed of silicon oxide, silicon nitride is used to form the second passivation layer 221.

As described above, the reason why the second passivation layer 221 is further deposited on the portion of the first passivation layer 220 which is in contact with the light emitting part 240 is the leakage current flowing in the portion which is in contact with the light emitting part 240. To make it as small as possible. Since the first passivation layer 220 and the second passivation layer 221 serving as the insulating layer are additionally added, a light emitting diode having a better external quantum efficiency can be manufactured.

In order to smoothly drive the LED, the thickness of the light emitting unit 240 should be 4 μm or more. In the present invention, the thickness of the light emitting part 240 is determined according to the thickness of the first passivation layer 220. When the thickness of the first passivation layer 220 is thin, the light emitting part is spread along the first passivation layer 220 when the light emitting part 240 is formed. Therefore, in the present invention, the first passivation layer 220 is formed to have a thickness of 4 μm or more.

In the light emitting unit 240, an n-type semiconductor layer 242, an active layer 243, and a p-type semiconductor layer 244 are sequentially deposited in a space between the second passivation layer 221 and formed of a nitride-based semiconductor compound. It is desirable to be.

The n-type semiconductor layer 242 preferably uses an n-GaN compound semiconductor as a GaN-based nitride compound semiconductor. In addition, the n-type semiconductor layer 242 may have a concave-convex pattern formed on the surface, thereby reflecting the light generated from the active layer 243 at the surface concave-convex patterned interface.

As the p-type semiconductor layer 244, a p-GaN compound semiconductor doped with a p-type conductive impurity is preferably used as the GaN-based nitride compound semiconductor.

The active layer 243 is a material layer in which light is generated by recombination of carriers such as electron-hole pair recombination when an electric field is applied to the light emitting diode device, and is formed of a quantum well (QW) structure of InGaN / GaN. . In addition, materials such as AlGaN and AlInGaN may also be used as the active layer. In addition, the active layer may have a plurality of quantum well structures formed in order to improve luminance, thereby forming a multi quantum well (MQW) structure.

The p-type electrode 250 is formed by depositing a plurality of layers of metal materials such as nickel (Ni), platinum (Pt), silver (Ag), and gold (Au). The p-type electrode 250 includes an ohmic contact layer 253 and a reflective film 254, and nickel (Ni) formed on the reflective film 254 to prevent diffusion of the silicon substrate and tin (Sn). , A platinum (Pt) layer, and a gold (Au) layer deposited on the upper portion with a thickness of about 1 μm.

The ohmic contact layer 253 may be formed by sequentially depositing nickel (Ni) and gold (Au). In addition, it may be formed of any suitable material such as ruthenium / gold (Ru / Au), nickel / gold (Ni / Au), or indium-tin-oxide (ITO). At this time, nickel and gold is preferably deposited to a thickness of less than 10nm. In addition, the ohmic contact layer 253 is heat-treated at a temperature of about 400 to 900 ℃ to improve the ohmic contact characteristics.

The reflective film 254 is formed by depositing silver (Ag) on the ohmic contact layer 253 to a thickness of 1000 to 5000 GPa. The reflective film 254 reflects the light emitted from the light emitter 240 so that the light can be effectively emitted. In addition to silver, the reflective film 254 may use a material having high reflectivity such as aluminum (Al).

The n-type electrode 260 is formed in a portion of the n-type semiconductor layer 242, and a metal material such as Ti / Al is used as the n-type electrode.

2 to 15 are cross-sectional views illustrating a method of manufacturing a vertical light emitting diode device according to a first embodiment of the present invention.

First, referring to FIG. 2, the first passivation layer 220 is formed by depositing silicon oxide (SiOx) or silicon nitride (SiNx) on the sapphire substrate 210. In this case, when the thickness of the first passivation layer 220 is thin, the metal material is spread along the first passivation layer 220 when the light emitting unit 240 is formed. It is preferable to form so that it may have thickness or more.

3, the photoresist layer 230 is formed such that a pattern remains only at left and right ends of the first passivation layer 220, and as shown in FIG. 4, the patterned photoresist layer 230 is used as a mask to form a first passivation layer ( 220 is patterned to remain only at the left and right ends of the sapphire substrate 210 using a photolithography process and an etching process.

Then, as shown in FIG. 5, the second passivation layer 221 is formed by coating a material of a different series from the first passivation layer on the inner surface of the patterned first passivation layer 220. Here, the width of the second passivation layer 221 is formed to about 1000 ~ 10㎛.

Next, as illustrated in FIG. 6, the light emitter 240 is formed in a space between the second passivation layers 221. First, after the undoped n-type semiconductor layer 241 is grown, the n-type semiconductor layer 242, the active layer 243, and the p-type semiconductor layer 244 are sequentially epitaxially grown.

At this time, methods such as organometallic vapor deposition (MOCVD), molecular beam growth (MBE), hydride vapor deposition (HVPE) and the like can be used.

The undoped n-type semiconductor layer 241 is made of a GaN-based nitride compound, and may be formed to a thickness of about 2 to 3 μm. In addition, the n-type semiconductor layer 242 is made of an n-GaN compound semiconductor, may be formed to a thickness of about 2 to 3㎛, the p-type semiconductor layer 244 is made of a p-GaN compound semiconductor, approximately 0.1 It may be formed to a thickness of about 0.3㎛. In addition, the active layer 243 may be formed to a thickness of about 0.1 to 0.2㎛.

As such, when the first passivation layer 220 and the second passivation layer 221 are formed first, and then the light emitting part 240 is formed in the space therebetween, the side surface of the light emitting part can be prevented from being damaged. When the metal material constituting the type electrode 250 is deposited, the metal material is generally formed to be wide, so that the bonding may be performed well when bonding to the silicon substrate.

Then, as illustrated in FIG. 7, the step of etching the first passivation layer 220 and the second passivation layer 221 by the wet or dry etching method according to the height of the light emitting unit 240 may be further included. have.

Next, as shown in FIG. 8, a metal material is sequentially deposited on the p-type semiconductor layer 244 to form the p-type electrode 250. First, nickel (Ni, 251) is deposited to a thickness of 10 nm or less for ohmic contact, and gold (Au, 252) is deposited to a thickness of 10 nm or less to form an ohmic contact layer 253. Then, heat treatment is performed at a temperature of 400 to 900 ° C, preferably 400 to 600 ° C to improve ohmic contact.

If the thickness of nickel (Ni, 251) and gold (Au, 252) exceeds 10 nm, the light generated from the light emitting unit is not reflected, and is absorbed by these layers, and thus the thickness of 10 nm or less should be formed.

Next, as shown in FIG. 9, silver (Ag) is deposited to a thickness of 1000 to 5000 kPa to form a reflective film 254 layer. Then, nickel (Ni, 255) and platinum (Pt, 256) are sequentially deposited on the reflective layer 254 to a thickness of 10 nm or less, in order to prevent diffusion of the silicon substrate and tin (Sn) to be bonded later. to be. Finally, nickel (Ni, 257) is deposited on platinum (Pt, 256), and gold (Au, 258) is deposited to a thickness of about 1 μm, thereby completing the p-type electrode 250. Here, nickel (Ni, 257) serves as an adhesive to deposit gold (Au, 258) well on the platinum (Pt, 256) layer.

Each metal material constituting the p-type electrode 250 is preferably deposited using an electro-beam deposition or thermal deposition, or electrolytic plating or electroless plating. In addition, processes such as sputtering, chemical vapor deposition, laser deposition, and hydride vapor deposition (HVPE), which are conventional metal layer growth processes, may be used.

Next, as shown in FIG. 10, the silicon substrate 300 is bonded to the p-type electrode 250 by applying heat and pressure.

Since the silicon substrate 300 serves as an electrode, it is preferable to use a high doped conductive substrate.

In addition, the silicon substrate 300 is washed with HF solution to remove the active oxygen layer on the surface, and deposited nickel (Ni, 310) to a thickness of 5 to 10nm, gold / tin containing 30% or less of tin It is desirable to prepare the (Au / Sn) alloy 320 by deposition.

Next, as shown in FIG. 11, the sapphire substrate 210 is separated and removed from the light emitting unit 240, which is preferably separated using a laser lift-off (LLO) process. When the laser light is irradiated onto the sapphire substrate 210, local heat is generated at the interface between the sapphire substrate 210 and the light emitting part 240, and the surface of the light emitting part 240 made of gallium nitride is formed by the heat. The sapphire substrate 210 is easily separated while being decomposed and melted with nitrogen gas.

Next, as shown in FIG. 12, the undoped n-type semiconductor layer 241 is removed by removing the sapphire substrate 210. At this time, since the plasma etching method is used, the first passivation layer 220 and the second passivation layer 221 beside the undoped n-type semiconductor layer 241 are also etched together. In addition, a portion of the n-type semiconductor layer 242 exposed as the undoped n-type semiconductor layer 241 is etched is also etched to form a rough pattern on the surface. Such surface irregularities may improve the efficiency of ohmic contact. In addition, the light generated from the active layer can be reflected at the surface-treated patterned interface.

Next, as shown in FIG. 13, an n-type electrode 260 is formed on the n-type semiconductor layer 242 of the light emitting unit 240. As the n-type electrode 260, a metal material such as Ti / Al is used.

Finally, as shown in FIG. 14, unnecessary portions next to the light emitting diodes are diced and removed to complete the light emitting diode elements according to the first embodiment of the present invention as shown in FIG.

[Other Embodiments]

The vertical light emitting diode according to another embodiment of the present invention is the same as the vertical light emitting diode according to the first embodiment of the silicon substrate 300, the first passivation layer 220, the second passivation layer 221, the light emitting unit ( 240, a p-type electrode 250, and an n-type electrode 260. The second passivation layer 221 may not be formed.

Only predetermined regions of both ends of the metal layer 251 positioned at the top of the p-type electrode 250 are formed to be vertically higher in length, and the first passivation layer 220 and the light emitting unit 240 are formed therein. This is different from the first embodiment in that respect.

16 to 21 are cross-sectional views illustrating a method of manufacturing a vertical light emitting diode according to a second embodiment of the present invention.

2 to 7 are the same as in the first embodiment.

Next, as shown in FIG. 16, a predetermined region of the first surface of the first passivation layer 220 on the opposite surface of the first passivation layer 220 in contact with the light emitting unit 240 is etched. At this time, the first passivation layer 220 and the remaining sapphire substrate exposed by etching becomes a stepped form.

Next, as shown in FIG. 17, a p-type electrode is formed to cover the etched region 240, the upper portion of the first passivation layer 220, and the second passivation layer 221 and the first passivation layer. Nickel (251, 251) is deposited. That is, due to this process, the light emitting part 240, the first passivation layer 220, and the second passivation layer 221 are surrounded by a nickel layer.

When the metal material is deposited on the surface of the first passivation layer 220, the metal material serves to reflect the light generated by the light emitting unit 240, thereby increasing the light intensity of the light emitting diode. It has the advantage of being.

Then, as in the manufacturing method of the first embodiment, gold is deposited to a thickness of 10 nm or less to form an ohmic contact layer 253.

18 to 21 are the same as those described with reference to FIGS. 10 to 13 of the first embodiment, and thus will not be described in detail herein.

Thus, as shown in FIG. 21, the vertical light emitting diode according to the second embodiment of the present invention is completed.

FIG. 22 illustrates a vertical light emitting diode in which the second passivation layer 221 is not formed.

Although the present invention has been shown and described with reference to the preferred embodiments as described above, it is not limited to the above embodiments and those skilled in the art without departing from the spirit of the present invention. Various changes and modifications will be possible.

1 is a cross-sectional view of a conventional vertical structure light emitting diode,

2 to 15 are manufacturing process diagrams of the vertical structure light emitting diode according to the first embodiment of the present invention;

16 to 22 is a manufacturing process of the vertical structure light emitting diode according to another embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

210: sapphire substrate 220: first passivation layer

221: second passivation layer 230: photosensitive film

240: light emitting unit 250: p-type electrode

260 n-type electrode 300 silicon substrate

Claims (21)

Silicon substrates; A p-type electrode formed on the silicon substrate; First passivation layers formed at both ends of the upper portion of the p-type electrode; A second passivation layer formed by coating on an inner surface of the first passivation layer; A light emitting part formed by sequentially depositing an n-type semiconductor layer, an active layer, and a p-type semiconductor layer on a p-type electrode in a space between the second passivation layers; And An n-type electrode formed on a portion of the n-type semiconductor layer Vertical structure light emitting diode for improving external quantum efficiency, including. The method of claim 1, The first passivation layer and the second passivation layer is a vertical structure light emitting diode for improving the external quantum efficiency made of a different series of insulating materials. Silicon substrates; A p-type electrode on which the metal material is deposited on the silicon substrate in a plurality of layers, wherein only a predetermined region of both ends of the metal layer positioned at the top thereof is vertically higher in length; First passivation layers formed at both ends of the internal space of the p-type electrode and formed to have the same height as that of both ends of the metal layer positioned at the top; A light emitting part formed by sequentially depositing an undoped n-type semiconductor layer, an n-type semiconductor layer, an active layer and a p-type semiconductor layer on the p-type electrode in the space between the first passivation layer; And An n-type electrode formed on a portion of the n-type semiconductor layer Vertical structure light emitting diode for improving external quantum efficiency, including. The method of claim 3, wherein A vertical structure light emitting diode for improving external quantum efficiency further comprising a second passivation layer coated on the inner surface of the first passivation layer with a different series of insulating materials. The method according to claim 2 or 4, And a refractive index of the second passivation layer is greater than an index of refraction of the first passivation layer. The method according to claim 2 or 4, And a leakage current at an interface of the second passivation layer is less than a leakage current at an interface of the first passivation layer. The method according to claim 2 or 4, The first passivation layer or the second passivation layer is made of an insulating material of any one selected from silicon oxide (SiO _x ), silicon nitride (SiN _x ), titanium dioxide (TiO ₂ ), and tantalum oxide layer (Ta _x O _y ). Vertical structure light emitting diode for quantum efficiency improvement. The method according to claim 1 or 3, The thickness of the first passivation layer is 4 to 20㎛, the width is 20 to 500㎛ vertical structure light emitting diode for improving the external quantum efficiency. The method according to claim 1 or 4, The width of the second passivation layer is a vertical structure light emitting diode for improving the external quantum efficiency of 1000 ~ 10㎛. The method according to claim 1 or 3, The p-type electrode is formed by depositing one or more metal materials selected from nickel, platinum, silver, and gold in a plurality of layers, and includes a ohmic contact layer and a reflective film, and has a vertical structure light emitting diode for improving external quantum efficiency. Depositing a passivation layer on the sapphire substrate; A second step of patterning the passivation layer by photolithography to form only at both ends of the sapphire substrate; A third step of forming a second passivation layer by coating a material of a different series from the first passivation layer on an inner surface of the first passivation layer; Forming a light emitting part by sequentially depositing an undoped n-type semiconductor layer, an n-type semiconductor layer, an active layer, and a p-type semiconductor layer in a space between the second passivation layers; A fifth step of forming a p-type electrode by depositing a plurality of metal materials on the p-type semiconductor layer; Bonding a silicon substrate to the p-type electrode and removing the sapphire substrate using a laser lift-off process; A seventh step of removing the undoped n-type semiconductor layer by removing the sapphire substrate; And An eighth step of forming an n-type electrode on the n-type semiconductor layer of the light emitting unit Method of manufacturing a vertical structure light emitting diode for improving the external quantum efficiency comprising a. The method of claim 11, The first passivation layer or the second passivation layer is made of an insulating material of any one selected from silicon oxide (SiO _x ), silicon nitride (SiN _x ), titanium dioxide (TiO ₂ ), and tantalum oxide layer (Ta _x O _y ). A method of manufacturing a vertical light emitting diode for improving quantum efficiency. The method of claim 11, The thickness of the first passivation layer is 4 to 20㎛, the width is 20 to 500㎛ the manufacturing method of the vertical structure light emitting diode for improving the external quantum efficiency for improving the external quantum efficiency. The method of claim 11, The width of the second passivation layer is 1000Å to 10㎛ manufacturing method of a vertical structure light emitting diode for improving the external quantum efficiency. The method of claim 11, The p-type electrode of the fifth step, Depositing nickel and gold sequentially, followed by heat treatment at a temperature of 400 to 900 ° C. to form an ohmic contact layer; Depositing silver on the ohmic contact layer to a thickness of 1000 to 5000 kV to form a reflective film; Sequentially depositing nickel and platinum on the reflective film; And Sequentially depositing nickel and gold on the platinum Method of manufacturing a vertical structure light emitting diode for improving the external quantum efficiency formed, including. The method of claim 11, After the fourth step, Etching a predetermined area of the opposite surface of the first passivation layer in contact with the light emitting part to form a first passivation layer etched and remaining with the sapphire substrate in a stepwise manner to improve external quantum efficiency. Method of manufacturing a diode. The method of claim 16, The p-type electrode of the fifth step, Sequentially depositing nickel and gold to cover the light emitting portion, the upper portion of the first passivation layer, and the etched regions of the first passivation layer, and then heat-treating at a temperature of 400 to 900 ° C. to form an ohmic contact layer; Depositing silver on the ohmic contact layer to a thickness of 1000 to 5000 kV to form a reflective film; Sequentially depositing nickel and platinum on the reflective film; And Depositing nickel on the platinum layer and depositing gold Method of manufacturing a vertical structure light emitting diode for improving the external quantum efficiency comprising a. The method of claim 15 or 17, The nickel, gold, platinum is a manufacturing method of a vertical structure light emitting diode for improving the external quantum efficiency is deposited to a thickness of less than 10nm. The method of claim 15 or 17, The metal material is a manufacturing method of a vertical structure light emitting diode for improving the external quantum efficiency is deposited by any one selected from the e-beam deposition, thermal deposition, electroplating deposition and electroless plating deposition. The method of claim 11, After the third step, the method of manufacturing a vertical structure light emitting diode for improving the external quantum efficiency further comprising the step of adjusting the step by wet or dry etching the extra passivation layer in accordance with the height of the light emitting portion. The method of claim 11, The eighth step is a method of manufacturing a vertical structure light emitting diode for improving the external quantum efficiency using an etching process using a plasma.

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