KR20100050882A - Semiconductor device - Google Patents

Abstract

PURPOSE: A semiconductor device is provided to change current consumption of a circuit by changing a swing width of a signal swinging in a CML(Current Mode Logic) domain and a size of a sinking current supplied to an output node. CONSTITUTION: A frequency detector(300) detects the frequency of the input signal. A CML buffering part(320) implements the buffering for swing the input signal in the CML domain. According to the output signal of the frequency estimator, the swing width of the CML domain and the size of the biasing current are changed. The CML buffering part comprises a signal input part(322) changing the potential level of a signal outputted through the CML output node.

Description

Semiconductor device {SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design techniques, and more particularly, to a semiconductor device having a circuit used to generate or transmit a signal swinging in the CML region, and more particularly, in a CML region according to an operating frequency of the semiconductor device. A semiconductor device capable of varying the amount of current consumed in a circuit used to generate or transmit a swinging signal.

In general, a signal swinging in a current mode logic (CML) region is used for an input / output (I / O) interface of a signal having a high frequency such as a clock in a semiconductor device.

Here, the CML region means a potential range of a predetermined range defined by a predetermined direct current (DC) potential level or a potential range of a predetermined range defined by an average potential level determined by a predetermined criterion, and swings in a CML region. The signal refers to a signal that toggles between the highest potential level Vmax of the CML region and the lowest potential level Vmin of the CML region at a predetermined frequency based on the potential level that is a reference in the CML region.

For example, even if the power supply voltage (VDD) level of the predetermined device for inputting / outputting a signal swinging in the CML area is 1.5 (V) and the ground voltage (VSS) level is 0 (V), It can be defined as 1.5 (V) to 1.0 (V), the reference potential level of the CML region is 1.25 (V), the signal swinging in the CML region is a swing width of 0.5 (V) relative to 1.25 (V) It is a signal toggling at a predetermined frequency with a swing range.

As mentioned above, the CML region is a region of the region compared to the potential level region due to the difference between the power supply voltage (VDD) level and the ground voltage (VSS) level of a predetermined device for inputting / outputting a swinging signal in the CML region. The size is designed to be relatively small, and the reason for this design is that the signal swinging in the CML region is a clock signal having a high frequency.

That is, the CML region is a region defined for stably transmitting even in the case of a clock signal (Clock) having a very high frequency of Giga Hertz or several tens of Giga Hertz.

For reference, since a signal swinging in the CML region is generally toggled to a small swing width at a high frequency, a phase distortion or a potential level fluctuates due to noise generated during transmission. It is more likely to occur. Therefore, when transmitting a swinging signal in the CML domain, a differential signal is divided into two signals having phases opposite to each other.

1 is a diagram illustrating a circuit used to generate or transmit a signal swinging in a CML area included in a semiconductor device according to the related art.

Referring to FIG. 1, a circuit 100 for generating or transferring signals CML_SIG and CML_SIGb swinging in a CML region in a semiconductor device according to the related art is in response to a positive input signal INPUT_SIG applied through a gate. The first NMOS transistor N1 for controlling the amount of current I1 flowing between the drain-source connected sub-output node OUT_NDb and the common node COMN and the sub-input signal INPUT_SIGb received through the gate. In response, the second NMOS transistor N2 for adjusting the amount of current I2 flowing between the drain-source connected positive output node OUT_ND and the common node COMN, and the CML bias voltage CML_BIAS input through the gate. Of sinking current I3 flowing out of the common node COMN by adjusting the amount of current I3 flowing between the drain-source connected common node COMN and the ground voltage VSS terminal. Third NMOS to Adjust Amount It is connected between the transistor N3, the power supply voltage VDD terminal, the positive output node OUT_ND, and the power supply voltage VDD terminal, and the negative output node OUT_ND, and outputs the positive output node OUT_ND and the negative output node OUT_ND. The first and second resistors R1 and R2 having the same predetermined resistance values for adjusting the swing widths of the signals CML_SIG and CML_SIGb swinging in the CML region are provided.

An operation of the circuit 100 for generating or transferring signals CML_SIG and CML_SIGb swinging in the CML region in the semiconductor device according to the above-described configuration will be described below.

First, the input positive input signal INPUT_SIG and the negative input signal INPUT_SIGb have phases opposite to each other. In addition, the CML bias voltage CML_BIAS always has a potential level corresponding to logic 'high'. Therefore, the third NMOS transistor N3 is always turned on to always draw a certain amount of current from the common node COMN to the ground voltage VSS terminal.

In this state, when the potential level of the positive input signal INPUT_SIG rises and the first NMOS transistor N1 is turned on, the potential level of the sub-input signal INPUT_SIGb decreases to lower the second NMOS transistor N2. Turned off, and accordingly, a predetermined amount of current I1 continuously flows from the negative output node OUT_NDb to the common node COMN, but the current flows from the positive output node OUT_ND to the common node COMN. (I2) does not flow.

That is, the amount of current I1 flowing from the negative output node OUT_NDb to the common node COMN is equal to the amount of current I3 flowing from the common node COMN to the ground voltage VSS terminal.

As a result, the potential level of the negative signal CML_SIGb swinging in the CML region output through the negative output node OUT_NDb is lowered, and the positive signal CML_SIG swinging in the CML region output through the positive output node OUT_ND. ), The potential level increases.

On the contrary, when the potential level of the positive input signal INPUT_SIG is lowered to turn off the first NMOS transistor N1, the potential level of the negative input signal INPUT_SIGb is raised to turn on the second NMOS transistor N2. The current I1 does not flow from the negative output node OUT_NDb to the common node COMN, but a predetermined amount of current I2 flows from the positive output node OUT_ND to the common node COMN. It flows continuously.

That is, the amount of current I2 flowing from the positive output node OUT_ND to the common node COMN is equal to the amount of current I3 flowing from the common node COMN to the ground voltage VSS terminal.

As a result, the potential level of the negative signal CML_SIGb swinging in the CML region output through the negative output node OUT_NDb becomes high, and the positive signal CML_SIG swinging in the CML region output through the positive output node OUT_ND. The potential level of is lowered.

In this case, the degree of decrease in the potential level of the signals CML_SIG and CML_SIGb swinging in the CML region may vary depending on the magnitudes of the first resistor R1 and the second resistor R2, which is a signal swinging in the CML region. The degree to which the potential level of (CML_SIG, CML_SIGb) is lowered is continuously passed from the power supply voltage (VDD) terminal through the positive output node (OUT_NDb) or the negative output node (OUT_ND) to the ground voltage (VSS) terminal. Current I1 or I2 passes through the first resistor R1 and the first NMOS transistor N1 and the third NMOS transistor N3 or the second resistor R2 and the second NMOS transistor N2 and the third NMOS transistor N3. This is because it may vary depending on the amount of potential changes.

Specifically, the first NMOS transistor N1 and the third NMOS transistor N3 are subsequently turned on by the input signals INPUT_SIG and INPUT_SIGb and the CML bias voltage CML_BIAS, or the second NMOS transistor N2 is turned on. Even if the third NMOS transistor N3 is subsequently turned on, the third NMOS transistor N3 may be in a state having a very small resistance component due to the turned on state.

Therefore, the potential level of the signals CML_SIG and CML_SIGb swinging in the CML region is a voltage distribution formed by passing the current I1 between the first resistor R1, the first NMOS transistor N1, and the third NMOS transistor N3. In accordance with the law or the voltage distribution law formed while the current I2 passes between the second resistor R2, the second NMOS transistor N2, and the third NMOS transistor N3.

At this time, since the magnitudes of the first resistor R1 and the second resistor R2 are the same, the larger the magnitude of the first resistor R1 and the second resistor R2 is, the larger the signal CML_SIG, The potential level of the CML_SIGb becomes relatively close to the level of the ground voltage VSS, and the smaller the size of the first resistor R1 and the second resistor R2 is, the smaller the signal swings in the CML region (CML_SIG, CML_SIGb). ) Is relatively far from the level of the ground voltage (VSS).

That is, as the sizes of the first resistor R1 and the second resistor R2 become larger, the swing widths of the signals CML_SIG and CML_SIGb swinging in the CML region become relatively large, and the first resistor R1 and the first resistor R1 and the second resistor R2 become larger. The smaller the two resistances R2, the smaller the swing width of the signals CML_SIG and CML_SIGb swinging in the CML region.

On the other hand, the degree of increase in the potential level of the signals CML_SIG and CML_SIGb swinging in the CML region is determined in a state in which current does not continuously flow to the first resistor R1 and the second resistor R2, and thus the signal swinging in the CML region When the potential levels of (CML_SIG, CML_SIGb) are high, they are almost at the same level as that of the power supply voltage VDD.

FIG. 2 is a graph showing the amount of current consumed by a circuit used to generate or transmit a swinging signal in a CML region included in the semiconductor device according to the related art shown in FIG.

Referring to FIG. 2, a circuit 100 used to generate or transmit signals CML_SIG and CML_SIGb swinging in a CML region in a semiconductor device according to the related art always provides a constant amount of current regardless of a change in operating frequency. It can be seen that it consumes.

In detail, the circuit 100 used to generate or transmit the signals CML_SIG and CML_SIGb swinging in the CML region will always be described as follows.

First, since the input signals INPUT_SIG and INPUT_SIGb are divided into the positive input signal INPUT_SIG and the negative input signal INPUT_SIGb having phases opposite to each other, the first NMOS transistor N1 operating in response to the input signals INPUT_SIG and INPUT_SIGb. ) And the second NMOS transistor N2 are always controlled so that another one is turned off when one is turned on. That is, the first NMOS transistor N1 and the second NMOS transistor N2 are controlled to perform operations that are opposite to each other.

At this time, since the sizes of the first NMOS transistor N1 and the second NMOS transistor N2 are the same, the signals CML_SIG and CML_SIGb that swing in the CML region regardless of whether or not the potential levels of the input signals INPUT_SIG and INPUT_SIGb are fluctuated. The total amount of the current I1 or I2 supplied from the power supply voltage VDD stage to the common node COMN does not change regardless of the potential level.

In addition, since the CML bias voltage CML_BIAS is a signal that always maintains a constant potential level, the third NMOS transistor N3 is always turned on in a state where power is supplied to the semiconductor device. Accordingly, in the third NMOS transistor N3, a constant amount of current I3 can always be subtracted from the common node COMN to the ground voltage VSS terminal.

Thus, whether the potential level of the input signals INPUT_SIG and INPUT_SIGb fluctuates or does not fluctuate, a constant amount of current I1 or I2 is always supplied to the common node COMN, and the ground voltage VSS at the common node COMN. Since the current I3 exiting from the stage is always constant, the potential level of the signals CML_SIG and CML_SIGb swinging in the output CML region will fluctuate as the potential levels of the input signals INPUT_SIG and INPUT_SIGb change. Therefore, the total amount of current consumed is not changed.

For example, the moment the logic level of the positive input signal INPUT_SIG transitions from logic 'low' to logic 'high' or from logic 'high' to logic 'low' Regardless of whether the logic level of the positive input signal INPUT_SIG is maintained at logic 'low' or logic 'high', a certain amount of current is always consumed.

Accordingly, in the circuit 100 used to generate or transmit the signals CML_SIG and CML_SIGb swinging in the CML region, as shown in the drawing, the potential levels of the input signals INPUT_SIG and INPUT_SIGb fluctuate rapidly. A constant amount of current is consumed at all times, whether at high frequencies or at low frequencies.

However, as described above, the circuit 100 used to generate or transmit the signals CML_SIG and CML_SIGb swinging in the CML region is a high frequency state in which the potential level of the input signals INPUT_SIG and INPUT_SIGb varies rapidly. Consuming a constant amount of current at all times, whether at low speed or at low frequency, is very important when the circuit 100 used to generate or deliver signals swinging in the CML region (CML_SIG, CML_SIGb) must operate at high frequencies. This can be a great advantage, but it can be a very big disadvantage when the circuit 100 used to generate or transmit the signals CML_SIG and CML_SIGb swinging in the CML region must operate at a low frequency.

That is, the circuit 100 used to generate or transmit the signals CML_SIG and CML_SIGb swinging in the CML region operates at a low frequency so that a relatively large amount of current is consumed in a state in which a relatively small amount of current is consumed. As a result, when the circuit 100 used to generate or transmit the signals CML_SIG and CML_SIGb swinging in the CML region operates at a low frequency, there is a problem of consuming more current than necessary.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems in the prior art, and has a semiconductor device capable of varying the current consumption of a circuit used to generate or transmit a signal swinging in the CML region according to the operating frequency of the semiconductor device. The purpose is to provide.

According to an aspect of the present invention for achieving the above object, a frequency detector for detecting the frequency of the input signal; And a CML buffering unit configured to buffer the input signal so as to swing in the CML region, wherein a swing width and a biasing current of the CML region vary according to an output signal of the frequency detector.

In addition, according to another aspect of the present invention for achieving the above object to be solved, the frequency detection unit for detecting the frequency of the input signal; A buffering unit for buffering the input signal to swing in the CML region and applying the buffer to the CML output node; A loading unit for varying a load resistance value of a CML output node in response to an output signal of the frequency detector; And a sinking unit for varying a magnitude of a sinking current provided to the CML output node in response to an output signal of the frequency detector.

In the above-described present invention, a CML region generated by detecting an operating frequency of a semiconductor device and varying a load resistance value connected to an output node of a circuit used to generate or transmit a signal swinging in a CML region according to a detection result is provided. By changing the swing width of the swinging signal and the magnitude of the sinking current supplied to the output node, the circuit used to generate or transmit the swinging signal in the CML region according to the operating frequency of the semiconductor device. There is an effect of varying the current consumption.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be configured in various different forms, only this embodiment is intended to complete the disclosure of the present invention and to those skilled in the art the scope of the present invention It is provided to inform you completely.

[First Embodiment]

3 is a diagram illustrating a circuit used to generate or transmit a signal swinging in a CML area included in a semiconductor device according to a first embodiment of the present invention.

Referring to FIG. 3, a circuit used to generate or transmit a signal swinging in a CML region included in a semiconductor device according to a first embodiment of the present invention may detect a frequency of an input signal INPUT_SIG and INPUT_SIGb. Buffering the frequency detector 300 and the input signals INPUT_SIG and INPUT_SIGb to swing in the CML region, but swinging and biasing the CML region according to the output signals EN_HIGH and EN_LOW of the frequency detector 300. The CML buffering unit 320 may vary in magnitude of the current.

Here, the CML buffering unit 320 determines the potential levels of the signals CML_SIG and CML_SIGb swinging in the CML region output through the CML output nodes OUT_ND and OUT_NDb corresponding to the potential levels of the input signals INPUT_SIG and INPUT_SIGb. According to the signal input unit 322 for fluctuating and the output signals EN_HIGH and EN_LOW of the frequency detector 300, the CML is changed by varying the magnitude of the resistance connected between the power supply voltage VDD and the CML output nodes OUT_ND and OUT_NDb. The swing width changing unit 324 for changing the swing width of the signals CML_SIG and CML_SIGb swinging in the CML region output through the output nodes OUT_ND and OUT_NDb, and the output signals EN_HIGH and EN_LOW of the frequency detector 300. A current amount change unit 326 for varying the sinking driving force of the CML output nodes OUT_ND and OUT_NDb.

In addition, the signal input unit 322 among the components of the CML buffering unit 320 may correspond to the potential level of the positive input signal INPUT_SIG applied through the positive input node IN_ND through the secondary CML output node OUT_NDb. The positive CML output node OUT_ND corresponding to the potential level of the first signal input unit 3222 for changing the potential level of the output signal CML_SIGb and the negative input signal INPUT_SIGb applied through the negative input node IN_NDb. And a second signal input part 3224 for varying the potential level of the signal CML_SIG output through the CML_SIG.

At this time, the first signal input unit 3322 is connected to the source of the drain CML output node OUT_NDb connected in drain in response to the potential level of the positive input signal INPUT_SIG applied through the positive input node IN_ND connected to the gate. And an NMOS transistor N1 for varying the potential level of the signal CML_SIGb output through the sub CML output node OUT_NDb by adjusting the magnitude of the current flowing to the common node COMN.

In addition, the second signal input unit 3224 is connected to the source of the positive CML output node OUT_ND drain-connected in response to the potential level of the sub-input signal INPUT_SIGb applied through the sub-input node IN_NDb connected to the gate. The NMOS transistor N2 is configured to vary the potential level of the signal CML_SIG output through the positive CML output node OUT_ND by adjusting the magnitude of the current flowing to the common node COMN.

The swing width variation unit 324 of the components of the CML buffering unit 320 is connected in parallel between the power supply voltage VDD stage and the CML output nodes OUT_ND and OUT_NDb, and each of which has a predetermined resistance value. According to the resistors R0A, R1A, R2A, R0B, R1B, and R2B, and the output signals EN_HIGH and EN_LOW of the frequency detector 300, the power supply voltage VDD stage and the respective resistor elements R0A, R1A, R2A, and R0B. , R1B, R2B are provided with a plurality of switching units 3422A, 3242B, 3242C, 3244A, 3244B, 3244C for selectively on / off control of the connection.

In this case, the plurality of resistors R0A, R1A, R2A, R0B, R1B, and R2B and the plurality of switching units 3422A, 3242B, 3242C, 3244A, 3244B, and 3244C are symmetrical to each other (R0A, R1A, R2A / R0B). Are divided into R1B, R2B and 3242A, 3242B, 3242C / 3244A, 3244B, and 3244C, respectively, between the supply voltage (VDD) and the negative CML output node (OUT_NDb), and between the supply voltage (VDD) and the positive CML output node (OUT_ND). Is provided. That is, among the plurality of resistors R0A, R1A, R2A, R0B, R1B, and R2B and the plurality of switching units 3422A, 3242B, 3242C, 3244A, 3244B, and 3244C, the plurality of first resistors R0A, R1A, R2A ) And a plurality of first switching units (3242A, 3242B, and 3242C) are provided between the power supply voltage (VDD) terminal and the sub CML output node OUT_NDb to swing the signal CML_SIGb output through the sub CML output node OUT_NDb. The width varies, and the plurality of second resistors R0B, R1B, and R2B and the plurality of second switching units 3244A, 3244B, and 3244C are provided between the power supply voltage VDD stage and the positive CML output node OUT_ND. Therefore, the swing width of the signal CML_SIG output through the positive CML output node OUT_ND is varied.

In addition, the plurality of switching units 3422A, 3242B, 3242C, 3244A, 3244B, and 3244C are respectively connected to the plurality of drains in response to the output signals EN_HIGH and EN_LOW of the frequency detector 300 respectively applied to the plurality of gates. A plurality of NMOS transistors N3, N4, N5, and N6 for controlling the connection of a plurality of resistors R0A, R1A, R2A, R0B, R1B, and R2B connected to a plurality of power supply voltage VDD stages and a plurality of sources, respectively. , N7, N8).

For reference, some of the plurality of switching units 3242A, 3242B, 3242C, 3244A, 3244B, and 3244C may use the CML enable signal (not the output signals EN_HIGH and EN_LOW) of the frequency detector 300. In response to EN_CML), the operation is controlled on / off. In this case, the CML enable signal EN_CML is a signal that is unconditionally activated to logic 'High' when the CML buffering unit 320 operates. This signal is defined in (Mode Register Set: MRS).

The current amount fluctuation part 326 among the components of the CML buffering part 320 respectively sinks currents I_SINKA, I_SINKB, and I_SINKC of predetermined magnitudes in response to a bias voltage VBIAS having a predetermined potential level. Sinking drivers 3262A, 3262B, and 3262C for providing the CML output nodes OUT_ND and OUT_NDb, and the respective sinking drivers 3262A, 3262B, according to the output signals EN_HIGH and EN_LOW of the frequency detector 300, respectively. A plurality of operation controllers 3264A, 3264B, and 3264C are provided for selectively turning on / off the 3262C.

At this time, the plurality of sinking drivers 3262A, 3262B, and 3262C drive the common node COMN to the ground voltage VSS to connect the CML output node connected to the common node COMN at a predetermined timing through the signal input unit 322. The sinking currents I_SINKA, I_SINKB, and I_SINKC are supplied to (OUT_ND, OUT_NDb). In addition, the plurality of operation control units 3264A, 3264B, and 3264C allow the plurality of sinking drivers 3262A, 3262B, and 3262C to be selectively connected to the common node COMN, thereby being common to the CML output nodes OUT_ND and OUT_NDb. The size of the sinking currents I_SINKA, I_SINKB, and I_SINKC flowing through the node COMN to the ground voltage VSS terminal is adjusted.

In addition, the plurality of sinking drivers 3262A, 3262B, and 3262C may be connected to the plurality of intermediate nodes MCOMNA, MCOMNB, and MCOMNC respectively connected to the plurality of drains in response to the bias voltages VBIAS applied to the plurality of gates, respectively. A plurality of NMOS transistors N10, N12, and 14 are provided to adjust the magnitude of each sinking current I_SINKA, I_SINKB, I_SINKC flowing between ground voltages VSS connected to a plurality of sources, respectively.

In addition, the plurality of operation controllers 3264A, 3264B, and 3264C are connected to the plurality of drains, respectively, in response to the output signals EN_HIGH and EN_LOW of the frequency detector 300 respectively applied to the plurality of gates. ) And a plurality of NMOS transistors N9, N11, 13 for selectively controlling the connection of the plurality of intermediate nodes MCOMNA, MCOMNB, MCOMNC connected to the plurality of sources, respectively.

For reference, some of the operation controllers 3264A, 3264B, and 3264C may operate in response to the CML enable signal EN_CML rather than the output signals EN_HIGH and EN_LOW of the frequency detector 300. The CML enable signal EN_CML is a signal defined in the mode register set MRS as a signal that is unconditionally activated to logic 'high' when the CML buffering unit 320 operates. to be.

The frequency detector 300 may include a pulse generator 302 for generating an enable pulse DETECTION_PUL having a predetermined activation period, and an input signal INPUT_SIG and INPUT_SIGb in the activation period of the enable pulse DETECTION_PUL. In response to the counting unit 304 for counting the number of toggles and the output signals A0, A1, A2, A3, A4 and A5 of the counting unit 304, the logic level of the frequency detection signals EN_HIGH and EN_LOW is determined. And a logic level determining unit 306 for determining.

In addition, among the components of the frequency detector 300, the pulse generator 302 activates the enable pulse DETECTION_PUL in response to the detection enable signal DETECTION_EN defined in the mode register set MRS being activated. Deactivate the enable pulse DETECTION_PUL after the scheduled time has elapsed.

In addition, the counting unit 304 among the components of the frequency detector 300 may include a binary output code having a predetermined number of bits each time the input signals INPUT_SIG and INPUT_SIGb are toggled in the activation period of the enable pulse DETECTION_PUL. A0, A1, A2, A3, A4, A5) are incremented by '1' and output, and the binary output code (A0, A1, A2, A3) consisting of a plurality of predetermined bits in response to the disable period of the enable pulse DETECTION_PUL. , A4, A5) are kept in the initial state and output.

In addition, among the components of the frequency detector 300, the logic level determiner 306 is an upper part of the binary output codes A0, A1, A2, A3, A4, and A5 composed of a plurality of bits output from the counting unit 304. When N bits (N is a natural number, in this case A0 and A1 are assumed to be 2, A0 and A1) are all '0', the high frequency detection signal EN_HIGH among the frequency detection signals EN_HIGH and EN_LOW is deactivated and output. Since the upper N + M bits (N, M are natural numbers, in this case N, M are 2) of binary output codes (A0, A1, A2, A3, A4, A5) consisting of a plurality of bits output from the unit 304, A0 , A1, A2, and A3), if the values are all '0', the low frequency detection signal EN_LOW among the frequency detection signals EN_HIGH and EN_LOW is deactivated and output.

At this time, the logic level determining unit 306, the upper N bits (N is a natural number, here N) of the binary output code (A0, A1, A2, A3, A4, A5) consisting of a plurality of bits output from the counting unit 304 Since it is assumed to be 2, A0 and A1) are respectively input, and the output signal of the first NOR1 and the first NOR1 NOR1 for the negative logic sum and the output are received and the phase is inverted to detect the high frequency. The first inverter INV1 for outputting as the signal HIGH_FREQ and the high frequency detection signal HIGH_FREQ output from the first inverter INV1 are received and the phase is inverted to output the inverted signal EN_HIGHb of the high frequency detection signal. The second inverter INV2 and the third inverter INV3 for outputting the high frequency detection signal EN_HIGH and outputting the high frequency detection signal EN_HIGH, and the binary output code A0, which includes a plurality of bits output from the counting unit 304. Highest N bits of A1, A2, A3, A4, A5 (N is a natural number, female The first NOR gate (NOR1) for receiving and ORing the next M bits (M is a natural number, in this case A2 and A3 because M is 2 because N is assumed to be 2) is N0. ) And a first NAND gate for receiving the AND signal of the fourth inverter INV4, the output signal of the first NOA gate NOR1, and the output signal of the fourth inverter INV4, and outputting the result as a low frequency detection signal LOW_FREQ. NAND1) and the fifth inverter INV5, the high frequency detection signal HIGH_FREQ output from the first inverter INV1 and the low frequency detection signal LOW_FREQ output from the fifth inverter IN5 are input, and are negatively logic-summed to detect low frequency. A third NOR gate NOR3 and a sixth inverter INV6 for outputting the signal as an inverted signal EN_LOWb and inverting the phase again to output the low frequency detection signal EN_LOW are provided.

An operation of a circuit used to generate or transmit a swinging signal in a CML area included in the semiconductor device according to the first embodiment of the present invention will be described below.

First, when the frequency of the input signals INPUT_SIG and INPUT_SIGb has a higher frequency than the predetermined first frequency, the frequency detector 300 may logic both the high frequency detection signal EN_HIGH and the low frequency detection signal EN_LOW. And print it out. In addition, the frequency detector 300 may include a high frequency detection signal when the frequency of the input signals INPUT_SIG and INPUT_SIGb is lower than the predetermined first frequency and is higher than the predetermined second frequency, which is lower than the predetermined first frequency. EN_HIGH is deactivated to logic 'low' and output, and low frequency detection signal EN_LOW is activated to logic 'high' and output. In addition, the frequency detector 300 may logic 'low' both the high frequency detection signal EN_HIGH and the low frequency detection signal EN_LOW when the frequencies of the input signals INPUT_SIG and INPUT_SIGb have a frequency lower than the predetermined second frequency. To disable the output.

That is, the frequency detector 300 detects the frequency units of the input signals INPUT_SIG and INPUT_SIGb by appropriately adjusting the logic levels of the output signals EN_HIGH and EN_LOW according to the frequencies of the input signals INPUT_SIG and INPUT_SIGb. In this case, in the first embodiment of the present invention, only the high frequency detection signal EN_HIGH and the low frequency detection signal EN_LOW are output from the frequency detector 300, but this is for convenience of description and more detection signals are actually output. The frequency unit of the input signal INPUT_SIG and INPUT_SIGb may be output to detect more precisely.

In addition, the counting unit 304 among the components of the frequency detector 300 may toggle the input signals INPUT_SIG and INPUT_SIGb several times during the predetermined activation period of the enable pulse DETECTION_PUL output from the pulse generator 302. The frequency of the input signals INPUT_SIG and INPUT_SIGb is detected by counting the information. That is, since the enable pulse DETECTION_PUL always has a fixed activation interval with a predetermined length, the input signal INPUT_SIG and INPUT_SIGb is greater than the predetermined value when the counting number of the toggle signals of the input signals INPUT_SIG and INPUT_SIGb is greater than the predetermined value. If the frequency is high and the counted value is smaller than the predetermined value, it is possible to determine that the input signals INPUT_SIG and INPUT_SIGb are low frequencies.

When the high frequency detection signal EN_HIGH and the low frequency detection signal EN_LOW output from the frequency detector 300 are logic 'high', the CML buffering unit 320 may determine the input signal INPUT_SIG and INPUT_SIGb. Since the frequency is a very large frequency having a value greater than the first frequency, the swing width of the signals CML_SIG and CML_SIGb swinging in the CML region output through the CML output nodes OUT_ND and OUT_NDb is the predetermined first swing width. It is operated to have a swing width of the signals (CML_SIG, CML_SIGb) swinging in the CML region is very small, and the biasing current is operated to have a predetermined first size to sink in the CML output nodes (OUT_ND, OUT_NDb). The amount of current to be made must be very large.

Specifically, the high frequency detection signal EN_HIGH in the logic 'high' state and the low frequency detection signal EN_LOW in the logic 'high' state in the frequency detector 300 are components of the CML buffering unit 320. When input to the swing width fluctuation part 324, the plurality of switching parts 3322A, 3242B, 3242C, 3244A, 3244B, and 3244C provided in the swing width fluctuation part 324 are all activated to provide a plurality of resistance elements R0A, R1A, R2A, R0B, R1B, R2B) is directly connected to the power supply voltage (VDD) stage. At this time, a plurality of resistors R0A, R1A, R2A, R0B, R1B, and R2B are connected to the power supply voltage (VDD) stage. Since the CML output nodes (OUT_ND, OUT_NDb) are connected in parallel, the resistance between the power supply voltage (VDD) and the CML output nodes (OUT_ND, OUT_NDb) becomes the minimum size, and therefore the CML output nodes (OUT_ND, The swing widths of the signals CML_SIG and CML_SIGb swinging in the CML region output through OUT_NDb become the minimum size.

In addition, the high frequency detection signal EN_HIGH in the logic 'high' state and the low frequency detection signal EN_LOW in the logic 'high' state are included in the CML buffering unit 320 by the frequency detector 300. When inputted to the current amount change unit 326, the plurality of operation control units 3264A, 3264B, and 3264C provided in the current amount change unit 326 are all activated so that the plurality of sinking drivers 3326A, 3262B, and 3262C each have a predetermined size. The sinking currents I_SINKA, I_SINKB, and I_SINKC are supplied to the CML output nodes OUT_ND and OUT_NDb, which causes the CML output nodes OUT_ND and OUT_NDb to pass through the common node COMN to the ground voltage VSS terminal. The magnitude of the sinking current flowing in is equal to the maximum size (I_SINKA + I_SINKB + I_SINKC).

The CML buffering unit 320 is input when the high frequency detection signal EN_HIGH output from the frequency detector 300 is logic 'low' and the low frequency detection signal EN_LOW is logic 'high'. Since the frequency of the signals INPUT_SIG and INPUT_SIGb is smaller than the first frequency but has a larger value than the second frequency-less than the first frequency, the CML output through the CML output nodes OUT_ND and OUT_NDb. The swing width of the signals swinging in the area (CML_SIG, CML_SIGb) is operated to have a predetermined second swing width-greater than the first swing width so that the swing widths of the signals swinging in the CML area (CML_SIG, CML_SIGb) are of medium size. In addition, the biasing current must be operated to have a predetermined second magnitude-less than the first magnitude-so that the magnitude of the current sinking in the CML output nodes OUT_ND and OUT_NDb is medium.

Specifically, in the frequency detector 300, the high frequency detection signal EN_HIGH in the logic 'low' state and the low frequency detection signal EN_LOW in the logic 'high' state are components of the CML buffering unit 320. If the input is input to the swing width fluctuation part 324, some of the plurality of switching parts (3242A, 3242B, 3242C, 3244A, 3244B, 3244C) provided in the swing width fluctuation part (324) (3242A, 3242B, 3244A, 3244B). Is activated and the remaining parts 3324C and 3244C are deactivated so that only some of the resistors R0A, R1A, R0B, and R1B of the plurality of resistors R0A, R1A, R2A, R0B, R1B, and R2B are supplied to the power supply voltage VDD. The resistors R0A, R1A, R0B, and R1B are connected directly to the stages, since the power supply voltages are connected in parallel between the power supply voltage VDD and the CML output nodes OUT_ND and OUT_NDb. The resistance level between the (VDD) stage and the CML output nodes (OUT_ND, OUT_NDb) is of medium size, which is output through the CML output nodes (OUT_ND, OUT_NDb). A swing width of the signal (CML_SIG, CML_SIGb) to swing in CML area is to be a medium size.

In addition, the high frequency detection signal EN_HIGH in the logic 'low' state and the low frequency detection signal EN_LOW in the logic 'high' state are included in the CML buffering unit 320 by the frequency detector 300. When inputted to the current amount varying unit 326, some of the plurality of operation control units 3264A, 3264B, and 3264C provided in the current amount varying unit 326 (3264A, 3264B) are activated and the remaining part (3264C) is deactivated. Only some of the sinking drivers 3262A, 3262B, and 3262C (3262A, 3262B) will each supply a sinking current (I_SINKA, I_SINKB) of a predetermined magnitude to the CML output nodes (OUT_ND, OUT_NDb), thereby causing a CML output node. The magnitude of the sinking current flowing from the (OUT_ND, OUT_NDb) to the ground voltage VSS terminal through the common node COMN becomes an intermediate size (I_SINKA + I_SINKB).

When the high frequency detection signal EN_HIGH and the low frequency detection signal EN_LOW output from the frequency detector 300 are logic 'low', the CML buffering unit 320 outputs the input signals INPUT_SIG and INPUT_SIGb. Since the frequency is a very small frequency with a smaller value than the second frequency-less than the first frequency-the swing width of the signals (CML_SIG, CML_SIGb) swinging in the CML area output through the CML output nodes OUT_ND and OUT_NDb. The swing width of the signals CML_SIG and CML_SIGb swinging in the CML region is greatly increased by operating the predetermined third swing width, which is greater than the second swing width, and the biasing current has a predetermined second magnitude. It should be operated to have smaller than -1 so that the amount of current sinking in the CML output nodes (OUT_ND, OUT_NDb) is very small.

Specifically, the high frequency detection signal EN_HIGH in the logic 'low' state and the low frequency detection signal EN_LOW in the logic 'low' state in the frequency detector 300 are components of the CML buffering unit 320. When the input is input to the swing width fluctuation part 324, some of the plurality of switching parts 3322A, 3242B, 3242C, 3244A, 3244B, and 3244C included in the swing width fluctuation part 324 are activated, and the rest is activated. Some 3324B, 3242C, 3244B, and 3244C are inactivated so that only some of the resistors R0A, R1A, R2A, R0B, R1B, and R2B are directly connected to the power supply voltage VDD stage. At this time, the resistance magnitude between the power supply voltage VDD terminal and the CML output nodes OUT_ND and OUT_NDb, in which only some of the resistor elements R0A and R0B remain, becomes the minimum size, and thus the CML output node OUT_ND. The swing widths of the signals CML_SIG and CML_SIGb swinging in the CML region output through OUT_NDb become the minimum size.

In addition, the high frequency detection signal EN_HIGH in the logic 'low' state and the low frequency detection signal EN_LOW in the logic 'low' state are included in the CML buffering unit 320. When inputted to the current amount varying unit 326, some of the plurality of operation control units 3264A, 3264B, and 3264C provided in the current amount varying unit 326 (3264A) are activated and the remaining portions (3264B, 3264C) are deactivated. Only some of the sinking drivers 3262A, 3262B, and 3262C 3326A will supply a sinking current I_SINKA of a predetermined size to the CML output nodes OUT_ND and OUT_NDb, which causes the CML output nodes OUT_ND and OUT_NDb. The sinking current flowing through the common node COMN to the ground voltage VSS stage becomes a minimum size I_SINKA.

For reference, the swing width of the signals CML_SIG and CML_SIGb swinging in the CML area output through the CML output nodes OUT_ND and OUT_NDb, and the sinking current I_SINKA and SINK supplied to the CML output nodes OUT_ND and OUT_NDb. The size of I_SINKB, I_SINKC) must be inversely proportional to allow the CML buffering unit 320 to operate normally.

For example, a signal swinging in the CML region output through the CML output nodes OUT_ND and OUT_NDb because the frequencies of the INPUT_SIG and INPUT_SIGb detected by the frequency detector 300 are very high frequencies having a value greater than the first frequency. If the swing width of (CML_SIG, CML_SIGb) should be very small, the sinking currents (I_SINKA, I_SINKB, I_SINKC) supplied to the CML output nodes OUT_ND, OUT_NDb have small values. The signals CML_SIG and CML_SIGb swinging in the CML region output through the CML output nodes OUT_ND and OUT_NDb do not swing the predetermined potential level range, but swing a potential level range that is less than the normal swing waveform. A swinging wave can be generated.

The signal CML_SIG swings in the CML region output through the CML output nodes OUT_ND and OUT_NDb because the frequencies of the INPUT_SIG and INPUT_SIGb detected by the frequency detector 300 are very small and have a value smaller than the second frequency. Even if the swing width of CML_SIGb is very large, even if the sinking current (I_SINKA, I_SINKB, I_SINKC) supplied to the CML output nodes OUT_ND, OUT_NDb has a large value, the CML output The signals CML_SIG and CML_SIGb swinging in the CML region output through the nodes OUT_ND and OUT_NDb may generate a normal swing waveform, but waste current that does not need to be used as pointed out in the prior art.

As described above, according to the first embodiment of the present invention, a load resistor connected to an output node of a circuit used to generate or transmit a signal swinging in a CML region according to a result of detecting an operating frequency of a semiconductor device. By varying the value, the swing width of the signal swinging in the generated CML region can be varied.

In addition, the magnitude of a sinking current supplied to an output node of a circuit used to generate or transmit a signal swinging in the CML region may vary according to a result of detecting an operating frequency of the semiconductor device.

By simultaneously performing these two operations, the magnitude of the current used in the circuit used to generate or transmit a signal swinging in the CML region can be varied according to the operating frequency of the semiconductor device.

[Second Embodiment]

4 is a diagram illustrating a circuit used to generate or transmit a signal swinging in a CML area included in a semiconductor device according to a second embodiment of the present invention.

Referring to FIG. 4, a circuit used to generate or transmit a signal swinging in a CML area included in a semiconductor device according to a second embodiment of the present invention may be configured to detect frequencies of input signals INPUT_SIG and INPUT_SIGb. A frequency detector 400, a buffering unit 420 for buffering the input signals INPUT_SIG and INPUT_SIGb in the CML region to apply to the CML output nodes OUT_ND and OUT_NDb, and an output signal of the frequency detector 400. In response to EN_HIGH and EN_LOW, the CML output node (e.g., the loading unit 440 for varying the load resistance values of the CML output nodes OUT_ND and OUT_NDb) and the output signals EN_HIGH and EN_LOW of the frequency detector 400 are used. And a sinking unit 460 for varying the magnitude of the sinking current provided to OUT_ND and OUT_NDb.

Here, the buffering unit 420 changes the potential levels of the signals CML_SIG and CML_SIGb swinging in the CML region output through the CML output nodes OUT_ND and OUT_NDb in response to the potential levels of the input signals INPUT_SIG and INPUT_SIGb. Connected between the signal input unit 422 and the power supply voltage VDD terminal and the CML output nodes OUT_ND and OUT_NDb to provide a fixed load resistance value R0 of a predetermined size to the CML output nodes OUT_ND and OUT_NDb. And a sinking for providing a fixed sinking current I_SINKS of a predetermined magnitude to the CML output nodes OUT_ND and OUT_NDb in response to a bias voltage VBIAS having a predetermined potential level. A current providing unit 426 is provided.

In addition, the signal input unit 422 among the components of the buffering unit 420 is output through the sub-CML output node OUT_NDb corresponding to the potential level of the positive input signal INPUT_SIG applied through the positive input node IN_ND. The positive CML output node OUT_ND corresponding to the potential level of the first signal input unit 4222 and the negative input signal INPUT_SIGb applied through the first signal input unit 4202 and the negative input node IN_NDb for changing the potential level of the signal CML_SIGb. And a second signal input part 4224 for changing a potential level of the signal CML_SIG output through the second signal.

At this time, the first signal input unit 4222 is connected to the source of the negative CML output node OUT_NDb connected to the drain in response to the potential level of the positive input signal INPUT_SIG applied through the positive input node IN_ND connected to the gate. And an NMOS transistor N1 for varying the potential level of the signal CML_SIGb output through the sub CML output node OUT_NDb by adjusting the magnitude of the current flowing to the common node COMN.

In addition, the second signal input unit 4224 is connected to a source at the positive CML output node OUT_ND which is drained in response to the potential level of the negative input signal INPUT_SIGb applied through the negative input node IN_NDb connected to the gate. The NMOS transistor N2 is configured to vary the potential level of the signal CML_SIG output through the positive CML output node OUT_ND by adjusting the magnitude of the current flowing to the common node COMN.

According to the output signals EN_HIGH and EN_LOW of the frequency detector 400, the magnitude of the resistor connected between the power supply voltage VDD terminal and the CML output nodes OUT_ND and OUT_NDb is varied to output through the CML output nodes OUT_ND and OUT_NDb. The CML output nodes OUT_ND and OUT_NDb according to the swing width changing unit 424 for changing the swing widths of the signals CML_SIG and CML_SIGb swinging in the CML region, and the output signals EN_HIGH and EN_LOW of the frequency detector 400. And a current amount varying part 426 for varying a sinking driving force.

The fixed loading unit 424 of the components of the buffering unit 420 has a first fixed resistance element having a predetermined resistance value R0 connected between the power supply voltage VDD terminal and the positive CML output node OUT_ND. And a second fixed resistance element R0B having a predetermined resistance value R0 connected between the power supply voltage VDD terminal and the negative CML output node OUT_NDb.

In addition, the sinking current providing unit 426 among the components of the buffering unit 420 may be connected to the drain connected to the common node COMN and the source connected to the ground in response to the bias voltage VBIAS having a predetermined potential level applied to the gate. An NMOS transistor N3 for adjusting the magnitude of the sinking current I_SINKS flowing between the voltage VSS terminals is provided.

In addition, the loading unit 440 is connected in parallel to the fixed loading unit 424 of the components of the buffering unit 420 between the power supply voltage VDD stage and the CML output nodes OUT_ND and OUT_NDb, respectively. According to the plurality of resistors R1A, R2A, R1B, and R2B having a plurality of resistors and the output signals EN_HIGH and EN_LOW of the frequency detector 400, each of the resistors R1A, R2A, R1B, and R2B ) Are provided with a plurality of switches 4402B, 4402C, 4404B, 4404C for selectively on / off control of the connection.

In this case, the plurality of resistance elements R1A, R2A, R1B, and R2B and the plurality of switching units 4402B, 4402C, 4404B, and 4404C are symmetrical to each other (R1A, R2A / R1B, R2B, and 4402B, 4402C, 4404B, and 4404C). Are divided between the power supply voltage VDD and the negative CML output node OUT_NDb and between the power supply voltage VDD and the positive CML output node OUT_ND. That is, among the plurality of resistors R1A, R2A, R1B, and R2B and the plurality of switching units 4402B, 4402C, 4404B, and 4404C, the plurality of first resistors R1A and R2A and the plurality of first switching units 4402B. , 4402C is provided between the power supply voltage VDD terminal and the negative CML output node OUT_NDb, and the signal CML_SIGb outputted through the negative CML output node OUT_NDb by varying the load resistance value of the negative CML output node OUT_NDb. The swing width of the circuit is varied, and the plurality of second resistors R1B and R2B and the plurality of second switching units 4404B and 4404C are disposed between the power supply voltage VDD and the positive CML output node OUT_ND. By varying the load resistance of the CML output node OUT_ND, the swing width of the signal CML_SIG output through the sub CML output node OUT_NDb is varied.

In addition, the plurality of switching units 4402B, 4402C, 4404B, and 4404C respectively supply power voltages connected to the plurality of drains in response to the output signals EN_HIGH and EN_LOW of the frequency detector 400 respectively applied to the plurality of gates. And a plurality of NMOS transistors N4, N5, N7, and N8 for controlling the connection of the plurality of resistors R1A, R2A, R1B, and R2B connected to the VDD stage and the plurality of sources, respectively.

In addition, the sinking unit 460 provides sinking currents I_SINKB and I_SINKC of predetermined magnitudes to the CML output nodes OUT_ND and OUT_NDb in response to a bias voltage VBIAS having a predetermined potential level. A plurality of motion controllers 4604B for selectively on / off control of each of the sinking drivers 4602C and 4602C according to the plurality of sinking drivers 4602C and 4602C and the output signals EN_HIGH and EN_LOW of the frequency detector 400. 4604C).

In this case, the plurality of sinking drivers 4602B and 4602C drive the common node COMN to the ground voltage VSS to control the common node COMN at a predetermined timing through the signal input unit 422 included in the buffering unit 420. It supplies a sinking current (I_SINKB, I_SINKC) to the CML output nodes (OUT_ND, OUT_NDb) that are connected to. Further, the plurality of operation control units 4604B and 4604C allow the plurality of sinking drivers 4602B and 4602C to be selectively connected to the common node COMN, thereby allowing the common node COMN to be used in the CML output nodes OUT_ND and OUT_NDb. It adjusts the magnitude of the sinking current (I_SINKB, I_SINKC) flowing through the ground voltage (VSS) through.

In addition, the plurality of sinking drivers 4602B and 4602C may be connected to the plurality of intermediate nodes MCOMNB and MCOMNC and the plurality of sources respectively connected to the plurality of drains in response to the bias voltages VBIAS respectively applied to the plurality of gates. A plurality of NMOS transistors N12 and 14 are provided to adjust the magnitude of each sinking current I_SINKB and I_SINKC flowing between the connected ground voltages VSS.

In addition, the plurality of operation controllers 4604B and 4604C may include the common node COMN connected to the plurality of drains in response to the output signals EN_HIGH and EN_LOW of the frequency detector 400 respectively applied to the plurality of gates. A plurality of NMOS transistors N11 and 13 are provided for selectively controlling the connection of a plurality of intermediate nodes MCOMNB and MCOMNC respectively connected to a plurality of sources.

The frequency detector 400 may include a pulse generator 402 for generating an enable pulse DETECTION_PUL having a predetermined activation period, and an input signal INPUT_SIG and INPUT_SIGb in the activation period of the enable pulse DETECTION_PUL. In response to the counting unit 404 for counting the number of toggles and the output signals A0, A1, A2, A3, A4 and A5 of the counting unit 404, the logic level of the frequency detection signals EN_HIGH and EN_LOW is determined. And a logic level determining unit 406 for determining.

In addition, among the components of the frequency detector 400, the pulse generator 402 activates the enable pulse DETECTION_PUL in response to the detection enable signal DETECTION_EN defined in the mode register set MRS being activated. Deactivate the enable pulse DETECTION_PUL after the scheduled time has elapsed.

In addition, the counting unit 404 of the components of the frequency detector 400 includes a binary output code consisting of a predetermined number of bits each time the input signals INPUT_SIG and INPUT_SIGb toggle in the activation period of the enable pulse DETECTION_PUL. A0, A1, A2, A3, A4, A5) are incremented by '1' and output, and the binary output code (A0, A1, A2, A3) consisting of a plurality of predetermined bits in response to the disable period of the enable pulse DETECTION_PUL. , A4, A5) are kept in the initial state and output.

In addition, among the components of the frequency detector 400, the logic level determiner 406 is an upper part of the binary output codes A0, A1, A2, A3, A4, and A5 composed of a plurality of bits output from the counting unit 404. When N bits (N is a natural number, in this case A0 and A1 are assumed to be 2, A0 and A1) are all '0', the high frequency detection signal EN_HIGH among the frequency detection signals EN_HIGH and EN_LOW is deactivated and output. Since the upper N + M bits (N, M are natural numbers, in this case N, M are 2) of binary output codes A0, A1, A2, A3, A4, and A5 composed of a plurality of bits output from the unit 404, A0 , A1, A2, and A3), if the values are all '0', the low frequency detection signal EN_LOW among the frequency detection signals EN_HIGH and EN_LOW is deactivated and output.

In this case, the logic level determining unit 406 may include the upper N bits of the binary output codes A0, A1, A2, A3, A4, and A5 composed of a plurality of bits output from the counting unit 404 (N is a natural number, here N). Since it is assumed to be 2, A0 and A1) are respectively input, and the output signal of the first NOR1 and the first NOR1 NOR1 for the negative logic sum and the output are received and the phase is inverted to detect the high frequency. The first inverter INV1 for outputting as the signal HIGH_FREQ and the high frequency detection signal HIGH_FREQ output from the first inverter INV1 are received and the phase is inverted to output the inverted signal EN_HIGHb of the high frequency detection signal. The second inverter INV2 and the third inverter INV3 for inverting the phase and outputting the high frequency detection signal EN_HIGH and the plurality of bits output from the counting unit 404 are outputted. Highest N bits of A1, A2, A3, A4, A5 (N is a natural number, female The first NOR gate (NOR1) for receiving and ORing the next M bits (M is a natural number, in this case A2 and A3 because M is 2 because N is assumed to be 2) is N0. ) And a first NAND gate for receiving and multiplying an output signal of the first inverter gate NOR1 and an output signal of the fourth inverter INV4 and outputting the result as a low frequency detection signal LOW_FREQ. NAND1) and the fifth inverter INV5, the high frequency detection signal HIGH_FREQ output from the first inverter INV1 and the low frequency detection signal LOW_FREQ output from the fifth inverter IN5 are input, and are negatively logic-summed to detect low frequency. A third NOR gate NOR3 and a sixth inverter INV6 for outputting the signal as an inverted signal EN_LOWb and inverting the phase again to output the low frequency detection signal EN_LOW are provided.

The operation of the circuit used to generate or transmit a signal swinging in the CML region included in the semiconductor device according to the second embodiment of the present invention is described in the CML provided in the semiconductor device according to the first embodiment of the present invention. It is almost identical to the operation of the circuit used to generate or deliver the signal swinging in the area.

That is, the load resistance value of the loading unit 420 changes according to the output signals EN_HIGH and EN_LOW of the frequency detector 400, so that the CML region is output through the CML output nodes OUT_ND and OUT_NDb of the buffering unit 420. The swing width of the swing signals CML_SIG and CML_SIGb is changed, and the sinking current magnitude of the sinking unit 460 is changed according to the output signals EN_HIGH and EN_LOW of the frequency detector 400, thereby buffering the buffering unit 420. The same is true in that the magnitude of the biasing current of V varies. Therefore, the operation of the circuit used to generate or transmit a signal swinging in the CML region included in the semiconductor device according to the second embodiment will not be described in detail.

As described above, according to the second embodiment of the present invention, a load resistor connected to an output node of a circuit used to generate or transmit a signal swinging in a CML region according to a result of detecting an operating frequency of a semiconductor device. By varying the value, the swing width of the signal swinging in the generated CML region can be varied.

In addition, the magnitude of a sinking current supplied to an output node of a circuit used to generate or transmit a signal swinging in the CML region may vary according to a result of detecting an operating frequency of the semiconductor device.

By simultaneously performing these two operations, the magnitude of the current used in the circuit used to generate or transmit a signal swinging in the CML region can be varied according to the operating frequency of the semiconductor device.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill.

For example, the logic gate and the transistor illustrated in the above-described embodiment should be implemented differently in position and type depending on the polarity of the input signal.

1 illustrates a circuit used to generate or transmit a signal swinging in a CML region included in a semiconductor device according to the related art.

FIG. 2 is a graph illustrating an amount of current consumed by a change in an operating frequency of a circuit used to generate or transmit a swinging signal in a CML region included in the semiconductor device according to the related art shown in FIG. 1.

3 is a diagram illustrating a circuit used to generate or transmit a signal swinging in a CML region included in a semiconductor device according to a first embodiment of the present invention.

4 is a diagram illustrating a circuit used to generate or transmit a signal swinging in a CML area included in a semiconductor device according to a second embodiment of the present invention.

DESCRIPTION OF THE REFERENCE NUMERALS

100: circuit used to generate or transmit a signal swinging in the CML region

300, 400: frequency detector 320: CML buffering unit

322: signal input unit 324: swing width change unit

326: current variation unit 420: buffering unit

440: loading portion 460: sinking portion

Claims (10)

A frequency detector for detecting a frequency of an input signal; And CML buffering the buffer to swing the input signal in the CML area, the swing width of the CML area and the magnitude of the biasing current changes according to the output signal of the frequency detector A semiconductor device comprising a. The method of claim 1, The CML buffering unit, A signal input unit for varying a potential level of a signal output through a CML output node corresponding to the potential level of the input signal; A swing width changing unit for changing a swing width of a signal output through the CML output node by varying a magnitude of a resistor connected between a power supply voltage terminal and the CML output node according to an output signal of the frequency detector; And And a current amount changer for varying a sinking driving force of the CML output node according to the output signal of the frequency detector. The method of claim 2, The signal input unit, A first signal input unit for changing a potential level of a signal output through the sub-CML output node in response to a potential level of the positive input signal applied through the positive input node; And And a second signal input unit for varying the potential level of the signal output through the positive CML output node in correspondence with the potential level of the sub-input signal applied through the sub-input node. The method of claim 2, The swing width fluctuation part, A plurality of resistors connected in parallel between the power supply voltage stage and the CML output node, each resistor having a predetermined resistance value; And And a switching unit for selectively turning on / off a connection between a power supply voltage terminal and each resistance element in accordance with an output signal of the frequency detector. The method of claim 2, The current amount change unit, A plurality of sinking drivers for providing a sinking current of predetermined magnitude to the CML output node in response to a bias voltage having a predetermined potential level; And And an operation control unit for selectively turning on / off each sinking driver according to an output signal of the frequency detector. The method of claim 1, The frequency detector, A pulse generator for generating an enable pulse having a predetermined activation period; A counting unit for counting the number of toggles of the input signal in the activation period of the enable pulse; And And a logic level determination unit for determining a logic level of the frequency detection signal in response to an output signal of the counting unit. The method of claim 6, The pulse generation unit, And activating the enable pulse in response to the activation of a detection enable signal defined in a mode register set (MRS) and deactivating the enable pulse after a predetermined time has passed. The method of claim 6, The counting unit, Each time the input signal toggles in the enable period of the enable pulse, a binary output code consisting of a predetermined number of bits is incremented by '1', And maintain the binary output code in an initial state in response to an inactivation period of the enable pulse. The method of claim 8, The logic level determination unit, When the upper N bits (N is a natural number) of the binary output code are all '0', the high frequency detection signal of the frequency detection signal is deactivated. And if the upper N + M bits (M is a natural number) of the binary output code are all '0', the low frequency detection signal of the frequency detection signal is inactivated. 10. The method of claim 9, The CML buffering unit, When both the high frequency detection signal and the low frequency detection signal are activated, the CML region is operated to have a predetermined first swing width, and the biasing current is operated to have a predetermined first magnitude. When the high frequency detection signal is deactivated and the low frequency detection signal is activated, the CML region is operated to have a predetermined second swing width-greater than the first swing width and the biasing current is of a predetermined second magnitude. -Less than the first size; When the high frequency detection signal is deactivated and the low frequency detection signal is deactivated, the CML region operates to have a predetermined third swing width, which is greater than the second swing width, and the biasing current is of a predetermined third size. A semiconductor device operable to be smaller than the second size.

Images