KR20100042955A - Muti-level-cell non-volatile memory device using charge trapping region - Google Patents

Abstract

PURPOSE: A multi level cell nonvolatile memory device is provided to overcome interference between devices due to a scale down using a charge trap region to localize and stores a charge. CONSTITUTION: A semiconductor substrate(101) comprises three source/drain regions(105a) per unit cell or more. A charge trapping insulation unit is formed on a semiconductor substrate. The charge trapping insulation unit includes a charge trap region which traps the charge according to the voltage applied to the source/drain region. A gate electrode(150) is formed on the charge trapping insulation unit. The gate electrode has a flat shape of N polygons. The charge trapping region provides a charge trap site which localizes the charge and stores the charge. The source/drain region is arranged on angular points of N polygon formed by the gate electrode.

Description

Multi-level-cell Non-volatile Memory Device Using Charge Trapping Region

FIELD OF THE INVENTION The present invention relates to nonvolatile memory devices, and more particularly to far-level- having a novel structure capable of storing more than three bits per unit cell using charge trap regions in which charge can be stored localized. The present invention relates to a cell nonvolatile memory device.

Rewritable nonvolatile memory devices, such as flash memory, include a charge storage unit called a floating gate between dielectric layers of a conventional MOS structure, and has a characteristic of storing data even when a power supply is cut off. In the conventional flash memory device, polysilicon is mainly used as a floating gate for storing charge. However, due to the difficulty of improving the integration density due to interference between devices, a charge trap type memory device is recently used to replace polysilicon. There is an active research on. The charge trapping memory device includes a memory device having a SONOS structure using a nitride film as a floating gate, and a nano floating gate memory device using a nano structure as charge trap sites.

The performance of a nonvolatile memory device is determined by the data storage capability and the stability and speed of the write and read operations of the data. In the field of nonvolatile memory devices such as flash, the need for high integration is increasing. To this end, efforts have been made to reduce the size of memory devices, but there is a need for a method for preventing deterioration of device characteristics such as short channel effects due to device shrinkage. As another method for high integration, the possibility of a multi-level-cell for implementing a multi-bit operation such as 2 bits in a unit cell has been proposed.

However, the multi-level-cell using a conventional polysilicon floating gate simply divides each state according to the amount of charge stored in the floating gate, which makes it difficult to perform stable data writing and reading operations and complicated operation itself. In addition, although multi-level-cells implemented through trap sites have been proposed, it is difficult to clearly and stably distinguish each data storage state, and data storage of more than 3 bits per unit cell is not efficient or difficult. The charge trapping flash memory device capable of implementing a multi-bit unit cell has a clear limitation when implemented in a conventional MOS structure.

One object of the present invention is to provide a multi-level-cell nonvolatile memory device having a novel structure that efficiently and stably stores data of 3 bits or more per unit cell, thereby contributing to memory density improvement.

According to an aspect of the present invention, there is provided a multi-level-cell nonvolatile memory device, including: a semiconductor substrate on which three or more source / drain regions are formed per unit cell; A charge trapping insulating portion formed on the semiconductor substrate and having a charge trap region trapping charge according to a voltage applied to the source / drain region; And a gate electrode formed on the charge trapping insulation and having a planar shape of an N-angle (N is an integer greater than or equal to 3), wherein the charge trap region can be stored in which charge is localized. And the source / drain regions are disposed at vertices of an N-shape formed by the gate electrode.

The charge trapping insulating unit may include a tunneling insulating layer formed between the semiconductor substrate and the charge trap region; And a blocking insulating layer formed on the tunneling insulating layer.

The nonvolatile memory device selectively localizes charge in a portion of the charge trap region adjacent to the source / drain region (or a vertex portion of an N-angle) according to a voltage applied to the source / drain region. By storing, more than 3 bits of data can be stored per unit cell.

According to an embodiment of the present invention, a unique channel region may be formed in the semiconductor substrate along the sides of the N-angle or along the diagonal of the N-angle.

In an embodiment, the charge trap region may be formed of a plurality of metal nanodots formed on the tunneling insulating layer. The metal nano dot may be formed of a metal selected from gold, silver, nickel, platinum, and ruthenium. According to another embodiment, the charge trap region may be formed of a nitride film providing a charge trap site.

According to an embodiment of the present invention, the gate electrode has a quadrangular planar shape, the source / drain regions are disposed at each vertex of the quadrangular shape, and the nonvolatile memory device stores four bits of data per unit cell. Can be stored.

In another embodiment, the gate electrode may have a hexagonal planar shape, the source / drain regions may be disposed at each vertex of the hexagon, and the nonvolatile memory element may store 6 bits of data per unit cell. .

In another embodiment, the gate electrode has an octagonal planar shape, the source / drain regions are disposed at each vertex of the octagon, and the nonvolatile memory device may store 8 bits of data per unit cell. have.

In another embodiment, the gate electrode has a triangular planar shape, the source / drain regions are disposed at each vertex of the triangle, and the nonvolatile memory device may store 3 bits of data per unit cell. have.

In addition, according to an aspect of the present invention, there is provided a semiconductor substrate including N (N is an integer of 3 or more) source / drain regions formed per unit cell; A tunneling insulating film formed on the semiconductor substrate; A plurality of metal nanodots formed on the tunneling insulating layer and configured to trap charges according to a voltage applied to the source / drain to store localized charges; A blocking insulating film formed on the metal nano dot; And a gate electrode formed on the blocking insulating layer, the gate electrode having a planar shape of an N-angle, wherein the source / drain region is disposed at each vertex of the N-angle, and the plurality of metal nanodots is the N-angle. A multi-level-cell nonvolatile memory device is provided which realizes N-bit data storage per unit cell by localizing and selectively storing charge adjacent to a vertex of.

According to an embodiment of the present invention, N may be selected as an integer of 3 or more and 8 or less.

According to the present invention, various bits can be stably stored in a unit memory cell according to a polygonal gate shape. The present invention saves three or more bits in one memory cell while simultaneously overcoming the limitations of the storage capability of the conventional nonvolatile memory and the inter-device interference that occurs during scale-down. It can greatly improve. It can contribute to the implementation of a flash memory device having high integration and high reliability.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, the embodiments of the present invention may be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below. The shape and the size of the elements in the drawings may be exaggerated for clarity and the same elements are denoted by the same reference numerals in the drawings.

The multi-level-cell of 3 or 4 bits or more proposed by the present invention can be realized by the charge localization characteristic of the charge trap site provided by the metal nano dot or nitride film. In addition, the multi-level-cell has a gate electrode structure having a polygonal (triangular or larger) planar shape, and a plurality of source / drain regions (hereinafter, referred to as semiconductor substrates) overlapping edge portions (vertical portions) of the polygonal gate electrodes. Impurity region serving as a source or a drain is referred to as a 'source / drain region'. The multi-bit structure newly proposed by the present inventors is a structure in which four or more electrodes are associated with the development of three electrodes (source, drain and gate electrodes) of the existing MOS structure, and each bit has various gate plane shapes (from above the gate top surface). As seen from the above figure, the shape is stored in the area corresponding to the vertex of the square, hexagon, octagon, etc.).

1 is a plan view schematically illustrating a unit cell of a multi-level-cell nonvolatile memory device, in particular, a memory device according to an exemplary embodiment of the present invention. A cross-sectional view taken along the line XX 'of FIG. 1 is shown in FIG. 3 is a perspective view schematically illustrating the nonvolatile memory device of FIG. 1 in a three-dimensional structure.

1 to 3, the nonvolatile memory device 100 includes a semiconductor substrate 101 having four source / drain regions 105a, 105b, 105c, and 105d. The source / drain regions 105a to 105d may be, for example, n-doped impurity regions for forming n-channel transistors. Alternatively, as another embodiment, a source / drain of a p-doped impurity region for forming a p-channel transistor may be used.

A charge trapping insulation 140 is formed on the semiconductor substrate 101 for trapping charge and maintaining trapped charges, and a gate electrode (eg, a polysilicon or other conductor) is formed on the charge trapping insulation 140. 150) is formed. The charge tracking insulation unit 140 and the gate electrode 150 form a gate structure on the semiconductor substrate 101, and may have a polygonal planar shape as described below. The charge trapping insulating unit 140 includes a tunneling insulating layer 110, a charge trap region 60, and a blocking insulating layer 130 sequentially formed on the substrate 101.

The tunneling insulating layer 110 and the blocking insulating layer 130 may be formed of an oxide such as SiO ₂ . The blocking insulating layer 130 prevents charge trapped in the charge trap region 60 from leaking to the gate electrode 150, and prevents charge from being injected from the gate electrode 15 into the charge trap region 60. . As the metal nano dot 120, a metal having a work function similar to or larger than that of silicon, for example, a metal material such as gold, silver, nickel, platinum, ruthenium, or the like may be used.

In this embodiment, metal nanodots 120 are used as the charge trap region 60 for providing a charge trap site. The charge trap region 60 formed of the metal nano dot 120 may localize charge in a program (charge storage) operation and store the charge asymmetrically in a high field. For example, in the case of n-channel, in FIG. 2, 0V voltage is applied to the left source / drain region 105b, a predetermined positive voltage is applied to the source / drain region 105a on the right side, and a gate voltage (positive voltage) preset to the gate. ) Electrons (e-) flowing from the source side 105b to the drain side 105a pass through the tunneling insulating film 110 by hot electron injection or the like and are adjacent to the drain side 105a. May be trapped in area A (see FIG. 2). As a result, the electrons may be asymmetrically localized and stored in the predetermined region A adjacent to the drain side 105a. By inverting the voltage applied to the source / drain regions 105a and 105b, the charge can be localized and stored in the region B opposite to the region A. Similarly, in the case of the p-channel, according to the voltage applied to the source / drain regions 105a and 105b, the charge may be localized and stored in the region A or the region B (or both the regions A and B).

In a similar manner, depending on the voltage applied to the source / drain regions 105a, 105b, 105c, and 105d, the charge trap region portions A, B, C, and D adjacent to the vertex of the quadrilateral gate electrode 150 are applied. The charge can be localized and stored selectively. As such, the electrical characteristics such as the threshold voltage of the memory device vary according to the region where the charge is stored, and the data storage state of the memory is classified. By arranging the source / drain regions 150 at the four corners of the gate electrode 150 and storing or erasing charges at each vertex portion, one bit is stored by dividing 0 or 1 at each vertex portion. As a result, one bit is stored in each of areas A, B, C, and D corresponding to the vertex of the gate electrode 150 having a quadrangular planar shape, so that a total of four bits can be stored in one unit cell.

In the program operation for storing charge or the read operation for reading data, by applying a predetermined operating voltage to a pair of source / drain regions (for example, 105a and 105b) disposed at both ends of a quadrilateral side, A unique channel region may be formed in the semiconductor substrate 101 along the side of. For example, a channel region may be formed along the side connecting the pair of source / drain regions 105b and 105c by applying an operating voltage to the pair of source / drain regions 105a and 105b. In addition, by applying an operating voltage to the pair of source / drain regions 105b and 105c, another channel region may be formed along the side connecting the pair of source / drain regions 105b and 105c. In this manner, in the unit cell of the nonvolatile memory device of FIG. 1, four channel regions may be formed along four sides of the quadrangle of the gate. Alternatively, it is also possible to form a channel in at least one diagonal direction of the quadrilateral of the gate. For example, a channel region may be formed along a diagonal line connecting the pair of source / drain regions 105a and 105c by applying an operating voltage to the pair of source / drain regions 105a and 105c.

The memory device 100 described above may be manufactured by sequentially depositing several layers as described below. First, the source / drain regions 105 are formed in the semiconductor substrate 101 through ion implantation and rapid heat treatment. Here, the source / drain regions 105 are formed at positions overlapping the vertices of the gate electrode 150 to be formed later. Thereafter, about 7 nm of the first insulating film (for example, SiO _2, etc.) for the tunneling insulating film 110 is deposited on the semiconductor substrate 101 by a dry oxidation method. Rapid heat treatment at 15 ° C. for 15 seconds may form the metal nano dot 120.

4 is a scanning electron microscope (SEM) photograph showing a metal nanodot used as a charge trap site of a nonvolatile memory device according to an embodiment of the present invention. 4 (a) shows a metal nano dot obtained by heat treatment at about 800 ° C. after depositing the metal film Pt to a thickness of 4 nm, and FIG. Pt nanodots obtained by heat treatment at 800 ° C are shown.

Thereafter, a second insulating film (eg, SiO _2, etc.) for the blocking insulating film 130 to prevent charge leakage to the gate is deposited by PECVD to a thickness of 30 to 100 nm, and the gate conductive layer for the gate electrode 150 is deposited. Deposit 100 ~ 200nm. After such a series of deposition processes, a desired polygonal gate shape (eg, hexagonal, hexagonal, octagonal, triangular, etc., see FIGS. 1, 7, 8, 9) is obtained through the patterning process.

5 is a scheme of storing four bits in one unit cell through localization of charges using the multi-level-cell nonvolatile memory device 100 of FIGS. 1 to 3 according to an embodiment of the present invention. It is a schematic diagram for explaining.

As illustrated in (a) to (p) of FIG. 5, a memory device having a quadrangular gate shape will be described as an example. The source / drain is placed in the. In this case, 1 is a case where charge is localized and stored in a portion of the charge trap region located at each vertex of the quadrilateral charge trap region 60 (or at each vertex of the tetragonal gate electrode 150). If there is none, it can be represented as 0. Accordingly, according to the voltage applied to the source / drain region 105 near each vertex, one bit of each vertex can be stored, and since there are four vertices per unit cell, a total of four bits are stored in one memory cell. You can save it to. Accordingly, as shown in FIGS. 5A to 5P, a total of 2 ⁴ data storage states can be distinguished and displayed in a unit cell, and a total of 4 bits of data can be stored per unit cell.

In the above-described embodiment, although the nano-dot 120 is used as the charge trap region 60 which provides the charge trap site so that charge localization is possible, the present invention is not limited thereto. For example, as illustrated in FIG. 6, in the gate structure 161, a nitride film 125 capable of localizing charges may be used as the charge trapping region 60 in the charge trapping insulating portion 141. Referring to FIG. 6, the tunneling insulating film 110, the nitride film 125, the blocking insulating film 130, and the gate electrode 150 are sequentially formed on the semiconductor substrate 101 on which the source / drain regions 105a and 105b are formed. It is stacked. The tunneling insulating film 110, the nitride film 125, and the blocking insulating film 130 may constitute the charge trapping insulating portion 141 having an ONO structure, thereby forming a SONOS-type memory device as a whole. The planar shape is the same as shown in FIG. As such, the charge may be localized and stored at the vertex of the quadrangular gate shape by using the charge trap region 60 of the nitride film 125.

7 to 9 are plan views schematically illustrating multi-level-cell nonvolatile memory devices (particularly, unit cells) according to other embodiments of the present invention. Cross-sectional structures (eg, cross-sectional views cut along YY ', ZZ') of the memory device according to these embodiments may be formed as shown in FIG. 2 or 6. As illustrated in FIGS. 7 to 9, the gate electrode may be patterned into various polygonal shapes. For example, as shown in FIG. 7, a hexagonal gate electrode 250 may be formed on the semiconductor substrate 101 to define a hexagonal charge trap region 60 thereunder. As shown in FIG. 9, the gate electrodes 350 and 450 having an octagonal or triangular shape may be formed to define the charge trap region 60 having an octagonal or triangular shape beneath it.

By placing source / drain regions 205, 305, and 405 at the vertices of each polygon (hexagon, octagon, or triangle), and selectively storing charges at each vertex, the storage states of 0 or 1 are distinguished. One bit can be stored for each vertex. Accordingly, in the case of the hexagonal gate shape shown in FIG. 7, 6 bits of data can be stored per unit cell. In the case of the gate shape of the octagonal gate shown in FIG. 8, 8 bits of data can be stored per unit cell. In the triangular gate shape shown in FIG. 9, a total of 3 bits of data can be stored per unit cell. In this manner, a new type of high-capacity high-density nonvolatile memory device in which the number of bits that can be stored per unit cell is determined according to the number of vertices of the polygon formed by the planar shape of the gate.

The multi-level-cell nonvolatile memory devices (see FIGS. 1 and 7 to 9) also solve the inter-device interference problem, which has been a problem in the conventional horizontal reduction process, thereby enabling stable multi-level-cell implementation. This can result in significantly increased circuit integration, while lowering production costs.

The present invention is not limited by the above-described embodiment and the accompanying drawings. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims, .

1 is a plan view illustrating a unit cell of a multi-level-cell nonvolatile memory device according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line XX ′ of FIG. 1.

3 is a perspective view schematically illustrating a three-dimensional structure of the nonvolatile memory device of FIG. 1.

4 is a scanning electron microscope (SEM) photograph showing a metal nanodot used as a charge trap site for a multi-level-cell nonvolatile memory device according to an embodiment of the present invention.

FIG. 5 is a schematic diagram illustrating a method of storing four bits in one unit cell through localization of charges according to an embodiment of the present invention.

6 is a cross-sectional view of a multi-level-cell nonvolatile memory device according to another embodiment of the present invention.

7 is a plan view illustrating a unit cell of a multi-level-cell nonvolatile memory device according to another embodiment of the present invention.

8 is a plan view illustrating a unit cell of a multi-level-cell nonvolatile memory device according to still another embodiment of the present invention.

9 is a plan view illustrating a unit cell of a multi-level-cell nonvolatile memory device according to still another embodiment of the present invention.

Claims (13)

A semiconductor substrate on which three or more source / drain regions are formed per unit cell; A charge trapping insulating portion formed on the semiconductor substrate and having a charge trap region trapping charge according to a voltage applied to the source / drain region; And A gate electrode formed on the charge trapping insulating part and having a planar shape of an N-angle (N is an integer of 3 or more), And the charge trap region provides charge trap sites in which charge can be localized and stored, and the source / drain regions are disposed at vertices of an N-shape formed by the gate electrode. The method of claim 1, The charge trapping insulation unit, A tunneling insulating layer formed between the semiconductor substrate and the charge trap region; And And a blocking insulating film formed on the tunneling insulating film. The method of claim 1, The nonvolatile memory device stores data of three bits or more per unit cell by locally storing and selectively storing charge in a portion adjacent to the source / drain region of the charge trap region according to a voltage applied to the source / drain region. And a multi-level-cell nonvolatile memory device. The method of claim 1, And a unique channel region is formed in the semiconductor substrate along the sides of the N-angle or along the diagonal of the N-angle. The method of claim 1, And the charge trap region is formed of a plurality of metal nanodots formed on the tunneling insulating layer. The method of claim 5, The metal nanodot is formed of a metal selected from gold, silver, nickel, platinum and ruthenium. The method of claim 1, And wherein the charge trap region is formed of a nitride film providing a charge trap site. The method of claim 1, The gate electrode has a quadrangular planar shape, the source / drain regions are disposed at each vertex of the tetragon, and the nonvolatile memory device stores four bits of data per unit cell. Level-Cell Nonvolatile Memory Device. The method of claim 1, The gate electrode has a hexagonal planar shape, the source / drain regions are disposed at each vertex of the hexagon, and the nonvolatile memory device stores 6 bits of data per unit cell. Level-Cell Nonvolatile Memory Device. The method of claim 1, The gate electrode has an octagonal planar shape, the source / drain region is disposed at each vertex of the octagon, and the nonvolatile memory device stores 8 bits of data per unit cell. Level-Cell Nonvolatile Memory Device. The method of claim 1, The gate electrode has a triangular planar shape, the source / drain regions are disposed at each vertex of the triangular shape, and the nonvolatile memory device stores three bits of data per unit cell. Level-Cell Nonvolatile Memory Device. A semiconductor substrate in which N (N is an integer of 3 or more) source / drain regions are formed per unit cell; A tunneling insulating film formed on the semiconductor substrate; A plurality of metal nanodots formed on the tunneling insulating layer and configured to trap charges according to a voltage applied to the source / drain to store localized charges; A blocking insulating film formed on the metal nano dot; And A gate electrode formed on the blocking insulating film and having a planar shape of an N-angle; The source / drain regions are disposed at each vertex of the N-angle, and the plurality of metal nanodots are configured to store N bits of data per unit cell by localizing and storing charge adjacent to the vertex of the N-shape. -Level-cell nonvolatile memory device. The method of claim 12, N is an integer of 3 or more and 8 or less, the multi-level-cell nonvolatile memory device.

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