KR20100034611A

KR20100034611A - Method for verification of process window in semiconductor device

Info

Publication number: KR20100034611A
Application number: KR1020080093839A
Authority: KR
Inventors: 김중찬
Original assignee: 주식회사 하이닉스반도체
Priority date: 2008-09-24
Filing date: 2008-09-24
Publication date: 2010-04-01

Abstract

The process window verification method of the semiconductor device of the present invention includes: forming test patterns patterned on the test wafer while varying exposure energy dose and depth of focus; Performing a preliminary margin inspection to confirm the presence of a defect on the test wafer; Inspecting a field width (CD) uniformity margin for each field region of the test wafer to perform a field curvature inspection for detecting a field region having a weak line width uniformity; Combining the results detected by the preliminary margin inspection and the results detected by the field curvature inspection to select a chip having the weakest process margin and performing a full chip inspection; Creating a defect list of defects detected in the full chip test; Analyzing the process margins across the wafer of defects created in the defect list to set process windows of defects; And feeding back the set process window to the design data to secure the process margin of the target pattern to be actually formed on the wafer.

Description

Method for verification of process window in semiconductor device}

The present invention relates to a semiconductor device, and more particularly, to a process window verification method of a semiconductor device.

The development of semiconductor devices is carried out through more than a few dozen processes, and as the degree of integration of devices increases, it is becoming an important issue to improve the yield while optimizing device characteristics. In particular, securing process margins in terms of patterning is a starting point for securing wafer yield while improving device characteristics. Such process margins are generally reflected within the device window by checking within the process window. In this case, the process window refers to a combination of process parameter ranges that affect manufacturing a semiconductor device. Process variables are operator controllable variables, including critical dimensions (CDs) due to the design design of the device to be manufactured. Process variables are measured using a metrology tool. Metrology equipment is a device for measuring process variables of a patterned substrate in a lithographic apparatus, the process variables including, for example, overlays, critical dimensions, film thicknesses, macro defects or micro defects. By using the metrology equipment, the patterning result of the semiconductor device is measured to measure process variables such as defects that affect the fabrication of the device.

On the other hand, in the process of measuring process variables, there is a difference for each metrology equipment, but in the case of metrology equipment based on a simple critical dimension (CD), the operator measures the critical dimension (CD) for a certain point to be patterned. ) Is measured manually and reflected in the process window. However, the method of measuring the critical dimension (CD) by the worker has a limitation that takes a long time. It is also difficult to see that the operator's measurements represent the full margin of the wafer. In addition, in the case of extracting a process window using a defect detection apparatus, it is difficult to select defects generated on a wafer by type or to select errors by size. Accordingly, in the case of extracting the process window using the defect detection apparatus, it is simply determined whether there is a defect and there is a problem that precise data extraction is difficult.

A process window verification method of a semiconductor device according to the present invention includes: forming test patterns patterned on a test wafer while varying an exposure energy dose and a depth of focus; Performing a preliminary margin inspection to confirm the presence of a defect on the test wafer; Inspecting a field width (CD) uniformity margin for each field region of the test wafer to perform a field curvature inspection for detecting a field region having a weak line width uniformity; Performing a full chip test by selecting a chip having the weakest process margin by combining the result detected by the preliminary margin test and the result detected by the field curvature test; Creating a defect list of defects detected in the full chip inspection; Analyzing process margins across the wafer of defects created in the defect list to set process windows of defects; And feeding back the set process window to design data to secure a process margin of a target pattern to be actually formed on a wafer.

In the present invention, the preliminary margin inspection checks whether there is a defect for each field region in the entire test wafer, and performs the simulation with respect to the test wafer using a point extracted as a defect or an expected point of occurrence of a defect as an inspection point. It is desirable to.

The preliminary margin inspection is performed by comparing a design pattern of a database and a test pattern disposed on the test wafer while scanning the NGR device, which is a geometry verification system, in the X-axis and Y-axis directions of the field area of the test wafer. It is good.

The field curvature inspection compares the line width of the inspection point of the outer portion of the field region on the basis of the line width of the inspection point located at the center of the field region to inspect the line width uniformity.

The full chip test is performed by selecting 4 to 6 chips outside the test wafer.

The full chip inspection is preferably excluded when the pattern is broken and proceeds with the inspection.

The defect list is prepared by sorting by type and size of a defect detected in the full chip test.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

1 is a flowchart illustrating a process window verification method of a semiconductor device of the present invention. 2 to 7 are diagrams for explaining a process window verification method of a semiconductor device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, test patterns of a target pattern to be transferred onto an actual wafer are formed on a test wafer (S100). Here, the test patterns formed on the test wafer are formed while varying the exposure energy dose and depth of focus (DOF) in the X and Y axes, which are the left and right directions of the test wafer. 2 is a test wafer map illustrating a process window verification method of a semiconductor device according to an exemplary embodiment of the present invention. Description thereof will be omitted below. Referring to FIG. 2, the test wafer 100 includes a plurality of field regions 105, and the field region 105 includes a chip 110. Although not shown in the drawings, test patterns formed while varying the exposure energy dose and depth of focus (DOF) conditions are arranged in the X and Y axis directions, which are the left and right and up and down directions of the test wafer 100. In order to explain a preferred embodiment of the present invention, test patterns are formed on the test wafer while the exposure energy dose is in the range of 32 m to 38 m and the depth of focus is in the range of -0.17 m to 0.04 m.

Next, a preliminary margin check for checking the presence of a defect on the test wafer is performed (S110 of FIG. 1). The preliminary margin test is a test to check whether there is a defect for each field in the entire test wafer before proceeding to the full chip test. To this end, a simulation is performed on the test wafer to predetermine the points extracted as defects or the defect expected points as inspection points. That is, the inspection points designated as inspection targets in the preliminary margin inspection are points where defects are found in a priori performed wafer evaluation or are weak points where defects are expected to occur.

Referring to FIG. 3A, the presence of a defect is examined using NGR equipment, which is a geometry verification system, on a test wafer 100 in which a field region 105 is defined. Here, test patterns (not shown) formed while varying the exposure energy dose and the depth of focus in the X and Y-axis directions are disposed on the test wafer 100. The NGR device 300 scans the field area 105 in the X-axis and Y-axis directions, and compares a predetermined inspection point with a design value of a database to derive a defect. As shown in FIG. 3B, as a result of the preliminary margin inspection, the field region 'X' and the normal field region 'O' where defects are generated for each field region 105 in the entire test wafer 100 can be roughly identified. . In addition, during the preliminary margin inspection, NGR equipment can check the accuracy of the process parameters (parameters) to check the accuracy of the simulation results and improve the feedback (feedback) can be performed. For example, the process variables of an NGR instrument can be set to the line, space, center of line, center of space, and edge of the test pattern of the pattern, which can be changed by measuring the accuracy of the reference values of these process variables. Can be.

Next, a field curvature margin for each field region of the test wafer is inspected to perform a field curvature inspection for detecting a field region having a weak line width uniformity (S120 in FIG. 1). Specifically, referring to FIG. 4A, field curvature inspection is performed by using the NGR device 300 on inspection points on which the preliminary margin inspection is performed on the test wafer 100. The field curvature check examines the critical dimension (CD) uniformity of the field region. The field curvature inspection is performed by the NGR device 300 scanning the test wafer 100 in the X-axis and Y-axis directions, and the outer portion of the field region based on the line width of the inspection point 200 located at the center of the field region 105. The line width uniformity can be inspected by inspecting the line width of the inspection point 205. This field curvature check confirms that the linewidth uniformity is within the linewidth margin tolerance. Then, as illustrated in FIG. 4B, 'X', which is out of the line width margin range, that is, an area where the line width margin is weak, and 'O', which is an area within the line width margin range, are detected. Here, FIG. 4B is an enlarged view of a partial region in which the field curvature inspection of FIG. 4A is performed. The field curvature inspection is performed to select the chip having the least margin in the field region 105 to inspect the entire chip. The area to be inspected for the entire chip is selected as the general point with the weakest line width margin. For example, referring back to FIG. 4B in the embodiment of the present invention, the right side of the Y-axis field area of the test wafer has four field areas 105 having good line width margins, while the left side has three line widths and the left side has line width margins. While extracting the weak portion, the chip on the lower left side may be selected as the weakest point 210 of the line width margin.

Next, the result of the preliminary margin inspection (see FIG. 3B) and the field curvature inspection (see FIG. 4B) are combined to provide full chip inspection on the chip having the weakest process margin. (S130 of FIG. 1). In the full chip inspection, first, the field region where a defect is detected in the preliminary margin inspection of FIG. 3B and the chip having the smallest line width margin in the field curvature inspection in FIG. 4B are selected to select the chip having the weakest process margin. Accordingly, referring to FIG. 5, in the embodiment of the present invention, four to six chips on the outer surface of the wafer are selected as the chip 215 having the weakest process margin, and the full chip inspection is performed on the selected chip 215. . Here, in selecting a chip to perform a full chip test, the test is impossible when the pattern is completely collapsed, so it is excluded. The full chip inspection detects defects 220 on the chip by comparing the test patterns disposed on the chip with design values in the database while scanning the chip in the X-axis and Y-axis directions with NGR equipment. Next, a defect list is created by arranging the defects 220 detected in the chip subjected to the full chip inspection (S140 in FIG. 1). Defects detected in the full chip test may be sorted according to the type and size of the defects detected in the chip 215 on which the full chip test is performed.

The process margin is then analyzed across the wafer for the defects listed in the defect list (full wafer review, S150). To do this, the defect to be analyzed is selected from the defect list generated by the full chip inspection. Defects to be analyzed throughout the wafer can be arbitrarily selected by the operator. Referring to FIG. 6A, a defect point 225 is selected in a full wafer region, and a line width and a defect shape are inspected at the selected defect point 225. In this case, the region X whose pattern is completely collapsed is excluded since it cannot be inspected. In this way, the line width and the defective shape may be examined at the selected defect point 225 to derive a process margin range of the defect. Referring to FIG. 6B, which shows a process margin range of a randomly selected defect, the process margin range of a first defect point is a position where a defect does not occur on a test pattern in which the exposure energy dose and the depth of focus are changed in the X-axis and Y-axis directions. to be. Accordingly, as shown again in FIG. 6B, the process margin of the defect has a process margin for exposure energy dose by the range indicated by the first arrow 230, and focuses by the range indicated by the second arrow 235. It can be seen that it has a process margin of depth. The process margin is the remaining region excluding the point 240 at which the defect occurred.

The process window of each detected defect is set using the process margin range derived as described above (S160). Specifically, a margin evaluation table for over dose, under dose, and focus of exposure energy is extracted for each defect. Referring to FIG. 7, which shows the depth of focus by exposure energy dose of each defect, in the case of the 'A' defect, the depth of focus is applied from the exposure energy dose from 33.5m, which is the optimal energy dose, to 32.5m, which is 3% under dose. It can be seen that no change occurs even when applied at 34.5m which is 3% over dose. On the other hand, the 'E' defect shows a depth of focus of 160nm at 32.5m under 3%, while a depth of focus of 120nm appears at 34.5m at 3% overdose. In other words, it can be confirmed that the process margin of the defect is different for each defect.

Next, by feeding back the process window set for each defect to the design data (S160 of FIG. 1), the process margin of the target pattern to be actually formed on the wafer can be improved.

In the analysis method for verifying the process window of the semiconductor device according to the present invention, the wafer inspection is performed based on the data of the database instead of comparing the images, and thus, various types of patterns or sizes of defects can be detected and classified. . In addition, since the entire wafer area is inspected for various patterns existing in the chip, the process window for the entire wafer area can be extracted. In addition, analysis time for the process window that has been processed separately is performed according to the continuous system flow, thereby reducing the analysis time. In addition, the accuracy of the analysis can be improved by proceeding based on the data in the database. It can also be extracted from a vast library of inspection data when needed and used for a variety of analytical tasks.

1 is a flowchart illustrating a process window verification method of a semiconductor device of the present invention.

2 to 7 are diagrams for explaining a process window verification method of a semiconductor device according to an embodiment of the present invention.

Claims

Forming patterned test patterns on the test wafer with varying exposure energy dose and depth of focus;

Performing a preliminary margin inspection to confirm the presence of a defect on the test wafer;

Inspecting a field width (CD) uniformity margin for each field region of the test wafer to perform a field curvature inspection for detecting a field region having a weak line width uniformity;

Performing a full chip test by selecting a chip having the weakest process margin by combining the result detected by the preliminary margin test and the result detected by the field curvature test;

Creating a defect list of defects detected in the full chip inspection;

Analyzing process margins across the wafer of defects created in the defect list to set process windows of defects; And

And feeding back the set process window to design data to secure a process margin of a target pattern to be actually formed on a wafer.

The method of claim 1,

The preliminary margin inspection method for verifying a process window of a semiconductor device to determine whether a defect exists for each field region in the entire test wafer.

The method of claim 1,

The preliminary margin inspection is a process window verification method of a semiconductor device performing a simulation for the test wafer by using a point extracted as a defect or a point of occurrence of defect as an inspection point.

The method of claim 1,

The preliminary margin inspection is performed by scanning a NGR device, which is a geometry verification system, in the X and Y axis directions of the field area of the test wafer, by comparing the test values disposed on the test wafer with the design values of the database. Process window validation method.

The method of claim 1,

The field curvature inspection is a process window verification method of inspecting a line width uniformity by comparing the line width of the inspection point of the outer portion of the field region on the basis of the line width of the inspection point located in the center of the field region.

The method of claim 1,

The full chip inspection is a process window verification method of the semiconductor device to perform the selection of four to six chips outside the test wafer.

The method of claim 1,

The full chip inspection is a process window verification method for a semiconductor device to exclude the pattern is broken if the inspection proceeds.

The method of claim 1,

The defect list is a process window verification method of a semiconductor device, which is prepared by sorting by type and size of a defect detected in the full chip test.