KR20100030118A - Insert of apparatus of semiconductor package - Google Patents

Insert of apparatus of semiconductor package Download PDF

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Publication number
KR20100030118A
KR20100030118A KR1020080088908A KR20080088908A KR20100030118A KR 20100030118 A KR20100030118 A KR 20100030118A KR 1020080088908 A KR1020080088908 A KR 1020080088908A KR 20080088908 A KR20080088908 A KR 20080088908A KR 20100030118 A KR20100030118 A KR 20100030118A
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South Korea
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package
guide
semiconductor package
insert
semiconductor
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KR1020080088908A
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Korean (ko)
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KR100999000B1 (en
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김영웅
오지웅
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주식회사 티에프이스트포스트
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67144Apparatus for mounting on conductive members, e.g. leadframes or conductors on insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/673Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
    • H01L21/67333Trays for chips
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/673Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
    • H01L21/6735Closed carriers
    • H01L21/67356Closed carriers specially adapted for containing chips, dies or ICs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67703Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations
    • H01L21/67721Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations the substrates to be conveyed not being semiconductor wafers or large planar substrates, e.g. chips, lead frames

Abstract

PURPOSE: The apparatus of a semiconductor package insert is provided to prevent a semiconductor package and the package insert from damaging due to the misalignment of the semiconductor package using a lateral side package guide. CONSTITUTION: A semiconductor package insert includes a package insert(100), a latch(130) and a latch open cover(200). A guide hole(120) is formed on the both side of the surface of the package insert. A package loading groove(110) is formed on the center of the package insert. The guide hole guides the guidepost of a pusher unit. The latch is installed to be rotated around a hinge pin(131) on the inner wall of the package loading groove and is opened while a semiconductor package is transferred.

Description

반도체 패키지 인서트{insert of apparatus of semiconductor package}Semiconductor package insert {insert of apparatus of semiconductor package}

본 발명은 반도체 패키지 인서트에 관한 것으로서, 더욱 상세히는 반도체 생산공정을 통해 생산된 반도체패키지가 고온 또는 고전압 및 저온 환경에서 적합하게 제작되었는지 테스트하기 위해서 패키지인서트에 공급할 때, 정해진 정 위치에 안정적으로 안착되어 전기적 접촉이 양호하게 이루어질 수 있도록 하고, 또한 반도체패키지가 반도체인서트에 장착 또는 탈착될 때 반도체패키지의 파손 및 이탈되는 현상을 방지할 수 있도록 한 반도체 패키지 인서트에 관한 것이다.The present invention relates to a semiconductor package insert, and more particularly, when the semiconductor package produced through the semiconductor production process is supplied to the package insert to test whether it is properly manufactured in a high temperature or high voltage and low temperature environment, it is stably seated in a fixed position The present invention relates to a semiconductor package insert for preventing electrical breakage and detachment of a semiconductor package when the semiconductor package is attached to or detached from the semiconductor insert.

일반적으로 반도체패키지의 제조공정은 제조하고자 하는 반도체소자에 따라 조금씩 공정이 추가될 것이나, 기본적으로 18단계의 공통과정에 의하여 제조된다.In general, the manufacturing process of the semiconductor package will be added little by little depending on the semiconductor device to be manufactured, but is basically manufactured by a common process of 18 steps.

1단계는 단결정성장단계로 고순도로 정제된 실리콘 용융액에 시드(Seed) 결정을 접촉하고 회전시키면서 단결정규소봉(Ingot)을 성장시키는 단계이고, 2단계는 규소봉절단로 성장된 규소봉을 균일한 두께의 얇은 웨이퍼로 잘라내는 단계, 3단계는 웨이퍼 표면연마단계로 웨이퍼의 한쪽면을 연마(Polishing)하여 거울면처럼 만들어주며, 이 연마된 면에 회로패턴을 형성하는 단계이며, 4단계로는 회로설계단계 로 CAD(Computer Aided Design)시스템을 사용하여 전자회로와 실제 웨이퍼 위에 그려질 회로패턴을 설계하는 단계이다.The first stage is a single crystal growth stage, in which a single crystal silicon rod is grown while contacting and rotating the seed crystals with a highly purified silicon melt, and the second stage is a uniform silicon rod grown by silicon rod cutting. Step 3 is a step of polishing a thin wafer to make a mirror surface by polishing one side of the wafer, and forming a circuit pattern on the polished surface. In the circuit design stage, a CAD (Computer Aided Design) system is used to design circuit patterns to be drawn on electronic circuits and actual wafers.

그리고 5단계는 마스크(Mask)제작단계로 설계된 회로패턴을 유리판 위에 그려 마스크를 만드는 단계이고, 6단계는 산화(Oxidation)공정단계로 800~1200℃의 고온에서 산소나 수증기를 실리콘 웨이퍼표면과 화학반응시켜 얇고 균일한 실리콘산화막(SiO2)을 형성하는 단계, 7단계로는 감광액 도포(Photo Resist Coating)단계로 빛에 민감한 물질인 감광액(PR)을 웨이퍼 표면에 고르게 도포시키는 단계이며, 8단계는 노광(Exposure)공정단계로 노광기(Stepper)를 사용하여 마스크에 그려진 회로패턴에 빛을 통과시켜 감광막이 형성된 웨이퍼 위에 회로패턴을 사진 찍는단계이다.The fifth step is to make a mask by drawing a circuit pattern designed as a mask manufacturing step on a glass plate, and the sixth step is an oxidation process step. Reacting to form a thin and uniform silicon oxide film (SiO2), Step 7 is a photo-resist coating step to apply a light-sensitive material (PR) evenly to the surface of the wafer, Step 8 An exposure process is a step in which a circuit pattern is photographed on a wafer on which a photoresist film is formed by passing light through a circuit pattern drawn on a mask using an exposure machine.

또 9단계는 현상(Development)공정단계로 웨이퍼 표면에서 빛을 받은 부분의 막을 현상시키는 단계이고, 10단계는 식각(Etching)공정단계로 회로패턴을 형성시켜 주기 위해 화학물질이나 반응성 가스를 사용하여 필요없는 부분을 선택적으로 제거시키는 공정단계, 11단계는 이온주입(Ion Implantation)공정단계로 회로패턴과 연결된 부분에 불순물을 미세한 가스입자 형태로 가속하여 웨이퍼의 내부에 침투시킴으로써 전자소자의 특성을 만들어 주며, 이러한 불순물주입은 고온의 전기로 속에서 불순물입자를 웨이퍼 내부로 확산시켜 주입하는 확산공정에 의해서도 이루어지는 단계이다.In addition, Step 9 is a development process to develop a film of the lighted part on the wafer surface, and Step 10 is an etching process to use a chemical or reactive gas to form a circuit pattern. Process step for selectively removing unnecessary parts, step 11 is ion implantation process step to accelerate the impurities in the form of fine gas particles in the part connected to the circuit pattern to penetrate the inside of the wafer to make the characteristics of the electronic device The impurity implantation is also performed by a diffusion process in which impurity particles are diffused into a wafer in a high temperature electric furnace.

그리고 12단계로 화학기상증착(CVD:Chemical Vapor Deposition)공정단계로 반응가스간의 화학반응으로 형성된 입자들을 웨이퍼표면에 증착하여 절연막이나 전 도성막을 형성시키는 공정단계이고, 13단계는 금속배선(Metallization)공정단계로 웨이퍼 표면에 형성된 각 회로를 알루미늄선으로 연결시키는 공정단계, 14단계는 웨이퍼 자동선별(EDS Test)단계로 웨이퍼에 형성된 IC칩들의 전기적 동작여부를 컴퓨터로 검사하여 불량품을 자동선별단계이며, 15단계는 웨이퍼 절단(Sawing)단계로 웨이퍼상의 수많은 칩들을 분리하기 위해 다이아몬드 톱을 사용하여 웨이퍼를 전달하는 단계, 16단계는 칩 집착(Die Bonding)단계로 낱개로 분리되어 있는 칩 중 EDS 테스트에서 양품으로 판정된 칩을 리드 프레임 위에 붙이는 공정단계, 17단계는 금속연결(Wire Bonding)단계로 칩 내부의 외부연결단자와 리드프레임을 가는 금선으로 연결하여 주는 공정단계이고, 마지막으로 18단계은 성형(Molding)단계로 연결 금선 부분을 보호하기 위해 화학수지로 밀봉해 주는 공정으로 반도체소자가 최종적으로 완성된다.The chemical vapor deposition (CVD) process is carried out in 12 steps. The process of depositing particles formed by chemical reaction between reaction gases on the wafer surface forms an insulating film or a conductive film. In step 13, metallization is performed. The process step of connecting each circuit formed on the wafer surface with aluminum wire as a process step, and the step 14 is an automatic wafer selection (EDS test) step. Step 15 is a wafer cutting step to transfer a wafer using a diamond saw to separate a large number of chips on the wafer, and step 16 is an EDS test of chips separated in a die bonding step. In step 17, the chip, which is judged to be a good product, is attached to the lead frame, and the step 17 is a wire bonding step. And the process steps to connect the connection terminal to the lead frame by a thin gold wire, a process that the resin is sealed with a chemical semiconductor device is finally completed in order finally to protect the gold wire connected to the portion 18 forming dangyeeun (Molding) step.

이러한 복잡한 공정을 거쳐 생산되는 반도체패키지는 고온 또는 고전압 및 저온의 환경에서 정해진 조건을 충족시키는 가의 여부를 테스트하는 과정을 패스하여야만 하며, 이러한 테스트를 받기 위해 반도체패키지는 운반기기인 진공흡착픽커에 의해 패키지인서트로 공급된다.The semiconductor package produced through such a complicated process must pass the process of testing whether it meets the specified conditions in a high temperature or high voltage and low temperature environment. In order to receive such a test, the semiconductor package is carried out by a vacuum adsorption picker, which is a transport device. Supplied as a package insert.

패키지인서트는 반도체패키지가 공급되면, 공급된 반도체패키지의 리드가 테스트소켓의 프로브핀에 전기적으로 접촉되도록 구동부에 의해 테스트존으로 반도체패키지를 이동시켜주는 물품이다.The package insert is an article for moving the semiconductor package to the test zone by the driver so that the lead of the supplied semiconductor package is in electrical contact with the probe pin of the test socket when the semiconductor package is supplied.

또한, 푸셔유니트는 패키지인서트에 안착된 반도체패키지를 푸셔로 눌러서 반도체패키지의 테스트를 행하는 동안 반도체패키지가 유동되지 않도록 하는 기구 이다.In addition, the pusher unit is a mechanism for preventing the semiconductor package from flowing during the test of the semiconductor package by pressing the semiconductor package seated on the package insert with the pusher.

여기서, 도 1 내지 도 4 는 종래의 패키지인서트와 푸셔유니트의 일반적인 구조를 보여주기 위해 개략적으로 도시한 도면이다.1 to 4 are diagrams schematically showing a general structure of a conventional package insert and a pusher unit.

즉, 도 1 및 도 2 와 같이 푸셔유니트(40)의 양단에는 패키지인서트(10)의 위에서 승강 동작을 할 때 위치를 안내하는 가이드포스트(41)가 하향으로 돌출되어있고, 도 3 과 같이 푸셔유니트(40)의 저면 중앙부에는 패키지인서트(10)에 놓인 반도체패키지(30)를 눌러주는 푸셔를 구비하고 있다.That is, as shown in FIGS. 1 and 2, guide posts 41 for guiding a position when lifting and lowering the package insert 10 protrude downward from both ends of the pusher unit 40, and pushers as shown in FIG. 3. The center portion of the bottom surface of the unit 40 is provided with a pusher for pressing the semiconductor package 30 placed on the package insert 10.

그리고 종래의 패키지인서트(10)는 표면 양단에 상기 푸셔유니트(40)의 가이드포스트(41)를 안내하는 가이드홀(12)이 형성되고, 표면 중앙에는 반도체패키지(30)가 삽입되어 놓이는 패키지안착홈(11)이 형성되며, 패키지안착홈(11)의 양쪽 내벽에는 반도체패키지(30)가 이탈되지 않도록 잡아주는 래치(13)가 설치되고, 양쪽 내벽의 상면에는 래치(13)를 작동시키는 토글이 돌출형으로 설치되어 있다.In the conventional package insert 10, guide holes 12 for guiding the guide posts 41 of the pusher unit 40 are formed at both ends of the surface, and a package seat in which the semiconductor package 30 is inserted is placed at the center of the surface. A groove 11 is formed, and latches 13 are installed on both inner walls of the package seating groove 11 to prevent the semiconductor package 30 from being separated. Toggles for operating the latch 13 on the upper surfaces of both inner walls are provided. This protrusion is provided.

또한, 패키지인서트(10)의 상면에는 토글을 눌러서 래치(13)를 열어주는 래치오픈커버(20)가 설치되어 있고, 패키지안착홈(11)의 바닥 사방 모서리 부위에는 반도체패키지(30)가 정위치에 안착되도록 위치결정 및 안내를 유도하는 측면가이드가 형성되어 있다.In addition, a latch open cover 20 is installed on the top surface of the package insert 10 to open the latch 13 by pressing a toggle, and the semiconductor package 30 is fixed at the bottom four corners of the package seating groove 11. Side guides are formed to guide positioning and guidance to be seated in position.

이러한 종래의 패키지인서트는 반도체패키지의 테스트를 위해 진공흡착픽커(도면에 미도시)에 진공흡착된 반도체패키지를 패키지안착홈에 넣을 때 래치오픈커버가 토글을 누르면 토글은 아래로 슬라이딩되면서 래치로 하여금 스프링을 압축하면서 오픈되게 하며, 이때 패키지가이드로 안내되는 반도체패키지가 패키지안착홈 바닥에 안착된다. Such a conventional package insert has a latch opening while the latch open cover presses a toggle when the vacuum packaged semiconductor package is inserted into the package seating groove in a vacuum adsorption picker (not shown in the drawing) to test the semiconductor package. When the spring is compressed and opened, the semiconductor package guided by the package guide is seated on the bottom of the package seating groove.

그리고, 래치오픈커버를 눌러주던 힘이 해제되면 토글이 상승되고, 이때 래치는 스프링의 장력을 받아 곧바로 원위치로 복원되어 안착된 반도체패키지의 양단을 잡아주므로 테스트를 위한 이동과정에서 외부의 충격이 가해져도 반도체패키지가 이탈하지 않게 된다.When the force that presses the latch open cover is released, the toggle is raised. At this time, the latch is restored to its original position immediately under the tension of the spring, so as to hold both ends of the seated semiconductor package, an external shock is applied during the test process. Also, the semiconductor package will not be separated.

또한, 테스트 완료 후에 래치오픈커버를 눌러주면 래치가 스프링을 압축하면서 뒤로 밀려나 오픈되므로 반도체패키지를 뺄 수 있다.In addition, if the latch open cover is pressed after the test is completed, the latch is pushed back and opened while compressing the spring, thereby removing the semiconductor package.

그리고, 패키지인서트 위에서 승강되는 푸셔유니트의 푸셔는 가이드홀에 안내되는 가이드포스트에 의해 패키지인서트의 패키지안착홈에 놓인 반도체패키지를 눌러서 테스트가 진행되는 동안 반도체패키지가 유동되지 않도록 한다. Then, the pusher of the pusher unit which is lifted on the package insert presses the semiconductor package placed in the package seating groove of the package insert by the guide post guided by the guide hole so that the semiconductor package does not flow during the test.

그런데, 종래의 패키지인서트는 반도체패키지를 패키지안착홈에 삽입시킬 때 패키지안착홈의 사방에 형성된 측면가이드에 정확히 안착되지 못하고 반도체패키지의 일단이 측면가이드 위치를 벗어나서 다른 부위에 놓이게 되는 등 공급 불량 및 위치 결정이 좋지 않아 테스트시 수율이 떨어지는 현상이 많이 발생된다.However, in the conventional package insert, when the semiconductor package is inserted into the package seating groove, the side guides formed on all sides of the package seating groove are not accurately seated, and one end of the semiconductor package is placed in another part beyond the side guide position. Poor positioning results in poor yields during testing.

즉, 반도체패키지의 공급 불량 및 위치 경정이 좋지 않으면 양쪽 래치가 열려도 반도체패키지가 래치 아래로 삽입되지 못하고 래치 위에 걸쳐지는 상태가 되므로 테스트를 위한 이동과정 중에 또는 외부의 작은 충격에도 반도체패키지가 패키지인서트에서 이탈되는 경향이 많이 발생한다. In other words, if the supply of the semiconductor package is poor or the position correction is poor, the semiconductor package cannot be inserted under the latch even if both latches are opened, and the package is placed over the latch. There is a lot of tendency to deviate from the insert.

또한 반도체패키지가 정위치에 안착되지 못하고 불안정하게 놓이게 되면 테스트존에서 반도체패키지와 테스트 소켓 간의 접촉유지가 안정적으로 되지 않아 전 기적인 접촉에 문제가 발생하므로 테스트의 안정성과 정밀성이 떨어지게 된다.In addition, if the semiconductor package is unstable and placed in an unstable position, the contact between the semiconductor package and the test socket is not stable in the test zone, thereby causing electrical contact problems, thereby deteriorating test stability and precision.

그리고, 반도체패키지가 정위치에 안착되지 못하고 불안정하게 놓이면 푸셔유니트의 푸셔로 눌러줄 때 불안정하게 놓인 반도체패키지와 패키지인서트가 파손되어 테스트 장비의 안전성이 떨어지는 문제점이 있다.In addition, if the semiconductor package is not placed in an unstable position and is unstable, the semiconductor package and the package insert that are unstable when pressed into the pusher of the pusher unit are damaged, thereby degrading the safety of the test equipment.

그리고, 패키지인서트의 형태가 변경되면 기존 라인에서 사용중인 푸셔유니트의 호환성이 없어서 그대로 활용하지 못하고 그에 맞는 새 푸셔유니트로 교체하여야 하므로 상당한 원가상승의 요인이 되고 있다.In addition, if the shape of the package insert is changed, there is no compatibility of the pusher unit being used in the existing line, so it is not used as it is, and it must be replaced with a new pusher unit, which is a significant cost increase factor.

본 발명의 목적은 패키지인서트에 안착되는 반도체패키지의 공급 및 위치 결정이 양호하게 수행되어 이동과정 중 또는 외부의 작은 충격에 반도체패키지의 이탈되는 현상을 방지하고, 또한 전기적인 접촉이 안정되어 테스트의 정밀성을 높일 수 있는 반도체 패키지 인서트를 제공하는 데 있다. An object of the present invention is to supply and position the semiconductor package seated on the package insert is performed well to prevent the semiconductor package from falling off during a small impact or during the movement process, and also the electrical contact is stable to test It is to provide a semiconductor package insert that can increase precision.

본 발명의 다른 목적은 패키지인서트에 안착된 반도체패키지를 푸셔로 눌러줄 때 반도체패키지의 파손됨을 방지하고, 반도체패키지 탈착을 위해 푸셔가 상부로 상승할 때 패키지인서트가 푸셔를 따라 움직이는 현상을 방지하고, 또한 패키지인서트의 형태가 변경되더라도 기존 라인에서 사용중인 푸셔유니트를 그대로 활용할 수 있는 장비의 호환성으로 원가절감을 이룰 수 있는 반도체 패키지 인서트를 제공하는 데 있다.Another object of the present invention is to prevent the breakage of the semiconductor package when pressing the semiconductor package seated on the package insert with the pusher, and to prevent the phenomenon that the package insert moves along the pusher when the pusher is raised to the top for detaching the semiconductor package In addition, even if the shape of the package insert is changed, it is to provide a semiconductor package insert that can achieve cost savings through the compatibility of equipment that can utilize the pusher unit used in the existing line as it is.

이와 같은 본 발명은 표면 양단에는 푸셔유니트의 가이드포스트를 안내하는 가이드홀이 형성되고, 중앙부에는 반도체패키지가 놓이는 패키지안착홈이 형성된 패키지인서트와; 패키지안착홈의 양쪽 내벽에서 힌지핀을 중심으로 회동되게 설치되며, 반도체패키지의 공급 및 인출시 오픈되는 래치와; 패키지인서트 위에서 승강되며, 하강시 래치를 오픈시키는 래치오픈커버;로 반도체 패키지 인서트를 구성함에 있어서, 패키지인서트의 래치가 설치되는 양쪽 내벽과 직교되는 방향의 양쪽 측면 내벽에는 상단에 힌지핀과 한쌍의 스프링지지부가 구비된 패키지가이드장착부를 형성하는 것을 특징으로 한다. As described above, the present invention includes a package insert having guide holes for guiding the guide posts of the pusher unit at both ends of the surface, and having a package seating groove in which the semiconductor package is placed at the center thereof; A latch installed at both inner walls of the package seating groove so as to rotate about the hinge pin, the latch being opened when the semiconductor package is supplied and withdrawn; A latch open cover which is lifted on the package insert and opens the latch when it is lowered. In constructing the semiconductor package insert, a hinge pin and a pair of hinge pins are formed on both side inner walls perpendicular to both inner walls on which the latches of the package insert are installed. It characterized in that to form a package guide mounting portion provided with a spring support.

그리고, 패키지가이드장착부에는 반도체패키지를 패키지안착홈의 정위치로 안내하는 측면패키지가이드를 힌지공에 의해 힌지핀에 설치하여 패키지안착홈 쪽으로 출몰되도록 회동형으로 설치하되 상측이 개방된 상태에서 내부에 코일스프링이 설치되는 한쌍의 스프링수납부를 측면패키지가이드에 구비하여 상단이 스프링지지부에 걸려 지지되는 코일스프링의 장력에 의해 측면패키지가이드가 패키지안착홈을 향하여 탄력적으로 회동되게 하고, 패키지인서트 하단에는 측면패키지가이드가 패키지안착홈을 향하여 출몰됨을 안내하는 소켓가이드를 설치한 것을 특징으로 한다. In the package guide mounting portion, a side package guide for guiding the semiconductor package to the correct position of the package seating groove is installed on the hinge pin by the hinge hole and installed in a rotatable manner so that the package guide is mounted toward the package seating groove. A pair of spring housings in which the coil springs are installed is provided on the side package guides so that the side package guides are rotated elastically toward the package seating grooves by the tension of the coil springs supported by the upper ends of the spring support parts. It is characterized in that the socket guide for guiding that the package guide is released to the package seating groove.

특히, 측면패키지가이드의 힌지공을 수직방향의 장공으로 길게 형성하여 코일스프링의 장력을 받는 측면패키지가이드가 패키지안착홈을 향하여 전진될 때는 하강되면서 돌출되고, 측면패키지가이드가 패키지가이드장착부를 향하여 후진될 때 는 상승되면서 들어가게 형성하며, 측면패키지가이드(140)의 양 측면 하단에는 돌기부를 구비하여, 측면패키지가이드가 패키지가이드장착부에서 돌출되거나 들어갈 때, 측면패키지가이드와 패키지가이드장착부 사이에 공간을 형성하여, 측면패키지가이드와 패키지가이드장착부의 마찰을 줄일 수 있도록 함으로써 본 발명의 목적을 달성할 수 있는 것이다.In particular, the hinge hole of the side package guide is formed to be a long hole in the vertical direction so that when the side package guide subjected to the tension of the coil spring is advanced toward the package seating groove, it protrudes while descending, and the side package guide retreats toward the package guide mounting portion. When the side package guide 140 is formed to be raised and entered, and provided with projections at the bottom of both sides of the side package guide 140, when the side package guide protrudes or enters the package guide mounting portion, it forms a space between the side package guide and the package guide mounting portion In order to reduce the friction between the side package guide and the package guide mounting portion, the object of the present invention can be achieved.

이와 같은 본 발명은 반도체패키지가 테스트를 위해 패키지인서트에 공급될 때 측면패키지가이드에 의해 패키지안착홈의 정위치에 항시 안정적으로 안착되므로 푸셔가 안착된 반도체패키지를 눌러줄 때 종래처럼 잘못 놓임으로 인해 반도체패키지와 패키지인서트의 파손됨을 방지하고, 또한 푸셔와 측면패키지가이드의 마찰 시간을 최소화하여 푸셔가 상승할 때 패키지인서트가 움직이는 현상을 방지할 수 있는 효과가 있다.The present invention as described above is because when the semiconductor package is supplied to the package insert for testing, it is always stably seated in the correct position of the package seating groove by the side package guide, so when the pusher presses the seated semiconductor package, it is incorrectly placed as before. The semiconductor package and the package insert are prevented from being damaged, and the friction time between the pusher and the side package guide is minimized to prevent the package insert from moving when the pusher is raised.

또한, 반도체패키지가 언제나 패키지인서트의 결정된 정위치에 안착될 수 있어 테스트 소켓과의 접촉유지가 안정적으로 이루어지므로 테스트의 안정성과 정밀성을 유지하여 테스트시의 수율을 최대한 높일 수 있고, 기존의 푸셔유니트를 그대로 사용할 수 있는 호환성이 있어 설비 비용을 절감할 수 있으므로 품질향상과 원가절감을 이룰 수 있는 것이다.In addition, the semiconductor package can always be seated in the determined position of the package insert, thereby maintaining stable contact with the test socket, thereby maintaining the stability and precision of the test, thereby increasing the yield in the test as much as possible, and the existing pusher unit. Because it can be used as it is, it can reduce the cost of equipment, thereby improving the quality and reducing the cost.

이하 본 발명의 특징을 효과적으로 달성할 수 있는 바람직한 실시 예로서 그 기술구성 및 작용효과를 첨부된 도면에 의하여 상세히 설명하면 다음과 같다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

즉, 도 5 는 본 발명에 따른 반도체 패키지 인서트의 구조를 보여주는 분리사시도이고, 도 6 은 본 발명에 따른 반도체 패키지 인서트에 반도체패키지가 장착되는 모습을 보여주는 분리사시도, 도 7 은 본 발명에 따른 반도체 패키지 인서트의 모습을 보여주는 단면도이고, 도 8 과 도 9 는 본 발명에 따른 반도체 패키지 인서트의 측면패키지가이드의 작동모습을 보여주는 단면도이다.That is, FIG. 5 is an exploded perspective view showing a structure of a semiconductor package insert according to the present invention, FIG. 6 is an exploded perspective view showing a semiconductor package mounted on a semiconductor package insert according to the present invention, and FIG. 7 is a semiconductor according to the present invention. 8 and 9 are cross-sectional views showing the operation of the side package guide of the semiconductor package insert according to the present invention.

따라서 본 발명은 표면 양단에는 푸셔유니트(400)의 가이드포스트(410)를 안내하는 가이드홀(120)이 형성되고, 중앙부에는 반도체패키지(300)가 놓이는 패키지안착홈(110)이 형성된 패키지인서트(100)와; 패키지안착홈(110)의 양쪽 내벽에서 힌지핀(131)을 중심으로 회동되게 설치되며, 반도체패키지(300)의 공급 및 인출시 오픈되는 래치(130)와; 패키지인서트(100) 위에서 승강되며, 하강시 래치(130)를 오픈시키는 래치오픈커버(200); 로 반도체 패키지 인서트를 구성함에 있어서, 패키지인서트(100)의 래치(130)가 설치되는 양쪽 내벽과 직교되는 방향의 양쪽 측면 내벽에는 상단에 힌지핀(141)과 한쌍의 스프링지지부(151)가 구비된 패키지가이드장착부(150)를 형성하는 것을 특징으로 한다. Therefore, in the present invention, a guide hole 120 for guiding the guide post 410 of the pusher unit 400 is formed at both ends of the surface, and a package insert having a package seating groove 110 in which the semiconductor package 300 is placed in the center portion thereof. 100); A latch 130 installed pivotally around the hinge pins 131 at both inner walls of the package seating recess 110 and opened when the semiconductor package 300 is supplied and withdrawn; A latch open cover 200 which is lifted on the package insert 100 and opens the latch 130 when lowered; In configuring the semiconductor package insert, hinge pins 141 and a pair of spring support parts 151 are provided on both sides of the inner wall of the package insert 100 in the direction perpendicular to both inner walls on which the latch 130 of the package insert 100 is installed. Characterized in that to form a package guide mounting portion 150.

또한, 패키지가이드장착부(150)에는 반도체패키지(300)를 패키지안착홈(110)의 정위치로 안내하는 측면패키지가이드(140)를 힌지공(142)에 의해 힌지핀(141)에 설치하여 패키지안착홈(110) 쪽으로 출몰되도록 회동형으로 설치하되 상측이 개방된 상태에서 내부에 코일스프링(145)이 설치되는 한쌍의 스프링수납부(148)를 측면 패키지가이드(140)에 구비하여 상단이 스프링지지부(151)에 걸려 지지되는 코일스프링(145)의 장력에 의해 측면패키지가이드(140)가 패키지안착홈(110)을 향하여 탄력적으로 회동되게 하고, 패키지인서트(100) 하단에는 측면패키지가이드(140)가 패키지안착홈(110)을 향하여 출몰됨을 안내하는 소켓가이드(500)를 설치한 것을 특징으로 한다. In addition, the package guide mounting portion 150 has a side package guide 140 for guiding the semiconductor package 300 to the correct position of the package seating groove 110 to be installed on the hinge pin 141 by the hinge hole 142. It is installed in a rotatable manner so as to be settled toward the seating groove 110, but the upper side is provided with a pair of spring receiving portion 148 in the side package guide 140, the coil spring 145 is installed inside the upper side is opened The side package guide 140 is elastically rotated toward the package seating groove 110 by the tension of the coil spring 145 supported by the support 151, the side package guide 140 at the bottom of the package insert 100 It is characterized in that the socket guide 500 is installed to guide the wandering toward the package seating groove 110.

특히, 측면패키지가이드(140)의 힌지공(142)을 수직방향의 장공으로 길게 형성하여 코일스프링(145)의 장력을 받는 측면패키지가이드(140)가 패키지안착홈(110)을 향하여 전진될 때는 하강되면서 돌출되게 하는 것을 특징으로 한다., Particularly, when the hinge hole 142 of the side package guide 140 is formed as a long hole in the vertical direction, the side package guide 140 receiving the tension of the coil spring 145 is advanced toward the package seating groove 110. It is characterized by being protruded while descending.

그리고, 측면패키지가이드(140)가 패키지가이드장착부(150)를 향하여 후진될 때는 상승되면서 들어가게 한 것을 특징으로 한다. Then, when the side package guide 140 is reversed toward the package guide mounting portion 150, it is characterized in that it enters while rising.

또한, 측면패키지가이드(140)의 양 측면 하단에는 돌기부(149)를 구비하여, 측면패키지가이드(140)가 패키지가이드장착부(150)에서 돌출되거나 들어갈 때, 측면패키지가이드(140)와 패키지가이드장착부(150) 사이에 공간을 형성하여, 측면패키지가이드(140)와 패키지가이드장착부(150)의 마찰을 줄일 수 있도록 한 것을 특징으로 한다. In addition, both side lower ends of the side package guide 140 is provided with protrusions 149, when the side package guide 140 protrudes or enters from the package guide mounting portion 150, the side package guide 140 and the package guide mounting portion Forming a space between the 150, characterized in that to reduce the friction between the side package guide 140 and the package guide mounting portion 150.

즉, 이와 같은 본 발명의 특징은, 패키지안착홈(110)의 래치(130)가 설치되는 양쪽 내벽과 직교되는 방향의 양쪽 측벽에 힌지핀(141)을 중심으로 회동되는 한쌍의 측면패키지가이드(140)를 각각 경사지게 대향으로 설치한 것에 있다. That is, the feature of the present invention, a pair of side package guides rotated around the hinge pins 141 on both side walls in the direction orthogonal to both inner walls on which the latch 130 of the package seating groove 110 is installed ( 140 is provided to face each other inclinedly.

이때, 측면패키지가이드(140)는 각각의 패키지가이드장착부(150) 내부에 설치되는데, 이때 패키지가이드장착부(150) 상부에는 힌지핀(141)과 한쌍의 스프링지 지부(151)가 형성된다.At this time, the side package guide 140 is installed in each of the package guide mounting portion 150, in which the hinge pin 141 and a pair of spring paper 151 is formed on the package guide mounting portion 150.

그리고 측면패키지가이드(140)에는 패키드가이드장착부(150)의 힌지핀(141)이 결합되는 힌지공(142)과, 상단은 스프링지지부(151)에 결합되며 하단은 측면패키지가이드(140)의 양단에 구비되는 스프링수납부(148) 내부에 하단에 고정되는 코일스프링(145)이 구비되는 것이다.In addition, the side package guide 140 has a hinge hole 142 to which the hinge pin 141 of the package guide mounting unit 150 is coupled, and an upper end thereof is coupled to the spring support unit 151, and a lower end of the side package guide 140. Coil springs 145 fixed to the lower end are provided in the spring housing 148 provided at both ends.

이와 같이 평상시에는 코일스프링(145)의 탄발력에 의해 측면패키지가이드(140)가 패키지안착홈(110) 내부로 돌출되어있는 상태이고, 반도체패키지(300)가 패키지안착홈(110)으로 삽입되면 측면패키지가이드(140)는 각각의 패키지가이드장착부(150) 내부로 들어가게 되는 것이다.As such, when the side package guide 140 protrudes into the package seating groove 110 by the elastic force of the coil spring 145, and the semiconductor package 300 is inserted into the package seating groove 110. The side package guide 140 is to be entered into each package guide mounting portion 150.

이때, 측면패키지가이드(140)에 형성되는 힌지공(142)은 수직방향의 장공으로 길게 형성되어 있고, 측면패키지가이드(140) 하부에는 소켓가이드(500)가 설치되어 있기 때문에 반도체패키지(300)가 패키지안착홈(110)으로 삽입되어 측면패키지가이드(140)가 패키지가이드장착부(150) 내부로 들어갈 때, 측면패키지가이드(140)가 상측으로 이동하면서 들어가게 된다.At this time, the hinge hole 142 formed in the side package guide 140 is formed as a long hole in the vertical direction, the semiconductor package 300 because the socket guide 500 is installed below the side package guide 140 When the side package guide 140 is inserted into the package seating groove 110 to enter the package guide mounting portion 150, the side package guide 140 is moved while moving upward.

이렇게 측면패키지가이드(140)가 상부로 이동하면서 패키지가이드장착부(150)로 들어가면, 반도체패키지(300)가 패키지안착부(110)에 고정될 때까지 양 측면에서 안정되게 잡아주어 안정된 작업을 수행할 수 있는 것이다.When the side package guide 140 moves to the package guide mounting unit 150 while moving upward, the semiconductor package 300 is stably held on both sides until the semiconductor package 300 is fixed to the package mounting unit 110 to perform a stable operation. It can be.

또한, 측면패키지가이드(140)의 양 측면 하단에는 돌기부(149)를 형성하여 패키지가이드장착부(150)와 일정 간격을 유지시켜줌으로써, 측면패키지가이드(140)가 패키지가이드장착부(150)에서 돌출되거나 들어갈 때, 마찰이나 걸림 등의 오작 동이나 흔들림 없는 정확한 작동을 수행할 수 있는 것이다.In addition, by forming protrusions 149 on both side lower ends of the side package guide 140 to maintain a predetermined distance from the package guide mounting portion 150, the side package guide 140 protrudes from the package guide mounting portion 150 When entering, it can perform the correct operation without malfunction or vibration such as friction or jam.

도 1 은 종래의 반도체 패키지 인서트의 구조를 보여주는 분리사시도.1 is an exploded perspective view showing the structure of a conventional semiconductor package insert.

도 2 는 종래의 반도체 패키지 인서트의 구조를 보여주는 단면도.2 is a cross-sectional view showing the structure of a conventional semiconductor package insert.

도 3 은 종래의 반도체 패키지 인서트에 반도체패키지가 삽입된 모습을 보여주는 단면도.3 is a cross-sectional view showing a state in which a semiconductor package is inserted into a conventional semiconductor package insert.

도 4 는 종래의 반도체 패키지 인서트에 반도체패키지가 잘못 삽입된 모습을 보여주는 단면도.4 is a cross-sectional view showing a semiconductor package is incorrectly inserted into a conventional semiconductor package insert.

도 5 는 본 발명에 따른 반도체 패키지 인서트의 구조를 보여주는 분리사시도.5 is an exploded perspective view showing the structure of a semiconductor package insert according to the present invention.

도 6 은 본 발명에 따른 반도체 패키지 인서트에 반도체패키지가 장착되는 모습을 보여주는 분리사시도.Figure 6 is an exploded perspective view showing the semiconductor package is mounted on the semiconductor package insert according to the present invention.

도 7 은 본 발명에 따른 반도체 패키지 인서트의 모습을 보여주는 단면도.7 is a cross-sectional view showing a state of a semiconductor package insert according to the present invention.

도 8 과 도 9 는 본 발명에 따른 반도체 패키지 인서트의 측면패키지가이드의 작동모습을 보여주는 단면도.8 and 9 are cross-sectional views showing the operation of the side package guide of the semiconductor package insert according to the present invention.

도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings

100 : 패키지인서트 110 : 패키지안착홈100: package insert 110: package seating groove

130 : 래치 140 : 측면패키지가이드130: latch 140: side package guide

141 : 힌지핀 142 : 힌지공 141: hinge pin 142: hinge ball

145 : 스프링 148 : 스프링수납부145: spring 148: spring storage portion

150 : 패키지가이드장착부 151 : 스프링지지부150: package guide mounting portion 151: spring support

200 : 래치오픈커버 500 : 소켓가이드200: latch open cover 500: socket guide

Claims (3)

표면 양단에는 푸셔유니트(400)의 가이드포스트(410)를 안내하는 가이드홀(120)이 형성되고, 중앙부에는 반도체패키지(300)가 놓이는 패키지안착홈(110)이 형성된 패키지인서트(100)와;Package inserts 100 having guide holes 120 for guiding the guide posts 410 of the pusher unit 400, and a package seating groove 110 in which the semiconductor package 300 is placed in the center of the surface; 패키지안착홈(110)의 양쪽 내벽에서 힌지핀(131)을 중심으로 회동되게 설치되며, 반도체패키지(300)의 공급 및 인출시 오픈되는 래치(130)와;A latch 130 installed pivotally around the hinge pins 131 at both inner walls of the package seating recess 110 and opened when the semiconductor package 300 is supplied and withdrawn; 패키지인서트(100) 위에서 승강되며, 하강시 래치(130)를 오픈시키는 래치오픈커버(200); 로 반도체 패키지 인서트를 구성함에 있어서,A latch open cover 200 which is lifted on the package insert 100 and opens the latch 130 when lowered; In constructing the semiconductor package insert, 패키지인서트(100)의 래치(130)가 설치되는 양쪽 내벽과 직교되는 방향의 양쪽 측면 내벽에는 상단에 힌지핀(141)과 한쌍의 스프링지지부(151)가 구비된 패키지가이드장착부(150)를 형성하고, On both sides of the inner wall in a direction orthogonal to both inner walls on which the latch 130 of the package insert 100 is installed, a package guide mounting part 150 having a hinge pin 141 and a pair of spring supporting parts 151 is formed on an upper end thereof. and, 패키지가이드장착부(150)에는 반도체패키지(300)를 패키지안착홈(110)의 정위치로 안내하는 측면패키지가이드(140)를 힌지공(142)에 의해 힌지핀(141)에 설치하여 패키지안착홈(110) 쪽으로 출몰되도록 회동형으로 설치하되The package guide mounting portion 150 has a side package guide 140 for guiding the semiconductor package 300 to the correct position of the package seating groove 110 on the hinge pin 141 by the hinge hole 142 to install the package seating groove. Install in a rotational manner so that it emerges toward (110) 상측이 개방된 상태에서 내부에 코일스프링(145)이 설치되는 한쌍의 스프링수납부(148)를 측면패키지가이드(140)에 구비하여 상단이 스프링지지부(151)에 걸려 지지되는 코일스프링(145)의 장력에 의해 측면패키지가이드(140)가 패키지안착홈(110)을 향하여 탄력적으로 회동되게 하고, Coil spring 145 having the upper end is caught on the spring support 151 by having a pair of spring receiving part 148 in the side package guide 140 having the coil spring 145 installed therein in the upper side is opened. The side package guide 140 is elastically rotated toward the package seating groove 110 by the tension of the, 패키지인서트(100) 하단에는 측면패키지가이드(140)가 패키지안착홈(110)을 향하여 출몰됨을 안내하는 소켓가이드(500)를 설치한 것At the bottom of the package insert 100, a socket guide 500 for guiding that the side package guide 140 is sunk toward the package seating groove 110 is installed. 을 특징으로 하는 반도체 패키지 인서트. Semiconductor package insert, characterized in that. 제 1 항에 있어서, The method of claim 1, 측면패키지가이드(140)의 힌지공(142)을 수직방향의 장공으로 길게 형성하여 The hinge hole 142 of the side package guide 140 is formed as a long hole in the vertical direction 코일스프링(145)의 장력을 받는 측면패키지가이드(140)가 패키지안착홈(110)을 향하여 전진될 때는 하강되면서 돌출되고, When the side package guide 140, which receives the tension of the coil spring 145, is advanced toward the package seating groove 110, protrudes while descending. 측면패키지가이드(140)가 패키지가이드장착부(150)를 향하여 후진될 때는 상승되면서 들어가게 한 것을 특징으로 하는 반도체 패키지 인서트. When the side package guide 140 is reversed toward the package guide mounting portion 150, the semiconductor package insert, characterized in that the rising as entered. 제 1 항 또는 제 2 항에 있어서,The method according to claim 1 or 2, 측면패키지가이드(140)의 양 측면 하단에는 돌기부(149)를 구비하여, Both side lower ends of the side package guide 140 is provided with protrusions 149, 측면패키지가이드(140)가 패키지가이드장착부(150)에서 돌출되거나 들어갈 때, 측면패키지가이드(140)와 패키지가이드장착부(150) 사이에 공간을 형성하여, 측면패키지가이드(140)와 패키지가이드장착부(150)의 마찰을 줄일 수 있도록 하는 것을 특징으로 하는 반도체 패키지 인서트. When the side package guide 140 protrudes or enters from the package guide mounting unit 150, a space is formed between the side package guide 140 and the package guide mounting unit 150 to form a space between the side package guide 140 and the package guide mounting unit ( A semiconductor package insert, characterized in that to reduce the friction of 150).
KR1020080088908A 2008-09-09 2008-09-09 insert of apparatus of semiconductor package KR100999000B1 (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101322566B1 (en) * 2012-01-11 2013-10-29 세메스 주식회사 Apparatus for mounting a semiconductor device and test handler including the same
US20210265186A1 (en) * 2020-02-20 2021-08-26 Disco Corporation Carrier tray
CN116631958A (en) * 2023-07-19 2023-08-22 成都汉芯国科集成技术有限公司 Diamond material as semiconductor power device and control method thereof

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100769105B1 (en) 2002-03-06 2007-10-22 가부시키가이샤 아드반테스트 Insert and electronic component handler comprising it
AU2003227357A1 (en) 2003-04-23 2004-11-19 Advantest Corporation Insert and tray respectively for electronic component handling device and electronic component handling device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101322566B1 (en) * 2012-01-11 2013-10-29 세메스 주식회사 Apparatus for mounting a semiconductor device and test handler including the same
US20210265186A1 (en) * 2020-02-20 2021-08-26 Disco Corporation Carrier tray
US11521877B2 (en) * 2020-02-20 2022-12-06 Disco Corporation Carrier tray
CN116631958A (en) * 2023-07-19 2023-08-22 成都汉芯国科集成技术有限公司 Diamond material as semiconductor power device and control method thereof
CN116631958B (en) * 2023-07-19 2023-10-13 成都汉芯国科集成技术有限公司 Diamond material as semiconductor power device and control method thereof

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