KR20100030016A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

Info

Publication number
KR20100030016A
KR20100030016A KR1020080088767A KR20080088767A KR20100030016A KR 20100030016 A KR20100030016 A KR 20100030016A KR 1020080088767 A KR1020080088767 A KR 1020080088767A KR 20080088767 A KR20080088767 A KR 20080088767A KR 20100030016 A KR20100030016 A KR 20100030016A
Authority
KR
South Korea
Prior art keywords
gate
hard mask
layer
mask layer
forming
Prior art date
Application number
KR1020080088767A
Other languages
Korean (ko)
Inventor
김현정
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020080088767A priority Critical patent/KR20100030016A/en
Publication of KR20100030016A publication Critical patent/KR20100030016A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to prevent a short-circuit between adjacent gates due to the inclination of the gates by forming a thin hard mask on a upper side of the gates in order to reduce an aspect ratio. CONSTITUTION: Gates(112) including a first gate hard mask layer pattern(110a) is formed on the upper side of a semiconductor substrate(100). A spacer layer(114) is formed on the semiconductor substrate on which the gates are formed. A second gate hard mask layer pattern(110c) is formed to be overlapped with the first gate hard mask pattern on the upper side of the spacer layer.

Description

Manufacturing method of semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a gate of a semiconductor device.

In general, a semiconductor device includes a plurality of unit cells therein. As semiconductor devices are highly integrated, semiconductor devices must be formed at a high density on a predetermined cell area, thereby decreasing the size of unit devices, for example, transistors and capacitors.

In particular, in semiconductor memory devices such as DRAM (Dynamic Random Access Memory), as the design rule is reduced, the size of semiconductor devices formed inside the cell is gradually decreasing.

Therefore, more patterns must be formed within a limited cell area in order to ensure the desired memory capacity, so the critical dimension of the pattern is reduced and the height of the pattern is increased, consequently the aspect ratio continues. Will increase.

1 is a view showing a method of manufacturing a semiconductor device according to the prior art, (a) is a plan view, (b) and (c) is a cross-sectional view taken along the line AA 'of (a).

Referring to FIG. 1, an isolation layer 14 defining an active region 12 is formed in a semiconductor substrate 10. Next, the gate electrode layer 16a, the gate metal layer 16b, and the gate hard mask layer 16c are formed on the semiconductor substrate 10. Next, the gate 16 is formed by etching the gate hard mask layer 16c, the gate metal layer 16b, and the gate electrode layer 16a by a photolithography process using a gate mask (not shown).

However, as the semiconductor devices are highly integrated, the line width of the gate 16 decreases, so that the aspect ratio of the gate 16 increases. Therefore, as illustrated in FIG. 1C, when the gate 16 is inclined, the short gate B of the neighboring gate 16 is caused. In this case, there is a problem that it is difficult to proceed with the subsequent process, the device can not be implemented normally. In order to solve this problem, reducing the thickness of the gate hard mask layer 16c may damage the gate metal layer 16b while losing the gate hardmask layer 16c during the subsequent landing plug contact process.

The present invention has the following object.

First, it is possible to prevent the phenomenon that the gate is inclined and shorted with the neighboring gate during the etching process for forming the gate by reducing the aspect ratio by forming the hard mask layer on the gate to a low thickness.

Second, after the gate is formed, a gate hard mask layer is separately formed on the gate so as to overlap the gate, thereby preventing damage to the gate due to loss of the gate hard mask layer during the landing plug contact forming process.

A method of manufacturing a semiconductor device according to the present invention includes forming a gate including a first gate hard mask layer pattern on a semiconductor substrate; Forming a spacer layer on the semiconductor substrate including the gate; And forming a second gate hard mask layer pattern on the spacer layer so as to overlap the first gate hard mask layer pattern.

The forming of the gate may include forming a gate electrode layer, a gate metal layer, and the first gate hard mask layer on the semiconductor substrate; And etching the first gate hard mask layer, the gate metal layer, and the gate electrode layer by a photolithography process using a gate mask.

The spacer layer may be formed of the same material as the first gate hard mask layer pattern, and after the forming of the spacer layer, forming a first insulating layer on the spacer layer. And planarizing etching the first insulating layer until the spacer layer is exposed.

The forming of the second gate hard mask layer pattern may include forming a second gate hard mask layer on the first insulating layer and the spacer layer; Forming a photoresist pattern on the second gate hard mask layer to expose the first insulating layer; Etching the first insulating layer using the photoresist pattern as an etching mask; And removing the photoresist pattern.

The method may further include forming a second insulating film on the first insulating film and the second hard mask layer pattern; Planarization etching the second insulating layer until the second hard mask layer pattern is exposed; Etching the second insulating film, the first insulating film, and the spacer film to form a landing plug contact hole exposing the semiconductor substrate; And filling a conductive film in the landing plug contact hole to form a landing plug contact.

The present invention provides the following effects.

First, by forming the hard mask layer on the gate to a low thickness to reduce the aspect ratio, it provides an effect that can prevent the gate is inclined and short-circuit with the neighboring gate during the etching process for forming the gate.

Second, after the gate is formed, a gate hard mask layer is separately formed on the gate so as to overlap the gate, thereby providing an effect of preventing damage to the gate due to loss of the gate hard mask layer during the landing plug contact forming process.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2H are diagrams illustrating a method of manufacturing a semiconductor device according to the present invention, (a) is a plan view, and (b) is a cross-sectional view taken along the line C-C 'of (a).

Referring to FIG. 2A, an isolation layer 104 defining an active region 102 is formed in the semiconductor substrate 100. Next, a gate electrode layer (not shown), a gate metal layer (not shown), and a first gate hard mask layer (not shown) are formed on the semiconductor substrate 100. Here, the first gate hard mask layer is preferably formed at a lower height than the conventional gate hard mask layer 16c (see FIG. 1). The gate electrode layer is preferably formed of a polysilicon layer, the gate metal layer is formed of a tungsten (W) layer, and the first gate hard mask layer is formed of a nitride film.

Next, the first gate hard mask layer, the gate metal layer, and the gate electrode layer are etched by a photolithography process using a gate mask (not shown) to form the first gate hard mask layer pattern 110a, the gate metal layer pattern 108, and the gate electrode layer. Pattern 106 is formed. As a result, the gate 112 is formed. Here, since the height of the first gate hard mask layer is lowered, the aspect ratio of the gate 112 is reduced compared to the related art, and thus, the gate 112 may be prevented from falling during the photolithography process using the gate mask.

Referring to FIG. 2B, a spacer layer 114 is formed on the semiconductor substrate 100 including the gate 112. Here, the spacer layer 114 is to prevent a short between the landing plug contact and the gate 112 to be formed in a subsequent process, and is preferably formed of the same material as the first gate hard mask layer pattern 110a.

Referring to FIG. 2C, the first insulating layer 116 is formed on the spacer layer 114, and the first insulating layer 116 is planarized until the spacer layer 114 is exposed. Here, the first insulating layer 116 is buried between the gates 112 to support the gates 112 so as not to fall, and the etching layer and the spacer layer 114 and the first gate hard mask layer pattern 110a are selected. It is preferable to form with a material with a difference, for example, an oxide film.

Referring to FIG. 2D, a second gate hard mask layer 110b is formed on the first insulating layer 116 and the spacer layer 114. Here, the second gate hard mask layer 116b is preferably formed of the same material as the first gate hard mask layer pattern 110a.

The thickness of the second gate hard mask layer 116b is the sum of the thicknesses of the second gate hard mask layer 116b, the spacer layer 114, and the first gate hard mask layer pattern 110a. The thickness is adjusted to be equal to the thickness of the hard mask layer 16c (see FIG. 1).

Referring to FIG. 2E, a photoresist pattern 118 exposing the first insulating layer 116 is formed on the second gate hard mask layer 110b.

Referring to FIG. 2F, the second gate hard mask layer 110b is etched using the photoresist pattern 118 as an etch mask to form the second gate hard mask layer pattern 110c.

Referring to FIG. 2G, the photoresist layer pattern 118 is removed, and a second insulation layer 120 is formed on the second gate hard mask layer pattern 110c and the first insulation layer 116. Next, the second insulating layer 120 is planarized and etched until the second gate hard mask layer pattern 110c is exposed.

Referring to FIG. 2H, the second insulating layer 120, the first insulating layer 116, and the spacer layer 114 are etched to expose the semiconductor substrate 100 by a photolithography process using a landing plug contact mask (not shown). Landing plug contact holes (not shown) are formed. Here, since the second gate hard mask layer pattern 110c is formed thick in the landing plug contact hole forming process, the lower gate 112 may be prevented from being damaged.

Next, a conductive film (not shown) is formed on the entire surface including the landing plug contact hole, and the landing film contact 122 is formed by planarizing etching of the conductive film until the second gate hard mask layer pattern 110c is exposed. .

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

1 is a view showing a method for manufacturing a semiconductor device according to the prior art.

2A to 2H illustrate a method of manufacturing a semiconductor device according to the present invention.

Claims (6)

Forming a gate including a first gate hard mask layer pattern on the semiconductor substrate; Forming a spacer layer on the semiconductor substrate including the gate; And Forming a second gate hard mask layer pattern on the spacer layer to overlap the first gate hard mask layer pattern Method of manufacturing a semiconductor device comprising a. The method of claim 1, wherein the forming of the gate Forming a gate electrode layer, a gate metal layer, and the first gate hard mask layer on the semiconductor substrate; And Etching the first gate hard mask layer, the gate metal layer, and the gate electrode layer by a photolithography process using a gate mask Method of manufacturing a semiconductor device comprising a. The method of claim 1, wherein the spacer layer is formed of the same material as the first gate hard mask layer pattern. The method of claim 1, wherein after forming the spacer film Forming a first insulating film on the spacer film; And Planar etching the first insulating layer until the spacer layer is exposed Method of manufacturing a semiconductor device further comprising. The method of claim 4, wherein the forming of the second gate hard mask layer pattern is performed. Forming a second gate hard mask layer on the first insulating film and the spacer film; Forming a photoresist pattern on the second gate hard mask layer to expose the first insulating layer; Etching the first insulating layer using the photoresist pattern as an etching mask; And Removing the photoresist pattern Method of manufacturing a semiconductor device comprising a. The method of claim 4, wherein Forming a second insulating film on the first insulating film and the second hard mask layer pattern; Planarization etching the second insulating layer until the second hard mask layer pattern is exposed; Etching the second insulating film, the first insulating film, and the spacer film to form a landing plug contact hole exposing the semiconductor substrate; And Filling a conductive film in the landing plug contact hole to form a landing plug contact Method of manufacturing a semiconductor device further comprising.
KR1020080088767A 2008-09-09 2008-09-09 Method for manufacturing semiconductor device KR20100030016A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020080088767A KR20100030016A (en) 2008-09-09 2008-09-09 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020080088767A KR20100030016A (en) 2008-09-09 2008-09-09 Method for manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
KR20100030016A true KR20100030016A (en) 2010-03-18

Family

ID=42180059

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020080088767A KR20100030016A (en) 2008-09-09 2008-09-09 Method for manufacturing semiconductor device

Country Status (1)

Country Link
KR (1) KR20100030016A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160009754A (en) * 2014-07-16 2016-01-27 삼성전자주식회사 Method for manufacturing a semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160009754A (en) * 2014-07-16 2016-01-27 삼성전자주식회사 Method for manufacturing a semiconductor device

Similar Documents

Publication Publication Date Title
US6486558B2 (en) Semiconductor device having a dummy pattern
US20230056204A1 (en) Semiconductor structure and method for manufacturing same
KR20100111889A (en) Semiconductor device and method for forming it
JP4314278B2 (en) Semiconductor device and manufacturing method thereof
US20150214234A1 (en) Semiconductor device and method for fabricating the same
KR100827509B1 (en) Method for forming semiconductor device
KR20110001142A (en) Method for fabricating contacts in semiconductor device
KR20110132753A (en) Method for manufacturing semiconductor device
KR20100030016A (en) Method for manufacturing semiconductor device
KR20120004802A (en) Method for fabricating semiconductor device
KR100935198B1 (en) Semiconductor device and method for manufacturing the same
KR20060108432A (en) Dram device and methodp of forming the same
US11798837B2 (en) Methods for forming openings in conductive layers and using the same
KR101116287B1 (en) Vertical channel transistor of semiconductor device and method for forming the same
KR101172310B1 (en) Method for fabricating semiconductor device
KR101067875B1 (en) Method of manufacturing semiconductor device
KR20080086692A (en) Method for manufacturing semiconductor device
KR100811415B1 (en) Method for manufacturing semiconductor device
TW202220174A (en) Semiconductor device
KR100444312B1 (en) Method for forming fine contact of semiconductor device using insulating spacer
KR20090112925A (en) Method for manufacturing semiconductor device
KR100844939B1 (en) Method for manufacturing semiconductor device with gate line of fine line width
CN116685141A (en) Manufacturing method of semiconductor structure and structure thereof
KR20060000898A (en) Method for fabrication of semiconductor device
KR20060075971A (en) Method for fabrication of semiconductor device capable of increasing overlay margin

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E601 Decision to refuse application