KR20100024156A - Metal insulator metal capacitor and the manufacturing method thereof - Google Patents

Abstract

PURPOSE: A metal insulator metal(MIM) capacitor and a method for manufacturing the same are provided to obtain the high level of capacitance by alternately stacking a metal layer and an insulation layer and connecting the MIM capacitor in parallel. CONSTITUTION: A first interlayer insulation layer(110) forms a lower wire pattern and an etching part. A first metal layer(M1) is formed on the inner side and the upper side of the etching part. A first insulation layer(I1) is formed on the upper side of the first metal layer. A second metal layer(M2) is formed to cover the upper side of the first insulation layer. A second insulation layer(I2) is formed to cover the one upper side of the second metal layer. A third metal layer(M3) is formed to cover the upper side of the second insulation layer.

Description

MIM capacitor and its manufacturing method {METAL INSULATOR METAL CAPACITOR AND THE MANUFACTURING METHOD THEREOF}

The present invention relates to a MIM capacitor and a method for manufacturing the same. More specifically, the MIM capacitor has various capacitances in series or parallel connection according to the connection of the upper wiring pattern, and has a higher capacitance than a series connection of the same area by connecting in parallel. It relates to a MIM capacitor capable of having and a method of manufacturing the same.

As the use of semiconductor integrated circuits is diversified, analog capacitors formed in the logic circuit area also require high speed and large capacity. In order to achieve a high speed capacitor, the resistance of the electrode of the capacitor should be lowered to reduce the frequency dependency.

In general, when a high-capacitance capacitor has a PIP (Polysilicon-Insulator-Polysilicon) structure, since the upper electrode and the lower electrode are used as the conductive polysilicon, an oxidation reaction occurs at the upper electrode, the lower electrode, and the insulator thin film interface to form a natural oxide film. The disadvantage is that the total capacitance is reduced in size.

In order to solve this problem, the structure of the capacitor has been changed to MIM (Metal-Insulator-Metal). The MIM type capacitor has a high resistivity and high parasitic capacitance due to depletion. Mainly used in.

However, in order to achieve a large capacity capacitor, since the thickness of the capacitor insulating film is reduced, an insulating film with a high dielectric constant is used, or the area of the capacitor is increased, the area for forming the capacitor is substantially formed to form a large capacity capacitor used in a high performance semiconductor device. And increased thickness, which may affect the degree of integration of the device.

The present invention is to overcome the above-mentioned problems, an object of the present invention is to provide a MIM capacitor and a method for manufacturing the same by connecting the MIM capacitor in series or parallel according to the connection of the upper wiring pattern and having various capacitances. have.

In addition, another object of the present invention is to provide a MIM capacitor and a method of manufacturing the same by sequentially stacking a metal layer and an insulating film and connecting the MIM capacitors in parallel to have a high capacitance.

In order to achieve the above object, the MIM capacitor and the method of manufacturing the same according to the present invention are formed on the inside and the upper portion of the first interlayer insulating film and the etching portion of the first interlayer insulating film is formed at least one lower wiring pattern is formed; A first metal layer electrically connected to at least one lower wiring, a first insulating layer formed on the first metal layer formed on the etching unit, a second metal layer formed to cover an upper portion of the first insulating layer, and It may include a second insulating film formed to cover one side of the upper portion of the second metal layer and a third metal layer formed to cover the upper portion of the second insulating film.

The second insulating layer may be further formed to cover an upper portion of the other side of the first metal layer.

The first metal layer, the second metal layer and the third metal layer may be electrically connected to each other.

A substrate preparation step of preparing a substrate by forming an upper portion of at least one lower wiring pattern to be exposed in the first interlayer insulating layer, and an interlayer first etching layer forming an trench portion by etching inward from an upper direction of the first interlayer cutting film. An insulating film etching step, a first MIM forming step of sequentially stacking a first metal layer, a first insulating film, and a second metal layer on the upper and the etching portions of the first interlayer insulating film; and the second metal layer, the first insulating film, and the first insulating film. Planarizing the metal layer to planarize the upper portion of the first metal layer formed on the first interlayer insulating layer and to cover the upper portion of the first interlayer insulating layer, the first metal layer and the second metal layer; A second MIM forming step of sequentially stacking a second insulating layer and a third metal layer; A second MIM patterning step of patterning and removing the inner layer and the second insulating layer, and an upper wiring pattern forming step of forming an upper wiring pattern on an upper portion of the first metal layer, an upper portion of the second metal layer, and an upper portion of the third metal layer. .

After the second MIM patterning step, the method may further include a first metal layer etching step of etching and removing the first metal layer to expose the upper portion of the at least one lower wiring pattern to the outside.

As described above, the MIM capacitor and the method of manufacturing the same according to the present invention may have various capacitances by connecting the MIM capacitors in series or in parallel according to the connection of the upper wiring pattern.

In addition, as described above, the MIM capacitor and the manufacturing method thereof according to the present invention can have a high capacitance by alternately stacking the metal layer and the insulating film and connecting the MIM capacitor in parallel.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art may easily implement the present invention. Here, parts having similar configurations and operations throughout the specification are denoted by the same reference numerals.

Referring to FIG. 1, there is shown a cross-sectional view of a MIM capacitor in accordance with one embodiment of the present invention.

As illustrated in FIG. 1, the MIM capacitor 100 may include a first interlayer insulating layer 110 having at least one lower wiring pattern 111 and 121 formed thereon, and a first metal layer formed on the first interlayer insulating layer 110. M1), the first insulating layer I1 formed on the first metal layer M1, the second metal layer M2 formed on the first insulating layer, and the other side and the second metal layer M2 on the first metal layer. ), The second insulating layer I2 formed on one side of the upper side of the upper part), the third metal layer M3 formed on the second insulating layer I2, the lower wiring pattern 111, the first metal layer M1, and the second The second interlayer insulating layer 120 exposing the upper wiring patterns 121, 122, 123, 124, and 125 formed on the metal layer M2 and the third metal layer M3 to the outside is included.

Lower wiring patterns 111 and 121 are formed in the first interlayer insulating layer 110 from the upper side to the inner side. The first interlayer insulating layer 110 may be formed on the semiconductor substrate (not shown). An etching portion 110a is formed in the first interlayer insulating layer 110 from the upper side to the inner side, and the inside of the etching portion 110a includes the first metal layer M1, the first insulating layer I1, and the second metal layer. (M2) is formed by stacking sequentially. The first lower interconnection pattern 111 may be electrically connected to the first upper interconnection pattern 121 among the lower interconnection patterns 111 and 112, and the second lower interconnection pattern 112 may be one side of the first metal layer M1. It may be electrically connected to M1a. Copper (Cu) may be preferably used for the lower wiring patterns 111 and 121, but the metal material is not limited thereto. The first interlayer insulating film 110 may be formed of an oxide film in a plurality of layers, but the present invention is not limited thereto.

The first metal layer M1 is formed to extend a predetermined distance inside the etching unit 110a of the first interlayer insulating layer 110 and above the first interlayer insulating layer 110. In this case, one side M1a of the first metal layer M1 is formed to cover an upper portion of the second lower wiring pattern 112, and the second lower wiring pattern 112 and the second upper wiring pattern 122 are formed. The second lower wiring pattern 112 and the second upper wiring pattern 122 may be electrically connected to each other. The first insulating layer I1 is formed on the first metal layer M1 formed in the etching unit 110a in the first metal layer M1. The other side M1b of the first metal layer M1 may extend above the first interlayer insulating layer 110, and a second insulating layer I2 may be formed thereon. The first metal layer M1 may be made of titanium (Ti), titanium nitride (TiN), and equivalents thereof, but is not limited thereto.

The first insulating layer I1 is formed between the second metal layer M2 and the upper portion of the first metal layer M1 formed inside the etching unit 110a of the first interlayer insulating layer 110. That is, the first insulating layer I1 is formed between the first metal layer M1 and the second metal layer M2 to form a metal insulator metal (MIM) capacitor structure. The first insulating layer I1 may be formed of a nitride film SiNx, but is not limited thereto.

The second metal layer M2 is formed to cover all the upper portions of the first insulating layer I1. The second insulating layer I2 is formed on one side M2a of the second metal layer M2 and the fourth upper wiring pattern 124 is formed on the other side M2b. The second metal layer M2 forms a MIM capacitor structure with the first metal layer M1 and the first insulating layer I1. The second metal layer M2 may be made of titanium (Ti), titanium nitride (TiN), and equivalents thereof, but is not limited thereto.

The second insulating layer I2 is formed on one side M2a of the upper portion of the second metal layer M2 and the other side M1b of the upper portion of the first metal layer M1. The third metal layer M3 is formed on the second insulating layer I2. That is, in the second insulating layer I2 formed on one side M2a of the second metal layer M2, the second metal layer M2, the second insulating layer I2, and the third metal layer M3 have the structure of the MIM capacitor. The second insulating film I2 formed on the other side M1b of the upper portion of the first metal layer M1 may include the first metal layer M1, the second insulating film I2, and the third metal layer M3 of the MIM capacitor. It can be a structure. The second insulating layer I2 may be formed of a nitride film SiNx, but is not limited thereto.

The third metal layer M3 may be formed to cover all of the upper portions of the second insulating layer I2, and upper wiring patterns 123 and 125 may be formed thereon. A third upper wiring pattern 123 is formed on the third metal layer M3 formed on one side M2a of the second metal layer M2 in the third metal layer M3, and the first metal layer ( The fifth upper wiring pattern 125 may be formed on the third metal layer M3 formed on the other side M1b of the upper part of the M1. The third metal layer M3 may be made of titanium (Ti), titanium nitride (TiN), and equivalents thereof, but is not limited thereto.

The second interlayer insulating layer 120 is formed to cover all the upper portions of the first interlayer insulating layer 110, and the upper portions of the upper wiring patterns 121, 122, 123, 124, and 125 are exposed to the outside. In this case, the upper wiring patterns 121, 122, 123, 124, and 125 are connected to the first upper wiring pattern 121 and one side M1a of the first metal layer M1 electrically connected to the first lower wiring pattern 111. The second upper interconnection pattern 122 electrically connected, the third upper interconnection pattern 123 electrically connected to the third metal layer M3 formed on one side M2a of the upper portion of the second metal layer M2, and the second upper interconnection pattern 122. The fourth upper wiring pattern 124 electrically connected to the other side M2b of the metal layer M2 and the fifth upper part electrically connected to the third metal layer M3 formed on the other side M1b of the upper portion of the first metal layer M1. The wiring pattern 125 may be included. The upper wiring patterns 121, 122, 123, 124, and 125 may be exposed to an upper portion of the second interlayer insulating layer 120 to connect MIM capacitors in series or in parallel. Although the upper wiring patterns 121, 122, 123, 124, and 125 are illustrated as five in FIG. 1, the number of the upper wiring patterns is not limited in the present invention. Copper (Cu) may be used for the upper wiring patterns 121, 122, 123, 124, and 125, but the metal material is not limited thereto. The second interlayer insulating film 120 may preferably be formed of an oxide film in multiple layers, but is not limited thereto.

The MIM capacitor 100 has a plurality of upper wiring patterns 121, 122, 123, 124, and 125 and a plurality of capacitances according to a connection relationship of the upper wiring patterns 121, 122, 123, 124, and 125. Can have For example, when different thicknesses of the first insulating film I1 and the second insulating film I2 affecting the capacitance are formed, the second upper wiring pattern 122 and the fourth upper wiring pattern 124 may be selected. The capacitance at the time of selecting the second upper wiring pattern 122 and the fifth upper wiring pattern 125 may be different. When the second upper wiring pattern 122 and the third upper wiring pattern 123 are connected to each other, and the fourth upper wiring pattern 124 and the second upper wiring pattern 122 are selected, two MIM capacitors are parallel to each other. Since the structure is connected to each other, it is possible to have a higher capacitance than the MIM capacitor formed in the same space. That is, the MIM capacitor 100 may have various capacitances, and may have a higher capacitance when formed in the same space.

Referring to FIG. 2, a flowchart illustrating a method of manufacturing the MIM capacitor of FIG. 1 is shown.

As shown in FIG. 2, the method of manufacturing a MIM capacitor includes a substrate preparation step S1, a first interlayer insulating film etching step S2, a first MIM forming step S3, a planarizing step S4, and a second MIM forming step S5. ), A second MIM patterning step S6, a first metal layer etching step S7, and an upper wiring pattern forming step S8. Such a method of manufacturing the MIM capacitor will be described in detail with reference to FIGS. 3A to 3H.

3A to 3H, cross-sectional views illustrating a method of manufacturing the MIM capacitor shown in FIG. 2 are shown.

As shown in FIG. 3A, in the substrate preparing step S1, a semiconductor device formed on the semiconductor substrate by applying a first interlayer insulating layer 110 on a semiconductor substrate (not shown) and forming a contact hole on one side thereof; At least one lower wiring pattern 111 and 112 is formed to be electrically connected to the integrated circuit to prepare a substrate. The first lower wiring patterns 111 and the second lower wiring patterns 112, which are the lower wiring patterns 111 and 112, are formed to be exposed to the upper portion of the first interlayer insulating layer 110, and may be formed by a damascene method. have. The first interlayer insulating layer 110 may be formed of a multilayer to prevent diffusion of impurities. The first interlayer insulating layer 110 may be formed using any one selected from thermal oxidation, chemical vapor deposition (CVD), physical vapor deposition (PVD), and the like. However, the method is not limited thereto.

As illustrated in FIG. 3B, in the first interlayer insulating layer etching step S2, the first interlayer insulating layer 110 may be etched to form an etching unit 110a. In this case, the etching unit 110a may be formed in a trench shape from the upper side of the first interlayer insulating layer 110 on which the lower wiring patterns 111 and 112 are not formed. The method of etching the first interlayer insulating layer 110 may be performed by photolithography, dry etching, or an equivalent thereof, but is not limited thereto.

As shown in FIG. 3C, in the first MIM forming step S3, the first metal layer M1 and the first insulating layer I1 are covered to cover both the lower wiring patterns 111 and 112 and the first interlayer insulating layer 110. ) And the second metal layer M2 are sequentially stacked. In this case, the first metal layer M1, the first insulating layer I1, and the second metal layer M2 are formed to be stacked inside the etching unit 110a.

As shown in FIG. 3D, in the planarization step S4, the second metal layer M2 and the first insulating layer I1 formed in the first MIM formation step S3 are sequentially planarized to form the first metal layer M1. Let the top of) be exposed to the outside. That is, in the planarization step S4, the first metal layer M1 formed on the first interlayer insulating layer 110 is exposed to the outside by planarizing the second metal layer M2 and the first insulating layer I1. Only the first metal layer M1 remains on the first interlayer insulating layer 110, and the first metal layer M1, the first insulating layer I1, and the second metal layer M2 are disposed inside the etching unit 110a. It is stacked. The planarization may be formed by any one method selected from chemical mechanical polishing (CMP) and equivalent methods, and the method is not limited thereto.

As shown in FIG. 3E, in the second MIM formation step S5, the second insulating layer I2 and the third metal layer M3 are sequentially stacked on the planarized surface in the planarization step S4. That is, the second insulating layer I2 and the third metal layer M3 are sequentially stacked to cover both the second metal layer M2 and the upper portion of the first metal layer M1 exposed to the outside in the planarization step S4. To form.

As shown in FIG. 3F, in the second MIM patterning step S6, the third metal layer is exposed such that one side M1a of the first metal layer M1 and the other side M2b of the second metal layer M2 are exposed to the outside. The third metal layer M3 and the second insulating layer I2 may be patterned by removing the M3 and the second insulating layer I2 by etching. That is, the third metal layer M3 and the second insulating layer I2 are patterned, so that the second insulating layer I2 and the third metal layer M3 are the other side M1b and the second of the first metal layer M1. Only the upper portion of one side M2a of the metal layer M2 remains. The method of patterning the third metal layer M3 and the second insulating layer I2 may be performed by photolithography or an equivalent thereof, but is not limited thereto.

As illustrated in FIG. 3G, in the first metal layer etching step S7, one side of the first metal layer M1 may be etched and removed to expose the upper portion of the first lower wiring pattern 111 to the outside. . The method of etching the first metal layer M1 may be performed by photolithography or an equivalent method thereof, but is not limited thereto.

As shown in FIG. 3H, in the upper wiring pattern forming step S8, the first interlayer insulating layer 110, the first lower wiring pattern 111, the first metal layer M1, the second metal layer M2, and The second interlayer insulating layer 120 is formed to cover all of the third metal layers M3. Thereafter, the second interlayer insulating layer 120 may expose the first lower wiring pattern 111, one side M1a of the first metal layer M1, a third metal layer M3, and a part of the second metal layer M2 to the outside. A contact hole is formed if possible. Thereafter, upper wiring patterns 121, 122, 123, 124, and 125 are formed to fill all of the contact holes. The upper wiring patterns 121, 122, 123, 124, and 125 may be formed by a damascene method. The second interlayer insulating layer 120 may be formed of a multilayer to prevent diffusion of impurities.

What has been described above is just one embodiment for carrying out the MIM capacitor and its manufacturing method according to the present invention, the present invention is not limited to the above embodiment, as claimed in the following claims Without departing from the gist of the present invention, those skilled in the art to which the present invention pertains to the technical spirit of the present invention to the extent that various modifications can be made.

1 is a cross-sectional view showing a MIM capacitor according to an embodiment of the present invention.

FIG. 2 is a flowchart illustrating a method of manufacturing the MIM capacitor of FIG. 1.

3A to 3H are cross-sectional views illustrating a method of manufacturing the MIM capacitor shown in FIG. 2.

<Description of Symbols for Main Parts of Drawings>

110; First interlayer insulating films 111 and 112; Bottom wiring pattern

120; Second interlayer insulating films 121, 122, 123, 124, and 125; Upper wiring pattern

M1; First metal layer I1; First insulating film

M2; Second metal layer I2; Second insulating film

M3; Third metal layer

Claims (5)

A first interlayer insulating layer on which at least one lower wiring pattern is formed and an etching portion is formed; A first metal layer formed on an inner side and an upper side of an etching portion of the first interlayer insulating layer, and one side of which is electrically connected to at least one lower wiring line; A first insulating layer formed on the first metal layer formed on the etching portion; A second metal layer formed to cover an upper portion of the first insulating layer; A second insulating layer formed to cover one side of the upper portion of the second metal layer; And MIM capacitor comprising a third metal layer formed to cover the upper portion of the second insulating film. The method of claim 1, The second insulating layer is MIM capacitor, characterized in that further formed to cover the upper portion of the other side of the first metal layer. The method of claim 1, MIM capacitor, characterized in that the upper wiring pattern is further formed to be electrically connected to the first metal layer, the second metal layer and the third metal layer. A substrate preparation step of preparing a substrate by forming an upper portion of at least one lower wiring pattern on the first interlayer insulating layer; Etching the first interlayer insulating film to form a trench-etched portion by etching inward from an upper direction of the first interlayer cut film; A first MIM forming step of sequentially stacking a first metal layer, a first insulating film, and a second metal layer on the first interlayer insulating film and the etching part; Planarizing the second metal layer, the first insulating layer and the first metal layer to planarize the upper portion of the first metal layer formed on the first interlayer insulating layer; A second MIM forming step of sequentially stacking a second insulating film and a third metal layer to cover all of the first interlayer insulating film, the first metal layer, and the second metal layer; A second MIM patterning step of patterning and removing the third metal layer and the second insulating layer so that one side of the upper portion of the first metal layer and the upper portion of the second metal layer is exposed to the outside; And And forming an upper wiring pattern on the upper part of the first metal layer, the upper part of the second metal layer, and the upper part of the third metal layer. The method of claim 4, wherein After the second MIM patterning step And etching the first metal layer by removing the first metal layer so that the upper portion of the at least one lower wiring pattern is exposed to the outside.

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