KR20100023135A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PURPOSE: A semiconductor device and a manufacturing method of the same are provided to improve leakage current by preventing the exposure of a semiconductor substrate due to an excessive etch. CONSTITUTION: A semiconductor device comprises an element isolation film(109), a gate insulating layer(103), a conductive film(105), and a compensation layer(113). The element isolation film fills in the trench. The element isolation film comprises a groove portion(111). The gate insulating layer and the conductive film are laminated on the semiconductor substrate. The compensation layer fills the groove portion.

Description

Semiconductor device and manufacturing method of the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device and a method for manufacturing the same, which prevent leakage of a semiconductor substrate through a groove formed by overetching a sidewall of the device isolation layer, thereby improving leakage current. .

The semiconductor device is divided into a cell array region in which memory cells storing data and a peripheral region in which circuits for applying driving signals to memory cells are formed.

A plurality of string structures are formed in the cell array region. Each string structure includes a source select transistor, a drain select transistor, and a plurality of memory cells connected in series between the source select transistor and the drain select transistor.

The peripheral area includes a high voltage NMOS (hereinafter referred to as "HVN") transistor, a low voltage NMOS (hereinafter referred to as "LVN") transistor, and a low voltage PMOS (hereinafter referred to as "LVP"). "Transistor".

As described above, each transistor and memory cell formed in the peripheral region and the cell array region includes a gate pattern. The gate pattern is formed on the active region of the semiconductor substrate with the gate insulating film interposed therebetween. In the case of a flash memory device, the gate pattern has a structure in which a floating gate conductive film, a dielectric film, and a control gate conductive film are stacked. The control gate conductive film of the transistor exposes the conductive film for the floating gate and is electrically connected to the conductive film for the floating gate through a contact hole formed in the dielectric film. In addition, the active region of the semiconductor substrate is isolated with the device isolation layer formed inside the trench formed by etching the device isolation region of the semiconductor substrate. Recently, by using the same hard mask pattern as an etching barrier, the floating gate conductive film and the semiconductor substrate are etched to automatically align the floating gate conductive film in the active region and to form a trench in the device isolation region.

After forming the conductive film and the trench for the floating gate using the above-described Advanced Self Aligned-Shallow Trench Isolation (ASA-STI) method, the device isolation film is formed by filling the trench with the insulating film for the device isolation film. In this case, the insulating film for the device isolation layer may include an insulating film of two or more layers in order to improve the gap-fill characteristics of the trench having an increased aspect ratio according to high integration of the semiconductor device. In particular, a high density plasma (HDP) oxide film is formed on the lowermost layer of the insulating film for device isolation film, which has a characteristic of being deposited on the bottom of the trench thicker than the sidewall of the trench to reduce the aspect ratio of the trench.

In general, the size of the trench and the width of the active region are not the same in all regions of the semiconductor substrate, but are larger in the peripheral region than in the cell array region. Accordingly, the HDP oxide film is formed thicker in the peripheral region.

After forming the device isolation layer including the HDP oxide film, the hard mask pattern used as the etching barrier is removed. The etchant used to remove the hard mask pattern may penetrate the HDP oxide having a high wet etching rate. In particular, since the HDP oxide film formed on the sidewalls of the trench in the peripheral region is thicker than the HDP oxide film formed on the sidewalls of the trench in the cell array region, the etching degree is large. As a result, grooves (for example, moats) are generated on the sidewalls of the device isolation layer in the peripheral region by etching the HDP oxide layer. When the cleaning process is performed to remove the residues remaining after the etching process, the HDP film is additionally etched through the cleaning solution, thereby increasing the depth of the groove formed in the sidewall of the trench in the peripheral area, thereby exposing the semiconductor substrate. As described above, the semiconductor substrate exposed in the peripheral region is connected to the control gate layer formed in a subsequent process to generate a leakage current when driving the semiconductor device.

The present invention provides a semiconductor device and a method of manufacturing the same, which prevent leakage of a semiconductor substrate through a groove formed by over-etching a sidewall of the device isolation layer, thereby improving leakage current.

A semiconductor device according to an embodiment of the present invention fills a trench formed in a semiconductor substrate and is formed higher than the surface of the semiconductor substrate and includes a device isolation layer including a groove on a sidewall and a gate stacked on the semiconductor substrate with the device isolation layer therebetween. An insulating film, a conductive film, and a compensation film filling the groove portion.

In the method of manufacturing a semiconductor device according to an embodiment of the present invention, a trench is formed in device isolation regions, and a semiconductor substrate formed by stacking a gate insulating film, a conductive film, and a hard mask pattern on active regions spaced apart from each other with a trench therebetween. Providing, forming a device isolation film in the trench higher than the surface of the semiconductor substrate, removing the hard mask pattern, and forming a compensation film filling the groove formed in the sidewall of the device isolation film while removing the hard mask pattern. Include.

After forming the compensation film filling the groove, a process of cleaning the contaminants remaining on the conductive film and the compensation film is performed.

A method of manufacturing a semiconductor device according to another embodiment of the present invention includes a first region in which a first trench is formed and a second region in which a second trench is denser than the first trench, and between the first and second trenches. Providing a semiconductor substrate in which a gate insulating film, a conductive film and a first hard mask pattern are stacked on the active regions separated from each other, and between the first and second trenches, the first hard mask film, the conductive film, and the gate insulating film. Forming an isolation layer to fill the space, removing the first hard mask pattern, and compensating an upper portion of the isolation layer and the conductive layer so as to fill a groove formed in a sidewall of the isolation layer while removing the first hard mask pattern. Forming a film; forming a second hard mask pattern on the compensation film formed in the first region; removing the compensation film formed in the second region; Lowering the height of the formed device isolation layer, and removing the second hard mask pattern, and removing the compensation layer on the conductive layer of the first region.

After removing the compensation film on the conductive film of the first region, a process of cleaning the contaminants remaining on the conductive film and the compensation film is performed.

The device isolation layer is formed along the sidewalls of the trench and the sidewalls of the gate insulating layer while filling the bottom surface of the trench, and includes a first insulating film including grooves and a second insulating film formed on the first insulating film and filling the trench to a height lower than that of the semiconductor substrate. And a third insulating film formed on the second insulating film and formed higher than the surface of the gate insulating film.

The first insulating film is formed of an HDP (High Density Plasma) oxide film.

The second insulating film is formed of a PSZ (polysilizane) film.

The compensation film is formed of an oxide film.

According to the present invention, the grooves formed on the sidewalls of the device isolation layers are filled using the compensation layer, and thus, even when the cleaning process is performed, the depth of the grooves is further deepened to prevent the semiconductor substrate from being exposed. Accordingly, the present invention can prevent the phenomenon in which the conductive film is connected to the semiconductor substrate through the groove portion, thereby improving leakage current generation of the semiconductor device, thereby stabilizing operating characteristics of the semiconductor device.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention. Hereinafter, a case in which a flash device is formed by using an Advanced Self Aligned-Shallow Trench Isolation (ASA-STI) method will be described as an example.

Referring to FIG. 1A, a gate insulating layer 103, a floating conductive first conductive layer 105, and a first hard mask pattern 107 are stacked on an active region, and a first hard mask pattern 107 is disposed on an isolation region. A semiconductor substrate 100 is provided in which the device isolation layer 109 is filled to a height of.

Specifically, the semiconductor substrate 100 is divided into a cell array region where memory cells and a select transistor are to be formed, and a peripheral region outside the cell array region. The cell array region is a portion in which a string structure including a source select transistor, a drain select transistor, and a plurality of memory cells connected in series between the source select transistor and the drain select transistor is formed. The peripheral area is a high voltage NMOS transistor (hereinafter referred to as "HVN TR") for driving memory cells and a low voltage NMOS transistor (hereinafter referred to as "LVN TR") (not shown). And a low voltage PMOS transistor (hereinafter referred to as "LVP TR"). In the semiconductor substrate 100, a bulk structure including at least one of a P-well, an N-well, and a TN (Triple N) well is formed in advance, and threshold voltage control ions are pre-injected. have.

The gate insulating film 103 and the first conductive film 105 are stacked on the semiconductor substrate 100 on which the bulk structure forming step and the threshold voltage ion implantation step are performed. Thereafter, a first hard mask pattern 107 to be used as an etching barrier is formed on the first conductive layer 105. The first conductive layer 105 may be formed of polysilicon, and the first hard mask pattern 107 may be formed of a nitride layer. Next, a trench for etching the first conductive layer 105, the gate insulating layer 103, and the semiconductor substrate 100 using the first hard mask pattern 107 as an etching barrier to partition the active region in the semiconductor substrate 100. 108 is formed, and an isolation layer 109 is formed in the trench 108. The width and spacing of the trench 108 are not the same in all regions of the semiconductor substrate, but are larger in the peripheral region than in the cell array region. That is, the trench 108 in the cell array region is denser than in the peripheral region. In addition, the device isolation layer 109 may have a structure in which a plurality of insulating layers are stacked in order to improve gap-fill characteristics of the trench 108 having an increased aspect ratio according to high integration of semiconductor devices. For example, the device isolation layer 109 is deposited on the bottom of the trench 108 to be thicker than the sidewalls of the trench 108 to lower the aspect ratio of the trench 108. The second insulating layer 109b and the third insulating layer 109c may fill the remaining portion of the trench 108. The first insulating layer 109a may be formed of an HDP (High Density Plasma) oxide layer, and may include a surface of the trench 108 and sidewalls of each of the hard mask pattern 107, the first conductive layer 105, and the gate insulating layer 103. It is formed along the "U" shape. The second insulating layer 109b may be formed of a polysilizane (PSZ) film, and fills the trench 108 without voids at a height lower than that of the semiconductor substrate 100. Since the aspect ratio of the trench 108 opened after the formation of the first and second insulating layers 109a and 109b is significantly lower than before the formation of the first and second insulating layers 109a and 109b, the third insulating layer 109c is used in a subsequent process. The trench 108 may be buried to improve the gap-fill characteristics of the trench 108. The third insulating film 109c may be formed of an oxide film, and may include a space between the trench 108 and the gate insulating film 103, a space between the first conductive film 105, and a first hard mask pattern 107. Form to fill all of the space.

Referring to FIG. 1B, the first hard mask pattern 107 described above with reference to FIG. 1A is removed. Removal of the first hard mask pattern 107 may be performed using wet etching. The first insulating layer 109a formed of the HDP oxide layer may be etched under the influence of the wet etching process because the etching rate of the etchant used in the wet etching process is high. In particular, since the first insulating layer 109a formed on the sidewalls of the trench 108 in the peripheral region is thicker than the first insulating layer 109a formed on the sidewalls of the trench 108 in the cell array region, the degree of etching is large. Accordingly, the first insulating layer 109a in the peripheral region is excessively etched under the influence of the wet etching process, so that a groove (eg, a moat) 111 is formed on the sidewall of the device isolation layer 109 in the peripheral region. . In addition, the upper portion of the isolation layer 109 is etched due to the wet etching process, so that the height of the isolation layer 109 is lower than that of the first conductive layer 105.

Referring to FIG. 1C, a compensation layer 113 is formed along the surface of the device isolation layer 109 and the surface of the first conductive layer 105. The compensation layer 113 should be formed to a thickness sufficient to fill the groove 111. For example, the compensation film 113 may be formed to have a thickness of 300 GPa. In addition, the compensation layer 113 may be formed of an oxide layer including LP-TEOS (Low Pressure-Tetra Ethyl Ortho Silicate).

Referring to FIG. 1D, a second hard mask pattern 115 is formed on the compensation layer 113 in the peripheral area.

Referring to FIG. 1E, the second hard mask pattern 115 is used as an etching barrier to remove the compensation layer 113 in the cell array region and to lower the height of the device isolation layer 109 in the cell array region to reduce the effective field height. ). Accordingly, the height of the device isolation layer 109 in the cell array region is lower than that of the device isolation layer 109 in the peripheral region. In this case, the etching rate of the device isolation layer 109 and the compensation layer 113 is preferably 1: 1, and it is preferable to use an etching gas having a high etching selectivity with respect to the first conductive layer 105. In other words, it is preferable to use an etching gas for etching the device isolation layer 109 and the compensation layer 113 faster than the first conductive layer 105. To this end, it is preferable to use a low bias power of 300W to 800W during the etching process.

Referring to FIG. 1F, the second hard mask pattern 115 illustrated in FIG. 1E is removed, and the compensation layer 113 is etched to expose the first conductive layer 105 in the peripheral region. At this time, the compensation layer 113 filling the groove 111 remains without being removed. Thereafter, a cleaning process for removing contaminants remaining on the surfaces of the exposed first conductive film 105 and the device isolation film 109 is performed. In this case, the compensation layer 113 filling the groove 111 prevents the cleaning solution from penetrating into the first insulating layer 109a in the peripheral region, thereby preventing excessive etching of the first insulating layer 109. Accordingly, since the depth of the groove 111 may not be further deepened, the phenomenon in which the semiconductor substrate 100 is exposed through the groove 111 may be prevented.

As described above, in the present invention, since the groove 111 is filled using the compensation layer 113, the phenomenon in which the first insulating layer 109 is excessively etched through the groove 111 during the cleaning process may be prevented. Accordingly, the present invention can prevent the phenomenon in which the groove 111 is deepened and the semiconductor substrate 100 is exposed. As a result, after the dielectric film is formed in a subsequent process, the control film is prevented from being connected to the semiconductor substrate 100 in the peripheral area in the process of removing the dielectric film in the peripheral area and forming the second conductive film for the control gate. . Furthermore, in the present invention, even when the groove 111 is formed on the sidewall of the device isolation layer 109 in the cell array region, the second conductive layer for the control gate may be filled in the semiconductor substrate 100. It is possible to prevent the phenomenon connected to the. The semiconductor device formed through the series of processes described above includes a device isolation layer 109 having grooves 111 formed on sidewalls and a compensation layer 113 filling the grooves 111.

1A to 1F, the device isolation film of the flash device has been described as an example. However, the present invention is not limited to the flash device but may be applied to any semiconductor device in which grooves are formed on the sidewalls of the device isolation film during the manufacturing process of the semiconductor device. have.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1A to 1F are cross-sectional views illustrating a method of forming a device isolation film of a semiconductor device according to the present invention.

<Explanation of symbols for the main parts of the drawings>

100 semiconductor substrate 103 gate insulating film

105: first conductive film 107: first hard mask pattern

109: device isolation film 109a: first insulating film

109b: second insulating film 109c: third insulating film

111: groove 113: compensation film

115: second hard mask pattern

Claims (13)

A device isolation layer which fills the trench formed in the semiconductor substrate and is formed higher than the surface of the semiconductor substrate and includes a groove on the sidewall; A gate insulating film and a conductive film stacked on the semiconductor substrate with the device isolation layer therebetween; And And a compensation layer filling the groove. The method of claim 1, The device separator is A first insulating layer formed along the sidewalls of the trench and the sidewalls of the gate insulating layer while filling the bottom surface of the trench and including the groove portion; A second insulating film formed on the first insulating film and filling the trench with a height lower than that of the semiconductor substrate; And And a third insulating film formed on the second insulating film and formed higher than a surface of the gate insulating film. The method of claim 2, The first insulating film includes a high density plasma (HDP) oxide film. The method of claim 2, The second insulating film includes a polysilizane (PSZ) film. The method of claim 1, The compensation film comprises a semiconductor device. Providing a semiconductor substrate in which trenches are formed in device isolation regions, and a gate insulating film, a conductive film, and a hard mask pattern are stacked on active regions spaced apart from the trench; Forming an isolation layer in the trench higher than the surface of the semiconductor substrate; Removing the hard mask pattern; And Forming a compensation layer filling the groove formed on the sidewall of the device isolation layer while removing the hard mask pattern. The method of claim 6, After forming the compensation film to fill the groove portion, And cleaning the contaminants remaining on the conductive film and the compensation film. A gate insulating film, a conductive film, and a gate insulating film on an active region including a first region having a first trench and a second region having a second trench formed denser than the first trench, and having the first and second trenches interposed therebetween. Providing a semiconductor substrate having a first hard mask pattern stacked thereon; Forming an isolation layer to fill a space between the first and second trenches, the first hard mask layer, the conductive layer, and the gate insulating layer; Removing the first hard mask pattern; And Forming a compensation layer on the device isolation layer and the conductive layer so as to fill the groove formed in the sidewall of the device isolation layer while removing the first hard mask pattern; Forming a second hard mask pattern on the compensation layer formed in the first region; Removing the compensation layer formed in the second region and lowering the height of the device isolation layer formed in the second region; And Removing the second hard mask pattern, and removing the compensation layer on the conductive layer of the first region. The method of claim 8, After removing the compensation film on the conductive film of the first region, And cleaning the contaminants remaining on the conductive film and the compensation film. The method according to any one of claims 6 and 8, The device separator is A first insulating layer formed along the sidewalls of the trench and the sidewalls of the gate insulating layer while filling the bottom surface of the trench and including the groove portion; A second insulating film formed on the first insulating film and filling the trench with a height lower than that of the semiconductor substrate; And And a third insulating film formed on the second insulating film and formed higher than a surface of the gate insulating film. The method according to any one of claims 6 and 8, The first insulating film is a semiconductor device manufacturing method of forming a high density plasma (HDP) oxide film. The method according to any one of claims 6 and 8, The second insulating film is a semiconductor device manufacturing method of forming a polysilizane (PSZ) film. The method according to any one of claims 6 and 8, And the compensation film is formed of an oxide film.

Images