KR20100015073A - Method for manufacturing thin film transistors based on titanium oxides as active layer and thin film transistors thereof - Google Patents

Method for manufacturing thin film transistors based on titanium oxides as active layer and thin film transistors thereof Download PDF

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KR20100015073A
KR20100015073A KR1020080075977A KR20080075977A KR20100015073A KR 20100015073 A KR20100015073 A KR 20100015073A KR 1020080075977 A KR1020080075977 A KR 1020080075977A KR 20080075977 A KR20080075977 A KR 20080075977A KR 20100015073 A KR20100015073 A KR 20100015073A
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vapor deposition
active layer
chemical vapor
thin film
deposition
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KR101482944B1 (en
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박재우
한성원
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한국과학기술원
테크노세미켐 주식회사
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types

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  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Thin Film Transistor (AREA)

Abstract

PURPOSE: A method for manufacturing a thin film transistors based on titanium oxides as an active layer and a thin film transistors thereof is provided to improve charge transfer and the stability of air and moisture by using a titanium oxide as an active layer. CONSTITUTION: An active layer(140) is formed on a substrate(110). An insulating layer(150) is formed on the active layer. The active layer is formed through one among a chemical vapor deposition, an organometallic chemical vapor deposition, an atomic layer deposition, a low pressure chemical vapor deposition, and a plasma enhanced chemical vapor deposition method. The active layer is formed with the organic compound including the titanium.

Description

산화티타늄을 활성층으로 갖는 박막 트랜지스터의 제조 방법 및 이에 의해 제조된 박막 트랜지스터{method for manufacturing thin film transistors based on titanium oxides as active layer and thin film transistors thereof} Method for manufacturing thin film transistors based on titanium oxides as active layer and thin film transistors

본 발명은 박막 트랜지스터(thin film transistor)에 관한 것으로서, 특히, 저비용으로 제조하고, 유해 환경 문제를 해결하며, 성능을 향상 시킬 수 있을 뿐만 아니라 특정 유형의 전자 기기에 널리 적용될 수 있도록 하는 산화티타늄을 활성층으로 갖는 박막 트랜지스터의 제조 방법 및 이에 의해 제조된 박막트랜지스터에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to thin film transistors, and in particular, to produce titanium oxide, which can be manufactured at low cost, solves harmful environmental problems, improves performance, and can be widely applied to certain types of electronic devices. A method of manufacturing a thin film transistor having an active layer and a thin film transistor produced thereby.

휴대성과 양방향 의사소통 등을 고려하여 제품이 가벼울 뿐만 아니라 사용할 때에는 크게 확대되고 사용하지 않을 때에는 저장될 수 있는 다목적 디스플레이 기기들이 각광받고 있다. 특히, 유연성 디스플레이(flexible display)로서, 유기 EL(Electro Luminescence)이나 액정(liquid crystal) 및 전기영동(electrophoretic)에 의한 디스플레이의 개발이 진행되고 있다. 그밖에 AMLCD, AMOLED 및 투명디스플레이등 대형화 디스플레이에도 많은 관심이 집중되고 있다.Considering portability and two-way communication, multi-purpose display devices, which are not only lightweight but also greatly expandable when used and can be stored when not in use, are in the spotlight. In particular, as a flexible display, development of displays by organic EL (Electro Luminescence), liquid crystal (liquid crystal) and electrophoretic (electrophoretic) is in progress. In addition, much attention is being paid to large-sized displays such as AMLCD, AMOLED, and transparent display.

위에 언급된 디스플레이의 구동 장치로서 유기 박막 트랜지스터가 주목을 받고 있다. 유기 박막 트랜지스터에 쓰이고 있는 유기 반도체는 실리콘 반도체에 비하여 기계적인 유연성이 풍부하다. 유기 반도체는 전하이동도가 보통 0.001 ~ 수 cm2/V·sec 이내이고, 전류가 많이 필요치 않는 디스플레이에만 국한되어 사용되고 있다.Organic thin film transistors have attracted attention as a driving device of the above-mentioned display. Organic semiconductors used in organic thin film transistors are more mechanically flexible than silicon semiconductors. Organic semiconductors usually have a charge mobility of less than 0.001 to several cm 2 / V · sec and are limited to displays that do not require much current.

유기 박막 트랜지스터는 제한된 전하이동도 때문에 전류 구동력에 한계를 갖게 된다. 이에, 유기 박막 트랜지스터는 채널의 폭 대 길이 비율을 높여 일정 정도까지는 전류 구동력을 높일 수는 있다. 그러나 이와 같이 할 경우에 단위 디스플레이 픽셀 당 실제 발광부가 차지하는 영역의 비율(개구율)이 낮아지게 된다.Organic thin film transistors have a limited current driving force due to limited charge mobility. Accordingly, the organic thin film transistor may increase the current-to-power ratio up to a certain extent by increasing the width-to-length ratio of the channel. However, in this case, the ratio (opening ratio) of the area occupied by the actual light emitting unit per unit display pixel becomes low.

또한, 유기 반도체는 공기 중의 산소나 수분에 매우 취약하여 완벽한 봉지(packaging) 구현에 어려움이 있다. 유기 반도체는 유연성 기판의 산소 및 수분 투과율이 유리 기판 등에 비해 매우 높기 때문에 이를 사용하는 유연성 디스플레이의 경우 봉지가 더욱 어려워지게 된다.In addition, the organic semiconductor is very vulnerable to oxygen or moisture in the air, it is difficult to implement a perfect packaging (packaging). Since the organic semiconductor has a very high oxygen and moisture permeability of the flexible substrate compared to the glass substrate, the encapsulation becomes more difficult in the case of the flexible display using the organic semiconductor.

한편, 요소 트랜지스터 기술로서 비정질 실리콘이나 저온 폴리 실리콘 기반 트랜지스터들이 있다. 비정질 실리콘 기반 트랜지스터는 낮은 전하이동도와 트랜지스터 문턱 전압의 시변 특성이 좋지 못한 단점이 있다. 저온 폴리 실리콘 기반 트랜지스터는 높은 처리 온도로 인해 플라스틱 기판 등과는 사용될 수 없는 단점과 대형화에 제한성 있다는 단점이 있다.Meanwhile, as the element transistor technology, there are amorphous silicon or low temperature polysilicon based transistors. Amorphous silicon-based transistors have the disadvantage of low charge mobility and poor time-varying characteristics of transistor threshold voltages. Low-temperature polysilicon-based transistors have disadvantages that cannot be used with plastic substrates due to high processing temperatures and have limitations in their size.

이러한 문제점들을 극복하기 위해 금속 산화물 반도체 특히, 산화아연(ZnO) 계 기반 트랜지스터들이 제시되고 있다. 그러나 금속 산화물 반도체 기반 트랜지스터들은 높은 전하 이동도를 갖도록 하기 위하여 가격이 높은 인듐(In), 주석(Sn), 갈륨(Ga) 등이 첨가된 경우가 많다.In order to overcome these problems, metal oxide semiconductors, particularly zinc oxide (ZnO) based transistors, have been proposed. However, metal oxide semiconductor-based transistors are often added with indium (In), tin (Sn), gallium (Ga), etc., in order to have high charge mobility.

이와 같은 MOxTFT(metal-oxide thin-film transistors)는 액티브 매트릭스 디스플레이 및 RFID(Radio Frequency Identification) 태그와 같은 응용분야에서, 비용, 성능, 및 공정 난이도의 이상적 균형을 이룰 수 있어, Si 및 유기(organic) 기반 TFT에 대한 대안으로 최근 대단한 관심을 받고 있다. 또한, MOxTFT는 투명성(Transparency)을 활용하는 새로운 어플리케이션에서 적용 될 수 있을 것으로 기대되고 있다.These metal-oxide thin-film transistors (MOxTFTs) are ideally balanced for cost, performance, and process difficulty in applications such as active matrix displays and Radio Frequency Identification (RFID) tags. As an alternative to the TFT-based TFT, it is receiving great attention recently. In addition, MOxTFT is expected to be applied in new applications that utilize transparency.

그러나 앞서 말한 바와 같이, 지금까지 거의 모든 MOxTFT는 ZnO 또는 그 혼성물을 기반으로 제작되어 왔다. 게다가, 대부분의 성공적인 MOxTFT는 인듐(indium)을 혼합하기 때문에, 재료 및 공정 비용이 매우 높아지는 문제점과 성막방식이 주로 스퍼터링방식으로 이루어짐에따라 연속적인 성막시 성막된 박막의 조성이 달라져 결국 전기적 특성이 변화하는 안정성(Stability) 문제점을 가지고 있다. 이 경우 RFID 태그와 같이 초저가를 지향하는 분야 및 특히 양산시 제품의 재현성에 큰 문제로 제기 될 것이다.As mentioned above, however, almost all MOxTFTs have been made based on ZnO or its hybrids. In addition, since most successful MOxTFTs mix indium, the material and process cost are very high, and the film formation method is mainly made of sputtering method, and thus the composition of the deposited film is changed during continuous film formation. There is a changing stability problem. In this case, it will be a big problem in the field of ultra low cost such as RFID tag, and especially in the reproducibility of products during mass production.

이에, 성능이 우수하면서도 가격 요건이 좋은 박막 트랜지스터를 구현하기 위한 새로운 기반 물질을 발굴하고 그에 맞는 제조 방법들 및 구조들을 제시하기 위한 노력들이 계속되어야 할 것이다.Therefore, efforts should be made to discover new base materials and propose manufacturing methods and structures for implementing thin film transistors having high performance and good price requirements.

본 발명의 목적은 상기와 같은 문제점을 해결하기 위하여 창안된 것으로서, 지구상에 존재하는 풍부한 산화티타늄을 사용하고, 특히 박막 상으로 제조가 극히 용이한 다결정 내지 비정질(amorphous)의 산화티타늄을 박막 트랜지스터의 활성층으로 형성함으로써, 저비용으로 박막 트랜지스터를 제조할 수 있도록 하는 산화티타늄을 활성층으로 갖는 박막 트랜지스터의 제조 방법 및 이에 의해 제조된 박막트랜지스터를 제공하는데 있다.An object of the present invention is to solve the above problems, using abundant titanium oxide existing on the earth, in particular polycrystalline to amorphous (titanium) of titanium oxide, which is extremely easy to manufacture into a thin film of a thin film transistor The present invention provides a method for manufacturing a thin film transistor having titanium oxide as an active layer, which enables a thin film transistor to be manufactured at low cost, and a thin film transistor manufactured thereby.

본 발명의 다른 목적은 친환경물질인 산화티타늄을 박막 트랜지스터의 활성층으로 형성함으로써, 기존의 박막 트랜지스터들이 가지고 있는 유해 환경 문제를 해결할 수 있도록 하는 산화티타늄을 활성층으로 갖는 산화티타늄을 활성층으로 갖는 박막 트랜지스터의 제조 방법 및 이에 의해 제조된 박막트랜지스터를 제공하는데 있다.Another object of the present invention is to form a titanium oxide, an environmentally friendly material, as an active layer of a thin film transistor, thereby solving the harmful environmental problems of conventional thin film transistors. A manufacturing method and a thin film transistor manufactured thereby are provided.

본 발명의 또 다른 목적은 산화티타늄을 박막 트랜지스터의 활성층으로 형성함으로써, 높은 전하 이동도 및 공기나 수분에 대한 안정성 등을 포함하는 박막 트랜지스터의 성능을 향상 시킬 수 있도록 하는 산화티타늄을 활성층으로 갖는 박막 트랜지스터의 제조 방법 및 이에 의해 제조된 박막트랜지스터를 제공하는데 있다.Still another object of the present invention is to form titanium oxide as an active layer of a thin film transistor, whereby a thin film having titanium oxide as an active layer to improve the performance of a thin film transistor including high charge mobility and stability against air or moisture, etc. A method of manufacturing a transistor and a thin film transistor manufactured thereby are provided.

본 발명의 또 다른 목적은 투명성을 갖는 산화티타늄을 박막 트랜지스터의 활성층으로 형성함으로써, 전자소자가 보이지 않도록 해야 하는 특수 용도의 전자 기기에 널리 적용될 수 있도록 하는 산화티타늄을 활성층으로 갖는 박막 트랜지스 터의 제조 방법 및 이에 의해 제조된 박막트랜지스터를 제공하는데 있다.It is still another object of the present invention to form a thin film transistor having titanium oxide as an active layer, which can be widely applied to a special purpose electronic device where an electronic device should not be visible by forming a transparent titanium oxide as an active layer of a thin film transistor. A manufacturing method and a thin film transistor manufactured thereby are provided.

본 발명의 또 다른 목적은 대면적의 디스플레이에 사용될 대면적의 박막트랜지스터를 대량 생산할 수 있고, 제조 공정이 저렴하여 제품의 양산성이 좋은 산화티타늄을 활성층으로 갖는 박막 트랜지스터의 제조 방법 및 이에 의해 제조된 박막트랜지스터를 제공하는데 있다.It is still another object of the present invention to manufacture a thin film transistor having a large area of a large area thin film transistor to be used in a large area display, and having a low production process and having good mass productivity of the product as an active layer. To provide a thin film transistor.

본 발명의 또 다른 목적은 저온에서도 생산할 수 있어, 유리전이온도가 낮은 플라스틱 필름 등을 기판으로 사용하여 박막트랜지스터를 제조 할 수 있는 산화티타늄을 활성층으로 갖는 박막 트랜지스터의 제조 방법 및 이에 의해 제조된 박막트랜지스터를 제공하는데 있다.Another object of the present invention can be produced at a low temperature, a method of manufacturing a thin film transistor having a titanium oxide active layer capable of producing a thin film transistor using a plastic film having a low glass transition temperature, etc. as a substrate and the thin film produced thereby To provide a transistor.

상기 목적을 달성하기 위하여, 본 발명의 일례에 따른 산화티타늄을 활성층으로 갖는 박막 트랜지스터의 제조 방법은 기판을 준비하는 단계; 상기 기판 상에 활성층을 형성하는 단계; 및 상기 활성층 상에 절연막을 형성하는 단계를 포함하고, 상기 활성층을 형성하는 단계는 전구체로서 티타늄(Ti)을 포함한 유기화합물을 화학기상증착법(CVD ; Chemical Vapor Deposition), 유기금속 화학기상증착법(MOCVD ; Metal Organic Chemical Vapor Deposition), 원자층증착법(ALD : Atomic Layer Deposition), 저기압화학기상증착법(LPCVD ; Low Pressure Chemical Vapor Deposition) 및 플라즈마 화학기상증착법(PECVD ; Plasma Enhanced Vapor Deposition) 중에서 선택된 1종의 방법으로 증착하는 것으로 한다. 또, 본 발명의 일례에 따른 산화티타늄을 활성층으로 갖는 박막 트랜지스터의 제조 방법은 상기 기판 상에 소스 전극과 드레인 전극을 형성하는 단계; 및 상기 절연막 상에 게이트 전극을 형성되는 단계를 더 포함하고, 상기 소스 전극과 상기 드레인 전극은 상기 활성층으로 덮여있을 수 있다. 또, 본 발명의 일례에 따른 산화티타늄을 활성층으로 갖는 박막 트랜지스터의 제조 방법은 상기 활성층 상에 소스 전극과 드레인 전극을 형성하는 단계; 및 상기 절연막 상에 게이트 전극을 형성하는 단계를 더 포함하고, 상기 소스 전극과 상기 드레인 전극은 상기 절연막으로 덮여있을 수 있다.In order to achieve the above object, a method of manufacturing a thin film transistor having a titanium oxide active layer according to an example of the present invention comprises the steps of preparing a substrate; Forming an active layer on the substrate; And forming an insulating layer on the active layer, wherein the forming of the active layer includes chemical vapor deposition (CVD) and organic metal chemical vapor deposition (MOCVD) of an organic compound including titanium (Ti) as a precursor. ; Metal Organic Chemical Vapor Deposition), Atomic Layer Deposition (ALD), Low Pressure Chemical Vapor Deposition (LPCVD) and Plasma Enhanced Vapor Deposition (PECVD) It is supposed to deposit by the method. In addition, a method of manufacturing a thin film transistor having titanium oxide as an active layer according to an example of the present invention includes forming a source electrode and a drain electrode on the substrate; And forming a gate electrode on the insulating layer, wherein the source electrode and the drain electrode may be covered with the active layer. In addition, a method of manufacturing a thin film transistor having titanium oxide as an active layer according to an example of the present invention includes forming a source electrode and a drain electrode on the active layer; And forming a gate electrode on the insulating film, wherein the source electrode and the drain electrode may be covered with the insulating film.

상기 목적을 달성하기 위하여, 본 발명의 또 다른 일례에 따른 산화티타늄을 활성층으로 갖는 박막 트랜지스터의 제조 방법은 기판을 준비하는 단계; 상기 기판 상에 절연막을 형성하는 단계; 및 상기 절연막 상에 활성층을 형성하는 단계를 포함하고, 상기 활성층을 형성하는 단계는 전구체로서 티타늄(Ti)을 포함한 유기화합물을 화학기상증착법(CVD ; Chemical Vapor Deposition), 유기금속 화학기상증착법(MOCVD ; Metal Organic Chemical Vapor Deposition), 원자층증착법(ALD : Atomic Layer Deposition), 저기압화학기상증착법(LPCVD ; Low Pressure Chemical Vapor Deposition) 및 플라즈마 화학기상증착법(PECVD ; Plasma Enhanced Vapor Deposition) 중에서 선택된 1종의 방법으로 증착하는 것을 특징으로 한다. 또, 본 발명의 일례에 따른 산화티타늄을 활성층으로 갖는 박막 트랜지스터의 제조 방법은 상기 기판 상에 게이트 전극을 형성하는 단계; 및 상기 활성층 상에 소스 전극과 드레인 전극을 형성하는 단계를 더 포함하고, 상기 게이트 전극은 상기 절연막으로 덮여있을 수 있다. 또, 본 발명의 일례에 따른 산화티타늄을 활성층으로 갖는 박막 트랜지스터의 제조 방법은 상기 기판 상에 게이트 전극을 형성하는 단계; 및 상기 활성층 상에 소스 전극과 드레인 전극을 형성하는 단계를 더 포함하고, 상기 게이트 전극은 상기 절연막으로 덮여있을 수 있다. In order to achieve the above object, a method of manufacturing a thin film transistor having a titanium oxide as an active layer according to another embodiment of the present invention comprises the steps of preparing a substrate; Forming an insulating film on the substrate; And forming an active layer on the insulating layer, and the forming of the active layer includes chemical vapor deposition (CVD) and organic metal chemical vapor deposition (MOCVD) of an organic compound including titanium (Ti) as a precursor. ; Metal Organic Chemical Vapor Deposition (ALD), Atomic Layer Deposition (ALD), Low Pressure Chemical Vapor Deposition (LPCVD) and Plasma Enhanced Vapor Deposition (PECVD) It is characterized by depositing in a method. Further, a method of manufacturing a thin film transistor having titanium oxide as an active layer according to an example of the present invention includes forming a gate electrode on the substrate; And forming a source electrode and a drain electrode on the active layer, wherein the gate electrode may be covered with the insulating layer. Further, a method of manufacturing a thin film transistor having titanium oxide as an active layer according to an example of the present invention includes forming a gate electrode on the substrate; And forming a source electrode and a drain electrode on the active layer, wherein the gate electrode may be covered with the insulating layer.

따라서, 본 발명은 전구체로서 티타늄(Ti)을 포함한 유기화합물을 화학기상증착법(CVD ; Chemical Vapor Deposition), 유기금속 화학기상증착법(MOCVD ; Metal Organic Chemical Vapor Deposition), 원자층증착법(ALD : Atomic Layer Deposition), 저기압화학기상증착법(LPCVD ; Low Pressure Chemical Vapor Deposition) 및 플라즈마 화학기상증착법(PECVD ; Plasma Enhanced Vapor Deposition) 중에서 선택된 1종의 방법으로 증착하는 것으로 박막트랜지스터의 활성층을 형성함으로서, 대면적의 박막트랜지스터를 제조할 수 있으며, 대량 생산이 가능하여 양산성을 좋게 할 수 있는 것이다.Accordingly, the present invention provides an organic compound including titanium (Ti) as a precursor, chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD). Deposition), Low Pressure Chemical Vapor Deposition (LPCVD) and Plasma Enhanced Vapor Deposition (PECVD) are used to form the active layer of the thin film transistor. Thin film transistors can be manufactured, and mass production is possible, so that mass production can be improved.

산화티타늄(TiOx)은 매우 낮은 비용으로 대량 생산될 수 있고 색소(pigments), 자외선 흡수제(UV-absorbers), 광촉매(photocatalyst), 광학 코팅(optical coatings), 가스 센서(gas sensors)와 같이 다양한 분야에서 중요하게 응용되고 있는 재료이다. 이는 또한 TFT를 위한 고(高) 유전상수(high-k) 절연체나, 염료 감응 및 유기 태양 전지의 전자 수송층으로서, 전자 분야에 있어서도 연 구되고 있다.Titanium oxide (TiO x ) can be mass produced at a very low cost and can be used in a variety of applications such as pigments, UV-absorbers, photocatalysts, optical coatings, and gas sensors. It is an important material in the field. It has also been studied in the electronics field as a high-k insulator for TFTs, or as an electron transport layer for dye-sensitized and organic solar cells.

그러나 산화티타늄(TiOx)를 활성 채널 재료로 사용하여 실제 적용 가능한 TFT 소자를 구현한 예는 그간 보고 된 바 없다. 본 발명자는 산화티타늄(TiOx)이 에너지 갭, 전도(conduction) 밴드 및 가전자(valence) 밴드의 위치 등 전자의 에너지 밴드 양상이 가장 흔히 쓰이는 ZnO와 유사하면서, 높은 홀(Hall) 전하이동도(high Hall mobility)를 보일 뿐 아니라, 저비용으로 대량생산이 가능하고 상기한 대로 다양한 응용분야에 적용될 수 있는 점에 착안, 산화티타늄을 TFT 채널의 활성층에 적용한 소자가 구현되었을 경우에 기대할 수 있는 높은 기술적 및 경제적 가능성에 주목하여 본 발명에 이르게 되었다.However, there have been no reported examples of practically applicable TFT devices using titanium oxide (TiO x ) as an active channel material. The inventors found that titanium oxide (TiO x ) is similar to ZnO, where the energy band pattern of electrons is most commonly used, such as the location of energy gaps, conduction bands and valence bands, and high Hall charge mobility. Not only does it show high hall mobility, but it can be mass-produced at low cost and can be applied to various applications as described above. Therefore, it can be expected that a device in which titanium oxide is applied to an active layer of a TFT channel is realized. Attention has been paid to the technical and economic possibilities.

산화티타늄(TiOx) 박막(thin film) 또는 단결정(single crystal)을 사용하는 효과적인 트랜지스터를 구현하는 데 있어서 직면하게 되는 실제적인 어려움은 TiO2의 고 저항율과 높은 트랩 밀도(trap density)에 의하여 비롯되는 것으로 볼 수 있다. 특히 트랩이 많은 경우, 게이트 전압에 의해 유기된 캐리어(gate bias-induced carrier)들의 상당수가 효과적으로 자유 캐리어(free carrier)들로 되지 못하기 때문에, 채널층에서 비충진 트랩의 밀도(unfilled trap density)들을 줄이는 것은 매우 중요할 수 있다. 저항율과 비충진 트랩 밀도(unfilled trap density)는 모두 전하 캐리어(charge carrier)의 외부 도핑에 의해 감소될 수 있다.The real challenges faced in implementing effective transistors using TiO x thin films or single crystals are due to the high resistivity and high trap density of TiO 2 . It can be seen as. Especially in the case of a large number of traps, the unfilled trap density in the channel layer, since many of the gate bias-induced carriers are not effectively free carriers. Can be very important. Both resistivity and unfilled trap density can be reduced by external doping of charge carriers.

산화티타늄(TiOx)의 경우, 산소 공핍(oxygen vacancy), 격자간 티타늄(Ti-interstitials) 및 도펀트(dopants) 같은 인자들을 통해, 절연체 범위의 저항율(1012Ωcm) 로부터 도체 범위의 저항율(0.001~1Ωcm)까지 매우 넓은 범위에서 저항율을 조절할 수 있다. 저항율이 지나치게 높거나 전도도가 지나치게 높은 막들은 TFT 활성 채널에 바람직하지 않기 때문에, 실제 응용 가능한 TFT의 구현에 성공하기 위한 열쇠는, 공정의 복잡성을 추가하지 않으면서 쉬운 방법으로 트랩 밀도를 줄이는 것이 중요하다. In the case of titanium oxide (TiO x ), the resistivity of the insulator range (10 12 Ωcm) to the conductor range resistivity (0.001), through factors such as oxygen vacancy, titanium-interstitials and dopants. Resistivity can be adjusted over a very wide range from ~ 1Ωcm). Films with too high resistivity or too high conductivity are undesirable for TFT active channels, so the key to success in the practical implementation of TFTs is to reduce the trap density in an easy way without adding process complexity. Do.

이와 같이, 본 발명에 따른 활성층은 전구체로서 티타늄(Ti)을 포함한 유기화합물을 화학기상증착법(CVD ; Chemical Vapor Deposition), 유기금속 화학기상증착법(MOCVD ; Metal Organic Chemical Vapor Deposition), 원자층증착법(ALD : Atomic Layer Deposition), 저기압화학기상증착법(LPCVD ; Low Pressure Chemical Vapor Deposition) 및 플라즈마 화학기상증착법(PECVD ; Plasma Enhanced Vapor Deposition) 중에서 선택된 1종의 방법으로 증착하는 것으로 산화티타늄층을 형성함으로서 박막트랜지스터의 활성층으로서 이용이 가능한 적정의 트랩밀도를 구현할 수 있었다. As described above, the active layer according to the present invention is an organic compound including titanium (Ti) as a precursor, chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition ( ALD: Atomic Layer Deposition (LPD), Low Pressure Chemical Vapor Deposition (LPCVD) and Plasma Enhanced Vapor Deposition (PECVD) are deposited by one method. An appropriate trap density that can be used as the active layer of the transistor was realized.

또, 본 발명의 일례에 따른 산화티타늄을 활성층으로 갖는 박막트랜지스터의 제조 방법은 전구체로서 티타늄(Ti)을 포함한 유기화합물을 화학기상증착법(CVD ; Chemical Vapor Deposition), 유기금속 화학기상증착법(MOCVD ; Metal Organic Chemical Vapor Deposition), 원자층증착법(ALD : Atomic Layer Deposition), 저기압화학기상증착법(LPCVD ; Low Pressure Chemical Vapor Deposition) 및 플라즈마 화학기상증착법(PECVD ; Plasma Enhanced Vapor Deposition) 중에서 선택된 1종의 방법으로 증착할 때, 400℃이하의 온도에서 증착할 수 있으며, 300℃이하의 온도에서 증착하는 것이 바람직하다. 따라서, 본 발명은 400℃이하, 바람직하게는 300℃이하의 온도에서도 박막트랜지스터의 제조가 가능하여, 400℃를 초과하는 고온에서 내열성과 치수안정성 등을 가지는 고가의 유리 기판이 아닌 저가의 유리기판을 사용할 수 있으며, 약 300℃이하의 유리전이온도를 가지는 폴리이미드 필름 등의 플라스틱 필름을 기판으로 사용할 수 있다.In addition, a method of manufacturing a thin film transistor having titanium oxide as an active layer according to an embodiment of the present invention includes chemical vapor deposition (CVD) and organic metal chemical vapor deposition (MOCVD) of an organic compound containing titanium (Ti) as a precursor. One method selected from Metal Organic Chemical Vapor Deposition (ALD), Atomic Layer Deposition (ALD), Low Pressure Chemical Vapor Deposition (LPCVD) and Plasma Enhanced Vapor Deposition (PECVD) When depositing with, can be deposited at a temperature of 400 ℃ or less, it is preferable to deposit at a temperature of 300 ℃ or less. Therefore, the present invention is capable of manufacturing a thin film transistor at a temperature of 400 ° C. or less, preferably 300 ° C. or less, so that a low-cost glass substrate is not an expensive glass substrate having heat resistance and dimensional stability at a high temperature exceeding 400 ° C. May be used, and a plastic film such as a polyimide film having a glass transition temperature of about 300 ° C. or less may be used as the substrate.

또, 본 발명의 일례에 따른 산화티타늄을 활성층으로 갖는 박막트랜지스터의 제조 방법은 전구체로서 티타늄(Ti)을 포함한 유기화합물을 화학기상증착법(CVD ; Chemical Vapor Deposition), 유기금속 화학기상증착법(MOCVD ; Metal Organic Chemical Vapor Deposition), 원자층증착법(ALD : Atomic Layer Deposition), 저기압화학기상증착법(LPCVD ; Low Pressure Chemical Vapor Deposition) 및 플라즈마 화학기상증착법(PECVD ; Plasma Enhanced Vapor Deposition) 중에서 선택된 1종의 방법으로 증착할 때, 산소(O2), 오존(O3) 및 수증기(H2O) 중 선택된 1종 이상의 음이온 소스(Anion Source) 분위기에서 증착할 수 있다. 이 때, 음이온 소스 분위기를 수증기(H2O)로 하는 경우에는 수증기(H2O)가 10 ~ 80℃의 온도로 제공됨으로서 티타늄을 포함하는 유기화합물과의 반응을 더욱 활발하게 할 수 있다. In addition, a method of manufacturing a thin film transistor having titanium oxide as an active layer according to an embodiment of the present invention includes chemical vapor deposition (CVD) and organic metal chemical vapor deposition (MOCVD) of an organic compound containing titanium (Ti) as a precursor. One method selected from Metal Organic Chemical Vapor Deposition (ALD), Atomic Layer Deposition (ALD), Low Pressure Chemical Vapor Deposition (LPCVD) and Plasma Enhanced Vapor Deposition (PECVD) When the deposition is carried out, the deposition may be performed in an atmosphere of at least one anion source selected from oxygen (O 2 ), ozone (O 3 ), and water vapor (H 2 O). At this time, when the anion source atmosphere is water vapor (H 2 O), water vapor (H 2 O) is provided at a temperature of 10 ~ 80 ℃ it can be more active to react with the organic compound containing titanium.

따라서, 본 발명은 유기금속 화학기상증착법에 의한 증착 단계에서 전구체로부터의 티타늄(Ti)이 박막트랜지스터의 활성층으로서 효율이 높은 산화티타늄 활성층을 형성할 수 있다. Accordingly, in the present invention, titanium (Ti) from the precursor may form a highly efficient titanium oxide active layer as the active layer of the thin film transistor in the deposition step by the organometallic chemical vapor deposition method.

또, 본 발명의 일례에 따른 산화티타늄을 활성층으로 갖는 박막트랜지스터의 제조 방법은 전구체로서 티타늄(Ti)을 포함한 유기화합물을 화학기상증착법(CVD ; Chemical Vapor Deposition), 유기금속 화학기상증착법(MOCVD ; Metal Organic Chemical Vapor Deposition), 원자층증착법(ALD : Atomic Layer Deposition), 저기압화학기상증착법(LPCVD ; Low Pressure Chemical Vapor Deposition) 및 플라즈마 화학기상증착법(PECVD ; Plasma Enhanced Vapor Deposition) 중에서 선택된 1종의 방법으로 증착할 때, 5초에서 50 분 동안 증착할 수 있다. 그리고, 활성층의 두께 형성속도가 1Å/min ~ 1㎛/min으로 증착하는 것이 바람직하다. 따라서, 본 발명은 화학기상증착법(CVD ; Chemical Vapor Deposition), 유기금속 화학기상증착법(MOCVD ; Metal Organic Chemical Vapor Deposition), 원자층증착법(ALD : Atomic Layer Deposition), 저기압화학기상증착법(LPCVD ; Low Pressure Chemical Vapor Deposition) 및 플라즈마 화학기상증착법(PECVD ; Plasma Enhanced Vapor Deposition) 중에서 선택된 1종의 방법에 의한 증착 단계에서 전구체로부터의 티타늄(Ti)이 박막트랜지스터의 활성층으로서의 충분한 밀도와 두께를 가져 효율이 높은 산화티타늄 활성층을 형성할 수 있다.In addition, a method of manufacturing a thin film transistor having titanium oxide as an active layer according to an embodiment of the present invention includes chemical vapor deposition (CVD) and organic metal chemical vapor deposition (MOCVD) of an organic compound containing titanium (Ti) as a precursor. One method selected from Metal Organic Chemical Vapor Deposition (ALD), Atomic Layer Deposition (ALD), Low Pressure Chemical Vapor Deposition (LPCVD) and Plasma Enhanced Vapor Deposition (PECVD) When deposited with, it can be deposited for 5 seconds to 50 minutes. In addition, it is preferable that the thickness formation rate of the active layer is deposited at 1 mW / min to 1 m / min. Therefore, the present invention provides a chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD; Low) In the deposition step by one method selected from Pressure Chemical Vapor Deposition (PECVD) and Plasma Enhanced Vapor Deposition (PECVD), titanium (Ti) from the precursor has a sufficient density and thickness as an active layer of the thin film transistor, resulting in high efficiency. It is possible to form a high titanium oxide active layer.

또, 본 발명의 일례에 따른 산화티타늄을 활성층으로 갖는 박막트랜지스터의 제조 방법은 전구체로서 티타늄(Ti) 유기화합물이 티타늄 테트라 알콕사이드(Titaniun tetra alkoxide ; Ti(OR)4, R은 알킬기), 티타늄 테트라 클로라이드(Titaniun tetra chloride ; TiCl4) 및 티타늄 테트라 다이알킬아민(Titanium tetra diaklyamine ; Ti(NR2)4, R은 알킬기) 중 선택된 1종 이상인 것일 수 있다. 또, 전구체로서 티타늄(Ti) 유기화합물은 티타늄 테트라 이소프로폭사이드(TTIP ; Titanium Tetra IsoPropoxide)인 것이 바람직하다. 또, 전구체로서 티타늄(Ti)을 포함한 유기화합물은 10 ~ 200℃의 온도로 제공됨으로서, 음이온 소스와의 반응을 더욱 활발하게 할 수 있다. In addition, according to an embodiment of the present invention, a method of manufacturing a thin film transistor having titanium oxide as an active layer includes a titanium (Ti) organic compound as a precursor, titanium tetraalkoxide (Ti (OR) 4 , R is an alkyl group), and titanium tetra It may be one or more selected from chloride (Titaniun tetra chloride; TiCl 4 ) and titanium tetra diaklyamine (Ti (NR 2 ) 4 , R is an alkyl group). In addition, as a precursor, the titanium (Ti) organic compound is preferably titanium tetra isopropoxide (TTIP). In addition, the organic compound including titanium (Ti) as a precursor is provided at a temperature of 10 ~ 200 ℃, it is possible to more actively react with the anion source.

특히, 본 발명은 유기금속 화학기상증착법에 의한 증착 단계에서 산소(O2), 오존(O3) 및 수증기(H2O) 중에서 선택된 1종의 분위기에서 보다 저온에서 산소와 반응을 잘 할 수 있는 전구체로서의 티타늄 유기화합물을 선택하여 사용할 수 있으며, 이에 따라 400℃이하, 보다 바람직하게는 300℃이하의 저온에서도 박막트랜지스터의 활성층으로서의 효율이 높은 산화티타늄 활성층을 포함하는 박막트랜지스터를 제조할 수 있다. In particular, the present invention can react well with oxygen at a lower temperature in one atmosphere selected from oxygen (O 2 ), ozone (O 3 ) and water vapor (H 2 O) in the deposition step by the organometallic chemical vapor deposition method. Titanium organic compounds can be selected and used as precursors, and accordingly, a thin film transistor including a titanium oxide active layer having high efficiency as an active layer of a thin film transistor can be manufactured even at a low temperature of 400 ° C or less, more preferably 300 ° C or less. .

상기 목적을 달성하기 위하여, 본 발명의 일례에 따른 산화티타늄을 활성층 으로 갖는 박막 트랜지스터는 상술한 제조 방법에 의하여 제조된 산화티타늄을 활성층으로 갖는 박막트랜지스터인 것이 특징이며, 산화티타늄 활성의 두께는 1Å ~ 1㎛인 것이 바람직하다. 즉, 1Å ~ 1㎛의 두께로 산화티타늄 활성층이 형성됨으로서, 박막트랜지스터의 활성층으로서 더욱 효율이 좋은 기능을 발휘 할 수 있는 것이다.In order to achieve the above object, the thin film transistor having titanium oxide as an active layer according to an example of the present invention is characterized in that the thin film transistor having titanium oxide prepared by the above-described manufacturing method as an active layer, the thickness of the titanium oxide active is 1Å It is preferable that it is-1 micrometer. That is, the titanium oxide active layer is formed to a thickness of 1 ~ 1㎛, it is possible to exhibit a more efficient function as the active layer of the thin film transistor.

이를 통해, 본 발명은 지구상에 풍부한 산화티타늄을 사용하고, 특히 박막 상으로 제조가 극히 용이한 다결정 내지 비정질(amorphous)의 산화티타늄을 박막 트랜지스터의 활성층으로 형성함으로써, 저비용으로 박막 트랜지스터를 제조할 수 있는 효과가 있다.Through this, the present invention can use a titanium oxide rich in the earth, and in particular, by forming a polycrystalline to amorphous titanium oxide which is extremely easy to manufacture in a thin film as the active layer of the thin film transistor, it is possible to manufacture a thin film transistor at low cost It has an effect.

본 발명은 친환경물질인 산화티타늄을 박막 트랜지스터의 활성층으로 형성함으로써, 기존의 박막 트랜지스터들이 가지고 있는 유해 환경 문제를 해결할 수 있는 효과가 있다.According to the present invention, by forming titanium oxide, which is an environmentally friendly material, as an active layer of a thin film transistor, there is an effect of solving a harmful environmental problem of existing thin film transistors.

본 발명은 산화티타늄을 박막 트랜지스터의 활성층으로 형성함으로써, 높은 전하 이동도 및 공기나 수분에 대한 안정성 등을 포함하는 박막 트랜지스터의 성능을 향상 시킬 수 있는 효과가 있다.The present invention has the effect of improving the performance of the thin film transistor including titanium oxide as an active layer of the thin film transistor, including high charge mobility and stability against air or moisture.

또한, 본 발명은 투명성을 갖는 산화티타늄을 박막 트랜지스터의 활성층으로 형성함으로써, 전자소자가 보이지 않도록 해야 하는 특수 용도의 전자 기기에 널리 적용될 수 있는 효과가 있다.In addition, the present invention has an effect that can be widely applied to special-purpose electronic devices that should not be visible by forming the titanium oxide having transparency as the active layer of the thin film transistor.

또한, 본 발명은 대면적의 디스플레이에 사용될 대면적의 박막트랜지스터를 대량 생산할 수 있고, 제조 공정이 저렴하여 제품의 양산성이 좋은 산화티타늄을 활성층으로 갖는 박막 트랜지스터의 제조 방법 및 이에 의해 제조된 박막트랜지스터를 제공하였다.In addition, the present invention can mass-produce a large-area thin film transistor to be used for a large-area display, and the manufacturing process is inexpensive, the production method of the thin film transistor having titanium oxide as an active layer having good mass productivity of the product and the thin film manufactured thereby A transistor was provided.

또한, 본 발명은 400℃이하의 저온에서도 생산할 수 있어, 유리전이온도가 낮은 플라스틱 필름 등을 기판으로 사용하거나, 저가의 유리 기판을 사용하여 박막트랜지스터를 제조 할 수 있는 방법을 제공하였다. In addition, the present invention can be produced at a low temperature of less than 400 ℃, using a plastic film having a low glass transition temperature, or the like, or a low-cost glass substrate to provide a method for manufacturing a thin film transistor.

이하에서는, 본 발명인 산화티타늄 활성층을 갖는 박막 트랜지스터의 제조하기 위한 방법 및 이에 의하여 제조된 박막트랜지스터를 실시할 수 있는 형태에 대하여 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a method for manufacturing a thin film transistor having a titanium oxide active layer of the present invention and a form in which the thin film transistor manufactured thereby can be implemented will be described in detail with reference to the accompanying drawings.

본 발명의 박막트랜지스터의 활성층을 구성하는 산화티타늄은 티타늄(titanium)을 산화시켜 생성되는 모든 종류의 산화물 즉, TiOx (0 < x ≤ 2)을 의미하며, 대표적인 것으로 TiO2, TiO 등을 포함할 수 있다.Titanium oxide constituting the active layer of the thin film transistor of the present invention means all kinds of oxides formed by oxidizing titanium, that is, TiO x (0 <x ≤ 2), and representative examples include TiO 2 , TiO, and the like. can do.

본 발명의 일실시형태에 따른 박막 트랜지스터는 절연막이 형성되는 MISFET(Metal Insulator Semiconductor Field Effect Transistor)를 제조하는 방법 으로 구분될 수 있다.The thin film transistor according to the exemplary embodiment of the present invention may be classified into a method of manufacturing a metal insulator semiconductor field effect transistor (MISFET) in which an insulating film is formed.

본 발명의 일실시형태에 따른 박막 트랜지스터는 기판, 활성층, 절연층, 게이트 전극, 소스 전극, 및 드레인 전극들의 일부 또는 전부를 포함할 수 있으며, 이들의 구성 형태에 따른 이들의 구성 방법에 따라 다양한 형태의 박막 트랜지스터의 제조방법을 구성할 수 있다.The thin film transistor according to the exemplary embodiment of the present invention may include a part or all of a substrate, an active layer, an insulating layer, a gate electrode, a source electrode, and a drain electrode, and may vary depending on their configuration method according to their configuration. The manufacturing method of the thin film transistor of the form can be comprised.

먼저, 절연막이 형성되는 MISFET의 구조의 박막트랜지스터의 제조방법을 도 1a 내지 도 1d를 참조하여 설명한다. 도 1a 내지 도 1d는 본 발명의 일실시형태에 따른 MISFET의 구조를 나타내는 단면도이다.First, a method of manufacturing a thin film transistor having a structure of an MISFET in which an insulating film is formed will be described with reference to FIGS. 1A to 1D. 1A to 1D are cross-sectional views showing the structure of a MISFET according to one embodiment of the present invention.

도 1a에 도시한 바와 같이, 본 발명의 일실시형태에 따른 박막 트랜지스터는 기판(substrate)(110)을 준비하여, 기판(110) 상에 소스 전극(source electrode)(120) 및 드레인 전극(drain electrode)(130)이 형성할 수 있다. 기판(110)과 기판(110) 상에 형성된 소스 전극(120) 및 드레인 전극(130) 상에 활성층(active layer)(140)을 형성할 수 있다.As shown in FIG. 1A, a thin film transistor according to an exemplary embodiment of the present invention may prepare a substrate 110, and may include a source electrode 120 and a drain electrode on the substrate 110. electrode) 130 may be formed. An active layer 140 may be formed on the substrate 110, the source electrode 120, and the drain electrode 130 formed on the substrate 110.

이후, 활성층(140)에 절연막(insulator)(150)을 형성하고, 절연막(150) 상에 게이트 전극(gate electrode)(160)이 형성할 수 있다. 여기서, 게이트 전극(160)의 폭은 소스 전극(120)과 드레인 전극(130) 간의 간격보다 약간 크게 형성할 수 있 다. 이러한 이유는 게이트 전극(160)의 폭과 소스 전극(120)과 드레인 전극(130) 간의 폭이 일치하는 것이 가장 이상적이지만 실제로 제작 마진을 고려해야 하기 때문이다.Thereafter, an insulating layer 150 may be formed on the active layer 140, and a gate electrode 160 may be formed on the insulating layer 150. Here, the width of the gate electrode 160 may be formed slightly larger than the gap between the source electrode 120 and the drain electrode 130. This is because the width of the gate electrode 160 and the width between the source electrode 120 and the drain electrode 130 are ideally matched, but the manufacturing margin must be considered in practice.

도 1b에 도시한 바와 같이, 본 발명의 일실시형태에 따른 박막 트랜지스터는 기판(110)을 준비하여, 기판(110) 상에 활성층(140)을 형성할 수 있다. 활성층(140) 상에 소스 전극(120) 및 드레인 전극(130)을 형성할 수 있다. 활성층(140)과 활성층(140) 상에 형성된 소스 전극(120) 및 드레인 전극(130) 상에 절연막(150)을 형성할 수 있다. 이후, 절연막(150) 상에 게이트 전극(160)을 형성할 수 있다.As shown in FIG. 1B, the thin film transistor according to the exemplary embodiment may prepare the substrate 110 and form the active layer 140 on the substrate 110. The source electrode 120 and the drain electrode 130 may be formed on the active layer 140. An insulating layer 150 may be formed on the active layer 140, the source electrode 120, and the drain electrode 130 formed on the active layer 140. Thereafter, the gate electrode 160 may be formed on the insulating layer 150.

도 1c에 도시한 바와 같이, 본 발명의 일실시형태에 따른 박막 트랜지스터는 기판(110)을 준비하여, 기판(110) 상에 게이트 전극(160)을 형성할 수 있다. 기판(110)과 기판(110) 상에 형성된 게이트 전극(160) 상에 절연막(150)을 형성할 수 있다. 절연막(150) 상에 활성층(140)을 형성할 수 있다. 이후, 활성층(140) 상에 소스 전극(120) 및 드레인 전극(130)을 형성할 수 있다.As illustrated in FIG. 1C, in the thin film transistor according to the exemplary embodiment, the substrate 110 may be prepared to form the gate electrode 160 on the substrate 110. An insulating layer 150 may be formed on the substrate 110 and the gate electrode 160 formed on the substrate 110. The active layer 140 may be formed on the insulating layer 150. Thereafter, the source electrode 120 and the drain electrode 130 may be formed on the active layer 140.

도 1d에 도시한 바와 같이, 본 발명의 일실시형태에 따른 박막 트랜지스터는 기판(110)이 형성되고 기판(110) 상에 게이트 전극(160)을 형성할 수 있다. 기판(110)과 기판(110) 상에 형성된 게이트 전극(160) 상에 절연막(150)을 형성할 수 있다. 절연막(150) 상에 소스 전극(120) 및 드레인 전극(130)을 형성할 수 있다. 이후, 절연막(150)과 절연막(150) 상에 형성된 소스 전극(120) 및 드레인 전극(130) 상에 활성층(140)을 형성할 수 있다.As illustrated in FIG. 1D, in the thin film transistor according to the exemplary embodiment, the substrate 110 may be formed and the gate electrode 160 may be formed on the substrate 110. An insulating layer 150 may be formed on the substrate 110 and the gate electrode 160 formed on the substrate 110. The source electrode 120 and the drain electrode 130 may be formed on the insulating layer 150. Thereafter, the active layer 140 may be formed on the insulating layer 150, the source electrode 120, and the drain electrode 130 formed on the insulating layer 150.

상기 도 1a 내지 도 1d에 도시한 실시예에서 상기 활성층의 형성은 전구체로서 티타늄(Ti) 유기화합물을 화학기상증착법 (CVD; Chemical Vapor Deposition) 또는 유기금속 화학기상증착법(MOCVD ; Metal Organic Chemical Vapor Deposition) 또는 원자층증착법(ALD : Atomic Layer Deposition), 저기압화학기상증착법(LPCVD ; Low Pressure Chemical Vapor Deposition) 및 플라즈마 화학기상증착법(PECVD ; Plasma Enhanced Vapor Deposition) 중에서 선택된 1종의 방법으로 증착할 수 있다. 이때, 증착온도는 400℃이하, 바람직하게는 300℃이하로 할 수 있으며, 특히, 산소(O2), 오존(O3) 및 수증기(H2O) 중 선택된 1종 이상의 음이온 소스 분위기에서 하는 것이 바람직하다. 이 때, 전구체는 산소(O2), 오존(O3) 및 수증기(H2O) 중 선택된 1종 이상의 분위기에서 산소와의 반응성이 좋은 티타늄 테트라 알콕사이드(Titaniun tetra alkoxide ; Ti(OR)4, R은 알킬기), 티타늄 테트라 클로라이드(Titaniun tetra chloride ; TiCl4) 및 티타늄 테트라 다이알킬아민(Titanium tetra diaklyamine ; Ti(NR2)4, R은 알킬기) 중에서 선택된 1종 이상인 것이 바람직하며, 저온에서 산소와 반응을 잘 할 수 있는 티타늄 유기화합물을 선택하여 사용할 수 있다. 이때, 기판(110)은 실리콘 기판, 반도체 기판, 유리 기판, 플라스틱 기판, 금속 호일, 직물, 종이, 및 나무 등을 사용하여 형성될 수 있다. 1A to 1D, the active layer may be formed by chemical vapor deposition (CVD) or metal organic chemical vapor deposition (MOCVD) of a titanium (Ti) organic compound as a precursor. ) Or Atomic Layer Deposition (ALD), Low Pressure Chemical Vapor Deposition (LPCVD) and Plasma Enhanced Vapor Deposition (PECVD). . At this time, the deposition temperature may be 400 ℃ or less, preferably 300 ℃ or less, in particular, at least one anion source selected from oxygen (O 2 ), ozone (O 3 ) and water vapor (H 2 O). It is preferable. At this time, the precursor is a titanium tetra alkoxide (Titaniun tetra alkoxide; Ti (OR) 4 , good reactivity with oxygen in one or more atmospheres selected from oxygen (O 2 ), ozone (O 3 ) and water vapor (H 2 O). R is an alkyl group), titanium tetrachloride (TiCl 4 ) and titanium tetra diaklyamine (Ti (NR 2 ) 4 , R is an alkyl group) is preferably at least one selected from, and oxygen at low temperature Titanium organic compounds that can react well with can be selected and used. In this case, the substrate 110 may be formed using a silicon substrate, a semiconductor substrate, a glass substrate, a plastic substrate, a metal foil, a fabric, paper, and wood.

또한, 산화티타늄 활성층(140)은 보통 n형이나, p형 산화티타늄의 경우 기존의 반도체 도핑 방법과 같이 불순물을 첨가하거나 혼합하여 형성될 수 있으며, n형의 경우도 도핑에 의해 전도도를 조절할 수 있다. 활성층(140)은 산화티타늄에 일정 비율로 다른 산화물이나 금속 예를 들면, Sn전구체, In전구체, Zn전구체, Al전구체, Ta전구체, V전구체, Cr전구체, Fe전구체, Mo전구체, W전구체 등을 혼합하여 형성될 수도 있다. 이러한 방법을 통하여 산화티타늄을 활성층으로 형성하는 박막 트랜지스터의 성능을 더욱 향상시킬 수 있다. In addition, the titanium oxide active layer 140 is usually n-type, but in the case of p-type titanium oxide can be formed by adding or mixing impurities as in the conventional semiconductor doping method, n-type also can control the conductivity by doping have. The active layer 140 may be formed of another oxide or metal such as Sn precursor, In precursor, Zn precursor, Al precursor, Ta precursor, V precursor, Cr precursor, Fe precursor, Mo precursor, W precursor, etc. It may be formed by mixing. Through this method, the performance of the thin film transistor which forms titanium oxide as an active layer can be further improved.

이와 같은 활성층 특히, TiOx 활성층, TiOx 활성 채널, 또는 TiOx 활성 채널층을 갖도록 실제 실험을 기반으로 생성된 박막 트랜지스터의 제조 원리 및 그 실험 결과를 도 3 내지 도 5를 참조하여 설명한다.The manufacturing principle and the experimental result of the thin film transistor generated based on the actual experiment to have such an active layer, in particular, TiO x active layer, TiO x active channel, or TiO x active channel layer will be described with reference to FIGS. 3 to 5.

본 발명의 실험예에서는 도 3과 같은 구조의 바텀-게이트(Bottom-Gate) 및 탑-컨택트(Top-contact) 타입의 박막트랜지스터를 구성하였다. In the experimental example of the present invention, a bottom-gate and a top-contact type thin film transistor having the structure shown in FIG. 3 were constructed.

우선, n+-Si 기판상에 100nm 두께의 SiO2 층을 5nm/sec의 비율로 PECVD(plasma-enhanced chemical vapor deposition)에 의해 게이트 유전층(gate dielectric layer)으로써 형성하였다.First, a 100 nm thick SiO 2 layer was formed on the n + -Si substrate as a gate dielectric layer by plasma-enhanced chemical vapor deposition (PECVD) at a rate of 5 nm / sec.

이 후, 산화티타늄의 활성층은 SiO2 게이트 유전층의 상부에 유기금속 화학기상증착법으로 전구체는 티타늄 테트라 이소프로폭사이드(TTIP ; Titanium Tetra IsoPropoxide) 약 20g을 소스 Bobble에 충전하여 표 1과 같은 조건으로 증착하였다. After that, the active layer of titanium oxide was organometallic chemical vapor deposition on the SiO 2 gate dielectric layer, and the precursor was filled with about 20 g of titanium tetra isopropoxide (TTIP) in a source Bobble under the conditions shown in Table 1. Deposited.

실험예 1Experimental Example 1 실험예 2Experimental Example 2 Base Pressure(Torr)Base Pressure (Torr) 0.030.03 0.030.03 Working Pressure(Torr)Working Pressure (Torr) 0.490.49 0.490.49 Deposition Temp.(℃)Deposition Temp. (℃) 260260 260260 SubstrateSubstrate SiO2/SiSiO 2 / Si SiO2/SiSiO 2 / Si PrecursorPrecursor TTIPTTIP TTIPTTIP Precursor Temp .(℃)Precursor Temp. (℃) 8080 8080 O2 gas MFC(sccm)O 2 gas MFC (sccm) 125125 125125 Deposition Time(min)Deposition Time (min) 2020 2020 활성층 두계(nm)Active layer thickness (nm) 30nm30 nm 30nm30 nm W/L(㎛/㎛)W / L (µm / µm) 250/5250/5 600/20600/20

도 3a 내지 도 3c는 본 발명의 실험예 1에 따라 형성된 산화티타늄 활성층의 표면 및 단면을 SEM 촬영한 것이다. 즉, SEM사진과 같이 유기금속 화학기상증착법(MOCVD ; Metal Organic Chemical Vapor Deposition)로 증착된 활성층의 박막두께는 전체적으로 균일하다는 것을 알 수있다.3A to 3C are SEM images of the surface and the cross section of the titanium oxide active layer formed according to Experimental Example 1 of the present invention. That is, it can be seen that the thin film thickness of the active layer deposited by MOCVD (Metal Organic Chemical Vapor Deposition) as shown in the SEM photograph is uniform throughout.

이후, Al(150nm)층이 소스/드레인 컨택(contact)을 위하여 열 증착법(thermal evaporation)에 의해 형성되는데, 패터닝은 흔히 알려진 포토 리소그라피 방법을 이용하는 리프트 오프(lift-off) 공정 또는 메탈에칭공정을 통해 이루어진다. 물론 이러한 리소그라피식 패터닝 공정 대신 프린팅이나 섀도우 마스킹 등을 통해서 직접 소스와 드레인 전극 패턴을 형성할 수도 있다.An Al (150 nm) layer is then formed by thermal evaporation for source / drain contacts, and patterning is commonly performed using a lift-off process or metal etching process using known photolithography methods. Is done through. Of course, instead of the lithographic patterning process, the source and drain electrode patterns may be directly formed through printing or shadow masking.

소스/드레인 전극은 일례로 다음과 같이 포토리소그래픽 리프트 오프(photolithographic lift-off) 처리를 사용하여 형성될 수 있다. 포토레지스트(photoresist)는 예컨대 30초 동안 5000 rpm 정도로 TiOx 막/기판 상에 스핀 코팅(spin-coating)되고, 1분 동안 90℃의 핫 플레이트(hot plate)상에서 건조될 수 있다. 패터닝 이전에, 포토레지스트로 코팅된 샘플들은 포토레지스트 필름의 표면 영역에 오버행(overhang) 구조를 구현하기 위해 5분 동안 클로로벤젠(chlorobenzene)에 담겨질 수 있다. 상술한 오버행 구조는 리프트 오프(lift-off) 공정을 더 쉽게 할 수 있다. 또한, 이러한 샘플들은 접촉식 마스크 얼라이너(contact mask aligner)를 사용하여 포토마스크(photomask)에 대해 정렬될 수 있다(예컨대, 9초 정도 UV 노광).The source / drain electrodes can be formed using photolithographic lift-off processing as an example. The photoresist can be spin-coated on a TiO x film / substrate, for example, at 5000 rpm for 30 seconds, and dried on a hot plate at 90 ° C. for 1 minute. Prior to patterning, the samples coated with photoresist may be immersed in chlorobenzene for 5 minutes to implement an overhang structure in the surface area of the photoresist film. The overhang structure described above can make the lift-off process easier. In addition, these samples can be aligned to the photomask using a contact mask aligner (eg, UV exposure on the order of 9 seconds).

디벨로퍼를 이용 포토레지스트의 소스/드레인 패턴을 만든 후에, Ti(5nm)/Au(150nm)층이 열 증착법으로 부착되고, 이후 아세톤(acetone)을 사용한 리프트 오프(lift-off) 공정에 의해 패터닝 될 수 있다. After creating the source / drain pattern of the photoresist using the developer, the Ti (5nm) / Au (150nm) layer is deposited by thermal evaporation, and then patterned by a lift-off process using acetone. Can be.

그 이외에 TiOx 활성층위에 소스(Source)와 드레인(Drain)메탈을 전체적으로 증착한후 포토레지스트 작업을 통해 패터닝을 한후 메탈 에칭을 통해서도 공정을 진행할 수있다.In addition, the source and drain metals are deposited on the TiO x active layer as a whole and then patterned by photoresist, followed by metal etching.

이와 같은 제조 과정을 통하여 제조된 산화티타늄을 활성층으로 갖는 박막트랜지스터 소자의 전기 특성은 파라메트릭 분석기(parametric analyzer)를 사용하여 측정하였으며, 그 결과를 도 4a, 도 4b, 및 도 5를 참조하여 설명한다. The electrical properties of the thin film transistor device having titanium oxide prepared through the manufacturing process as an active layer were measured using a parametric analyzer, and the results are described with reference to FIGS. 4A, 4B, and 5. do.

박막트랜지스터 소자는 n-채널 인핸스먼트 모드(enhancement-mode)특성을 보이는데, 핀치오프(pinch-off)와 포화 특성이 잘 나타나 게이트 전압 변화에 따른 모듈레이션(gate modulation) 특성을 나타내고 있다. 특히, 전류 포화(current saturation) 특성은, AMOLED(active-matrix organic display)내에 집적된 구동 TFT와 같이 전류 소스로 사용되는 경우에 매우 중요하다.The thin film transistor device exhibits an n-channel enhancement-mode characteristic. The pinch-off and saturation characteristics are well represented, indicating a modulation characteristic according to a gate voltage change. In particular, the current saturation characteristic is very important when used as a current source, such as a driving TFT integrated in an active-matrix organic display (AMOLED).

도 4a 및 4b는 본 발명의 실험예 1에 따른 박막트랜지스터 소자의 전기 특성을 나타내는 그래프, 즉, 실험예 1의 박막트랜지스터 소자의 게이트 전압대 소스-드레인간 전류 특성을 나타내는 소위 트랜지스터 전달 특성 (transfer characteristics) 커브로, VDS가 35V일 때, 6.3×10-2cm2V-1sec-1의 전계효과 이동도(field-effect mobility)와 -4.05V의 문턱전압이 산정된다. 또한, 온/오프(on/off) 전류 비율(ratio)은 2.7×105이고, sub-threshold swing은 1.47V/dec로 측정된다는 것을 알 수 있다.4A and 4B are graphs showing electrical characteristics of a thin film transistor device according to Experimental Example 1 of the present invention, that is, a so-called transistor transfer characteristic showing gate voltage versus source-drain current characteristics of the thin film transistor device of Experimental Example 1 characteristics curve, when V DS is 35V, a field-effect mobility of 6.3 × 10 −2 cm 2 V −1 sec −1 and a threshold voltage of −4.05V are calculated. It can also be seen that the on / off current ratio is 2.7 × 10 5 , and the sub-threshold swing is measured at 1.47V / dec.

도 7은 본 발명의 실험예 2에 따른 박막트랜지스터 소자의 전기 특성을 나타내는 그래프로서, 실험예 2의 박막트랜지스터 소자의 게이트 전압대 소스-드레인간 전류 특성을 나타내는 소위 트랜지스터 전달 특성 (transfer characteristics) 커브로, VDS가 35V일때,6.62×0-2cm2V-1sec-1의 전계효과 이동도(field-effect mobility)와 4.08V의 문턱전압이 산정된다. 또한, 온/오프(on/off) 전류 비율(ratio)은8.46×102이고, sub-threshold swing은 6.01V/dec로 측정된다는 것을 알 수 있다.7 is a graph showing the electrical characteristics of the thin film transistor device according to Experimental Example 2 of the present invention, the so-called transistor transfer characteristics curve showing the gate voltage versus source-drain current characteristics of the thin film transistor device of Experimental Example 2 Thus, when V DS is 35V, a field-effect mobility of 6.62 × 0 −2 cm 2 V −1 sec −1 and a threshold voltage of 4.08 V are calculated. It can also be seen that the on / off current ratio is 8.46 × 10 2 , and the sub-threshold swing is measured at 6.01 V / dec.

실험예 1 및 실험예 2는 도 6a , 도 6b 및 도 7에 도시된 바와 같이 박막트랜지스터의 특성이 무엇보다도 결과 특성(Output charateristics)에서 보여진 것 처럼 전류의 포화 상태 (Saturation) 영역의 전류값들이 일정하게 보여주고 있어 구동회로에서의 정전류원으로 사용하는데 문제가 없음을 확연히 보여주고 있다. 앞으로 포화영역이 확연히 일정하게 보여지는 소자를 이용하여 점차적인 최적화를 통해서 전자이동도, 문턱전압, On-off ratio, Sub-threshold swing값들을 향상시킬 수 있다.As shown in FIGS. 6A, 6B and 7, Experimental Example 1 and Experimental Example 2 show that the current values of the saturation region of the current are as shown in the output charateristics. As it is shown constantly, it shows clearly that there is no problem to use as a constant current source in the driving circuit. In the future, using the device whose saturation region is clearly constant, the electron mobility, threshold voltage, on-off ratio, and sub-threshold swing values can be improved through gradual optimization.

본 발명의 실시형태 및 실험예에서 제시되는 박막 트랜지스터(thin film transistor)는 활성 채널층으로서 화학기상증착법(CVD ; Chemical Vapor Deposition), 유기금속 화학기상증착법(MOCVD ; Metal Organic Chemical Vapor Deposition), 원자층증착법(ALD : Atomic Layer Deposition), 저기압화학기상증착법(LPCVD ; Low Pressure Chemical Vapor Deposition) 및 플라즈마 화학기상증착법(PECVD ; Plasma Enhanced Vapor Deposition) 중에서 선택된 1종의 방법으로 증착하는 방법을 이용하여 박막 산화티타늄을 갖는 최초의 성공적인 구현이었다.The thin film transistors presented in the embodiments and experimental examples of the present invention are chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), atoms as active channel layers. Thin film is deposited using one of the methods selected from Atomic Layer Deposition (ALD), Low Pressure Chemical Vapor Deposition (LPCVD) and Plasma Enhanced Vapor Deposition (PECVD). It was the first successful implementation with titanium oxide.

이러한 연구 결과를 통해 MOxTFT 기술을 위한 재료의 선택 범위를 넓힐 수 있고 MOxTFT의 성능을 개선하기 위해 사용될 수 있는 새로운 접근 방식도 제공할 수 있게 되었다. 산화티타늄은 대량생산 가능한 친환경 물질로서 값이 매우 저렴하다는 점과 나노입자 분산의 용액 공정 가능성을 고려해 볼 때, 이번 발명의 실시형태 및 실험예에서 보여준 결과는 많은 분야에서 응용될 수 있을 것이며, 또한 투명성 전자 소자와 같은 일부 새로운 분야에도 응용될 수 있을 것으로 예상된다. 산화티타늄 기반 박막트랜지스터의 성능은, 제조 공정의 최적화를 이루고, 산화티타늄 박막 성막을 위한 다수의 성장기술등을(growth technique) 활용한다면, 더욱 더 향상 될 수 있다. 예를 들면, 산화티타늄 나노와이어(nanowire)의 등을 이용하여, 이를 소스와 드레인간 채널에 나란히 배열한다면 스캐터링이 적은 전하 수송이 가능해 질 것이므로 전하이동도가 훨씬 더 증가 할 수 있을 것이다. These findings allow for a wider selection of materials for MOxTFT technology and provide new approaches that can be used to improve the performance of MOxTFT. Considering that titanium oxide is a mass-produced eco-friendly material, which is very inexpensive, and the possibility of solution processing of nanoparticle dispersion, the results shown in the embodiments and experimental examples of the present invention may be applied in many fields. It is anticipated that it may be applied to some new fields such as transparent electronic devices. Performance of titanium oxide based thin film transistors optimizes the manufacturing process The use of multiple growth techniques for thin film deposition can be further improved. For example, using titanium oxide nanowires and the like, if they are arranged side by side in the channel between the source and drain, less scattering of charge transport will be possible, so that the charge mobility can be increased even more.

본 발명에 의한, 박막 트랜지스터를 제조하기 위한 방법 및 그 구조는 본 발명의 기술적 사상의 범위 내에서 다양한 형태로 변형, 응용 가능하며 상기 실시 예에 한정되지 않는다. 또한, 상기 실시 예와 도면은 발명의 내용을 상세히 설명하기 위한 목적일 뿐, 발명의 기술적 사상의 범위를 한정하고자 하는 목적은 아니며, 이상에서 설명한 본 발명은 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에 있어 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형, 및 변경이 가능하므로 상기 실시 예 및 첨부된 도면에 한정되는 것은 아님은 물론이며, 후술하는 청구범위뿐만이 아니라 청구범위와 균등 범위를 포함하여 판단되어야 한다.The method and structure of the thin film transistor according to the present invention can be modified and applied in various forms within the scope of the technical idea of the present invention and are not limited to the above embodiments. In addition, the embodiments and drawings are merely for the purpose of describing the contents of the invention in detail, not intended to limit the scope of the technical idea of the invention, the present invention described above is common knowledge in the technical field to which the present invention belongs As those skilled in the art can have various substitutions, modifications, and changes without departing from the technical spirit of the present invention, it is not limited to the above embodiments and the accompanying drawings, of course, and not only the claims to be described below but also claims Judgment should be made including scope and equivalence.

도 1a 내지 도 1d은 본 발명의 일실시형태에 따른 MISFET의 구조를 나타내는 단면도이다.1A to 1D are cross-sectional views showing the structure of a MISFET according to an embodiment of the present invention.

도 2는 본 발명의 실험예에 따른 박막트랜지스터의 구조를 설명하기 위한 예시도이다.2 is an exemplary view for explaining the structure of a thin film transistor according to an experimental example of the present invention.

도 3a 내지 3c는 본 발명의 실험예 1에 따른 활성층 표면 및 단면의 SEM사진이다. 3a to 3c are SEM images of the surface and the cross-section of the active layer according to Experimental Example 1 of the present invention.

도 4a 및 도 4c은 본 발명의 실험예 1에 따른 박막트랜지스터 소자의 전기 특성을 나타내는 실험결과 그래프이다. 4A and 4C are graphs of experimental results showing electrical characteristics of a thin film transistor device according to Experimental Example 1 of the present invention.

도 5는 본 발명의 실험예 2에 따른 박막트랜지스터 소자의 전기 특성을 나타내는 실험결과 그래프이다.5 is a graph showing experimental results showing electrical characteristics of a thin film transistor device according to Experimental Example 2 of the present invention.

< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>

110: 기판110: substrate

120: 소스 전극120: source electrode

130: 드레인 전극130: drain electrode

140: 활성층140: active layer

150: 절연막150: insulating film

160: 게이트 전극160: gate electrode

Claims (18)

기판을 준비하는 단계;Preparing a substrate; 상기 기판 상에 활성층을 형성하는 단계; 및Forming an active layer on the substrate; And 상기 활성층 상에 절연막을 형성하는 단계를 포함하고, Forming an insulating film on the active layer, 상기 활성층을 형성하는 단계는 Forming the active layer 전구체로서 티타늄(Ti)을 포함한 유기화합물을 화학기상증착법(CVD ; Chemical Vapor Deposition), 유기금속 화학기상증착법(MOCVD ; Metal Organic Chemical Vapor Deposition), 원자층증착법(ALD : Atomic Layer Deposition), 저기압화학기상증착법(LPCVD ; Low Pressure Chemical Vapor Deposition) 및 플라즈마 화학기상증착법(PECVD ; Plasma Enhanced Chemical Vapor Deposition) 중에서 선택된 1종의 방법으로 증착하는 것을 특징으로 하는 산화티타늄을 활성층으로 갖는 박막트랜지스터의 제조 방법.Organic compounds containing titanium (Ti) as precursors are deposited by chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), and low pressure chemistry. A method of manufacturing a thin film transistor having titanium oxide as an active layer, characterized in that the deposition is carried out by one of the following methods: LPCVD (Low Pressure Chemical Vapor Deposition) and Plasma Enhanced Chemical Vapor Deposition (PECVD). 제 1항에 있어서,The method of claim 1, 상기 기판 상에 소스 전극과 드레인 전극을 형성하는 단계; 및Forming a source electrode and a drain electrode on the substrate; And 상기 절연막 상에 게이트 전극을 형성되는 단계를 더 포함하고, 상기 소스 전극과 상기 드레인 전극은 상기 활성층으로 덮여있는 것을 특징으로 하는 산화티타늄을 활성층으로 갖는 박막트랜지스터의 제조 방법.And forming a gate electrode on the insulating film, wherein the source electrode and the drain electrode are covered with the active layer. 제 1항에 있어서,The method of claim 1, 상기 활성층 상에 소스 전극과 드레인 전극을 형성하는 단계; 및Forming a source electrode and a drain electrode on the active layer; And 상기 절연막 상에 게이트 전극을 형성하는 단계를 더 포함하고, 상기 소스 전극과 상기 드레인 전극은 상기 절연막으로 덮여있는 것을 특징으로 하는 산화티타늄을 활성층으로 갖는 박막트랜지스터의 제조 방법.And forming a gate electrode on the insulating film, wherein the source electrode and the drain electrode are covered with the insulating film. 기판을 준비하는 단계;Preparing a substrate; 상기 기판 상에 절연막을 형성하는 단계; 및Forming an insulating film on the substrate; And 상기 절연막 상에 활성층을 형성하는 단계를 포함하고, Forming an active layer on the insulating film, 상기 활성층을 형성하는 단계는 Forming the active layer 전구체로서 티타늄(Ti)을 포함한 유기화합물을 화학기상증착법(CVD ; Chemical Vapor Deposition), 유기금속 화학기상증착법(MOCVD ; Metal Organic Chemical Vapor Deposition), 원자층증착법(ALD : Atomic Layer Deposition), 저기압화학기상증착법(LPCVD ; Low Pressure Chemical Vapor Deposition) 및 플라즈마 화학기상증착법(PECVD ; Plasma Enhanced Vapor Deposition) 중에서 선택된 1종의 방법으로 증착하는 것을 특징으로 하는 산화티타늄을 활성층으로 갖는 박막트랜지스터의 제조 방법.Organic compounds containing titanium (Ti) as precursors are deposited by chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), and low pressure chemistry. A method of manufacturing a thin film transistor having titanium oxide as an active layer, characterized in that the deposition is carried out by one of the methods selected from low pressure chemical vapor deposition (LPCVD) and plasma enhanced vapor deposition (PECVD). 제 4항에 있어서,The method of claim 4, wherein 상기 기판 상에 게이트 전극을 형성하는 단계; 및Forming a gate electrode on the substrate; And 상기 활성층 상에 소스 전극과 드레인 전극을 형성하는 단계를 더 포함하고, 상기 게이트 전극은 상기 절연막으로 덮여있는 것을 특징으로 하는 산화티타늄을 활성층으로 갖는 박막트랜지스터의 제조 방법.And forming a source electrode and a drain electrode on the active layer, wherein the gate electrode is covered with the insulating film. 제 5항에 있어서,The method of claim 5, 상기 기판 상에 게이트 전극을 형성하는 단계; 및Forming a gate electrode on the substrate; And 상기 활성층 상에 소스 전극과 드레인 전극을 형성하는 단계를 더 포함하고, 상기 게이트 전극은 상기 절연막으로 덮여있는 것을 특징으로 하는 산화티타늄을 활성층으로 갖는 박막트랜지스터의 제조 방법.And forming a source electrode and a drain electrode on the active layer, wherein the gate electrode is covered with the insulating film. 제 1항 또는 제 4항에 있어서, The method according to claim 1 or 4, 화학기상증착법(CVD ; Chemical Vapor Deposition), 유기금속 화학기상증착법(MOCVD ; Metal Organic Chemical Vapor Deposition), 원자층증착법(ALD : Atomic Layer Deposition), 저기압화학기상증착법(LPCVD ; Low Pressure Chemical Vapor Deposition) 및 플라즈마 화학기상증착법(PECVD ; Plasma Enhanced Vapor Deposition) 중에서 선택된 1종의 방법으로 증착하는 것은 400℃이하의 온도에서 증착하는 것을 특징으로 하는 산화티타늄을 활성층으로 갖는 박막트랜지스터의 제조 방법.Chemical Vapor Deposition (CVD), Metal Organic Chemical Vapor Deposition (MOCVD), Atomic Layer Deposition (ALD), Low Pressure Chemical Vapor Deposition (LPCVD) And Plasma Enhanced Vapor Deposition (PECVD). The method of manufacturing a thin film transistor having titanium oxide as an active layer, characterized in that the deposition at a temperature of 400 ℃ or less. 제 1항 또는 제 4항에 있어서, The method according to claim 1 or 4, 화학기상증착법(CVD ; Chemical Vapor Deposition), 유기금속 화학기상증착법(MOCVD ; Metal Organic Chemical Vapor Deposition), 원자층증착법(ALD : Atomic Layer Deposition), 저기압화학기상증착법(LPCVD ; Low Pressure Chemical Vapor Deposition) 및 플라즈마 화학기상증착법(PECVD ; Plasma Enhanced Vapor Deposition) 중에서 선택된 1종의 방법으로 증착하는 것은 300℃이하의 온도에서 증착하는 것을 특징으로 하는 산화티타늄을 활성층으로 갖는 박막트랜지스터의 제조 방법.Chemical Vapor Deposition (CVD), Metal Organic Chemical Vapor Deposition (MOCVD), Atomic Layer Deposition (ALD), Low Pressure Chemical Vapor Deposition (LPCVD) And Plasma Enhanced Vapor Deposition (PECVD). The method of manufacturing a thin film transistor having titanium oxide as an active layer, characterized in that the deposition at a temperature of 300 ℃ or less. 제 1항 또는 제 4항에 있어서, The method according to claim 1 or 4, 화학기상증착법(CVD ; Chemical Vapor Deposition), 유기금속 화학기상증착법(MOCVD ; Metal Organic Chemical Vapor Deposition), 원자층증착법(ALD : Atomic Layer Deposition), 저기압화학기상증착법(LPCVD ; Low Pressure Chemical Vapor Deposition) 및 플라즈마 화학기상증착법(PECVD ; Plasma Enhanced Vapor Deposition) 중에서 선택된 1종의 방법으로 증착하는 것은 산소(O2), 오존(O3) 및 수증기(H2O) 중 선택된 1종 이상의 음이온 소스(Anion souce)분위기에서 증착하는 것을 특징으로 하는 산화티타늄을 활성층으로 갖는 박막트랜지스터의 제조 방법.Chemical Vapor Deposition (CVD), Metal Organic Chemical Vapor Deposition (MOCVD), Atomic Layer Deposition (ALD), Low Pressure Chemical Vapor Deposition (LPCVD) And one or more of anion sources selected from oxygen (O 2 ), ozone (O 3 ), and water vapor (H 2 O) may be deposited by one method selected from among plasma enhanced vapor deposition (PECVD). A method of manufacturing a thin film transistor having titanium oxide as an active layer, characterized in that deposited in an atmosphere. 제 9항에 있어서, The method of claim 9, 음이온 소스 분위기에서 수증기(H2O)는 10 ~ 80℃의 온도로 제공되는 것을 특징으로 하는 산화티타늄을 활성층으로 갖는 박막트랜지스터의 제조 방법. Water vapor (H 2 O) in the anion source atmosphere is a method of manufacturing a thin film transistor having titanium oxide as an active layer, characterized in that provided at a temperature of 10 ~ 80 ℃. 제 1항 또는 제 4항에 있어서, The method according to claim 1 or 4, 화학기상증착법(CVD ; Chemical Vapor Deposition), 유기금속 화학기상증착법(MOCVD ; Metal Organic Chemical Vapor Deposition), 원자층증착법(ALD : Atomic Layer Deposition), 저기압화학기상증착법(LPCVD ; Low Pressure Chemical Vapor Deposition) 및 플라즈마 화학기상증착법(PECVD ; Plasma Enhanced Vapor Deposition) 중에서 선택된 1종의 방법으로 증착하는 것은 5초 ~ 50분 분 동안 증착하는 것을 특징으로 하는 산화티타늄을 활성층으로 갖는 박막트랜지스터의 제조 방법.Chemical Vapor Deposition (CVD), Metal Organic Chemical Vapor Deposition (MOCVD), Atomic Layer Deposition (ALD), Low Pressure Chemical Vapor Deposition (LPCVD) And Plasma Enhanced Vapor Deposition (PECVD), wherein the deposition is performed by one method selected from the group consisting of titanium oxide as an active layer, characterized in that the deposition for 5 seconds to 50 minutes. 제 1항 또는 제 4항에 있어서, The method according to claim 1 or 4, 화학기상증착법(CVD ; Chemical Vapor Deposition), 유기금속 화학기상증착법(MOCVD ; Metal Organic Chemical Vapor Deposition), 원자층증착법(ALD : Atomic Layer Deposition), 저기압화학기상증착법(LPCVD ; Low Pressure Chemical Vapor Deposition) 및 플라즈마 화학기상증착법(PECVD ; Plasma Enhanced Vapor Deposition) 중에서 선택된 1종의 방법으로 증착하는 것은 활성층의 두께 형성속도가 1Å/min ~ 1㎛/min으로 증착하는 것을 특징으로 하는 산화티타늄을 활성층으로 갖는 박막트랜지스터의 제조 방법.Chemical Vapor Deposition (CVD), Metal Organic Chemical Vapor Deposition (MOCVD), Atomic Layer Deposition (ALD), Low Pressure Chemical Vapor Deposition (LPCVD) And plasma chemical vapor deposition (PECVD), wherein the deposition is carried out by one of the methods selected from the group consisting of titanium oxide having an active layer thickness of 1 μm / min to 1 μm / min. Method of manufacturing thin film transistor. 제 1항 또는 제 4항에 있어서, The method according to claim 1 or 4, 화학기상증착법(CVD ; Chemical Vapor Deposition), 유기금속 화학기상증착법(MOCVD ; Metal Organic Chemical Vapor Deposition), 원자층증착법(ALD : Atomic Layer Deposition), 저기압화학기상증착법(LPCVD ; Low Pressure Chemical Vapor Deposition) 및 플라즈마 화학기상증착법(PECVD ; Plasma Enhanced Vapor Deposition) 중에서 선택된 1종의 방법으로 증착하는 것은 활성층의 두께가 1Å ~ 1㎛가 되도로 증착하는 것을 특징으로 하는 산화티타늄을 활성층으로 갖는 박막트랜지스터의 제조 방법.Chemical Vapor Deposition (CVD), Metal Organic Chemical Vapor Deposition (MOCVD), Atomic Layer Deposition (ALD), Low Pressure Chemical Vapor Deposition (LPCVD) And plasma chemical vapor deposition (PECVD), wherein the deposition is carried out by one of the selected methods, the thin film transistor having titanium oxide as an active layer, wherein the active layer is deposited to have a thickness of 1 μm to 1 μm. Way. 제 1항 또는 제 4항에 있어서, The method according to claim 1 or 4, 전구체로서 티타늄(Ti)을 포함한 유기화합물은 티타늄 테트라 알콕사이드(Titaniun tetra alkoxide ; Ti(OR)4, R은 알킬기), 티타늄 테트라 클로라이드(Titaniun tetra chloride ; TiCl4) 및 티타늄 테트라 다이알킬아민(Titanium tetra diaklyamine ; Ti(NR2)4, R은 알킬기) 중 선택된 1종 이상인 것을 특징으로 하는 산화티타늄을 활성층으로 갖는 박막트랜지스터의 제조 방법.Organic compounds containing titanium (Ti) as precursors include titanium tetra alkoxide (Ti (OR) 4 , R is an alkyl group), titanium tetrachloride (TiCl 4 ) and titanium tetra dialkylamine (Titanium tetra A method for producing a thin film transistor having titanium oxide as an active layer, characterized in that at least one selected from diaklyamine (Ti (NR 2 ) 4 , R is an alkyl group). 제 14항에 있어서, The method of claim 14, 전구체로서 티타늄(Ti) 유기화합물은 티타늄 테트라 이소프로폭사이드(TTIP ; Titanium Tetra IsoPropoxide)인 것을 특징으로 하는 산화티타늄을 활성층 으로 갖는 박막트랜지스터의 제조 방법.Titanium (Ti) organic compound as a precursor is titanium tetra isopropoxide (TTIP; Titanium Tetra IsoPropoxide) characterized in that the manufacturing method of a thin film transistor having a titanium oxide active layer. 제 1항 또는 제 4항에 있어서, The method according to claim 1 or 4, 전구체로서 티타늄(Ti)을 포함한 유기화합물은 10 ~ 200℃의 온도로 제공되는 것을 특징으로 하는 산화티타늄을 활성층으로 갖는 박막트랜지스터의 제조 방법.An organic compound including titanium (Ti) as a precursor is a method of manufacturing a thin film transistor having titanium oxide as an active layer, characterized in that provided at a temperature of 10 ~ 200 ℃. 제 1항 내지 제 16항 중 어느 한 항에 의하여 제조된 것을 특징으로 하는 산화티타늄을 활성층으로 갖는 박막트랜지스터.A thin film transistor having titanium oxide as an active layer, which is prepared according to any one of claims 1 to 16. 제 17항에 있어서, 산화티타늄 활성층의 두께는 1Å ~ 1㎛인 것을 특징으로 하는 산화티타늄을 활성층으로 갖는 박막트랜지스터.18. The thin film transistor according to claim 17, wherein the titanium oxide active layer has a thickness of about 1 mu m to about 1 mu m.
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