KR20100013978A - Semiconductor device and forming method of the same - Google Patents

Semiconductor device and forming method of the same Download PDF

Info

Publication number
KR20100013978A
KR20100013978A KR1020080075742A KR20080075742A KR20100013978A KR 20100013978 A KR20100013978 A KR 20100013978A KR 1020080075742 A KR1020080075742 A KR 1020080075742A KR 20080075742 A KR20080075742 A KR 20080075742A KR 20100013978 A KR20100013978 A KR 20100013978A
Authority
KR
South Korea
Prior art keywords
film
layer
pattern
forming
polysilicon
Prior art date
Application number
KR1020080075742A
Other languages
Korean (ko)
Inventor
임종순
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020080075742A priority Critical patent/KR20100013978A/en
Publication of KR20100013978A publication Critical patent/KR20100013978A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823443—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors

Abstract

The present invention relates to a semiconductor device capable of uniformly forming a metal silicide film and a manufacturing method thereof.

A method of manufacturing a semiconductor device according to the present invention includes the steps of forming a stacked pattern comprising a polysilicon film on the semiconductor substrate, forming an insulating film having a lower height than the stacked pattern in the space between the stacked pattern, the surface of the stacked pattern And forming a diffusion barrier along the surface of the insulating film, patterning the diffusion barrier to open a top surface of the polysilicon layer, and forming a diffusion barrier pattern to block the side surface of the polysilicon layer, and preventing diffusion including the surface of the opened polysilicon layer. Forming a metal film on the surface of the pattern, and diffusing the metal of the metal film into the polysilicon film to form a metal silicide film.

Description

Semiconductor device and method for manufacturing same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device capable of uniformly forming a metal silicide film and a method for manufacturing the same.

The semiconductor device includes gate patterns. Referring to the flash device as an example, the flash device includes gate patterns in which a conductive film for a floating gate, a dielectric film, and a conductive film for a control gate are stacked. The floating gate conductive film and the control gate conductive film included in the memory cell storing a plurality of data are formed with a dielectric film interposed therebetween, and the floating gate conductive film and the control gate conductive film included in the select transistor transferring the driving voltage. The films are connected to each other through contact holes formed in the dielectric film. In addition, the control gate conductive film is formed in a line shape to electrically connect a plurality of memory cells or select transistors. The conductive film for the control gate electrically connecting the memory cells is a word line, and the conductive film for the control gate connecting the select transistor is a select line.

As described above, the gate pattern is minutely formed according to high integration of the semiconductor device. Accordingly, in order to lower the resistance of the gate pattern, a method of introducing a metal silicide film having a low resistance in the gate pattern has been proposed. For example, the control gate conductive film of the gate pattern may be formed of a cobalt silicide film CoSix. Hereinafter, a method of forming a gate pattern including a cobalt silicide layer will be described in detail.

First, a gate insulating film, a floating gate conductive film, a dielectric film, and a control gate polysilicon film are laminated on a semiconductor substrate, and then a gate hard mask pattern is formed on the polysilicon film. The gate hard mask pattern is used as an etching barrier to etch the polysilicon film for the control gate, the dielectric film, and the conductive film for the floating gate to form a plurality of stacked patterns, thereby removing the hard mask pattern. In this case, the stacked pattern may be formed at different densities for each region. Due to the density difference of the stacked patterns, the etching process may not be uniformly performed for each region, and finally, the stacked patterns may be formed at different heights for each region. In particular, a step may occur between the stacked pattern in the cell array region of the semiconductor substrate on which the memory cell and the select transistor are to be formed and the stacked pattern in the peripheral region of the semiconductor substrate on which the low voltage or high voltage transistors constituting the driving circuit will be formed. . As such, an insulating film is formed on the semiconductor substrate including the stacked patterns having the steps. Subsequently, a chemical mechanical polishing (hereinafter referred to as "CMP") process is performed to planarize the upper portion of the insulating film. The CMP process is stopped in the polysilicon film formed on the uppermost layer of the laminated pattern. At this time, since the polysilicon film having a relatively high stacked pattern may not be exposed, the insulating film is additionally etched to lower the height of the insulating film between the stacked patterns. As a result, the entire polysilicon film is exposed, and not only the top surface but also the side surface of the polysilicon film is exposed by the additional etching of the insulating film. Thereafter, a cobalt film is formed on the exposed surface of the polysilicon film and the surface of the insulating film, followed by annealing to diffuse cobalt into the polysilicon to form a cobalt silicide film. Cobalt diffuses into the polysilicon film through the top and side surfaces of the polysilicon film. At this time, it is difficult to constantly control the diffusion of cobalt diffused through the side of the polysilicon film, so that the degree of diffusion of the cobalt varies for each part of the polysilicon film. Therefore, it is difficult to form a cobalt silicide film with a uniform thickness, and the content of cobalt contained in the cobalt silicide film is different for each part. After the cobalt silicide film is formed, the cobalt film remaining without reacting with the polysilicon is removed by an etching process. At this time, a portion of the cobalt silicide film having a high cobalt content may be removed at the same time. As a result, a necking phenomenon occurs in which a cobalt silicide film that is finally left is not formed in a uniform width and a portion having a large cobalt content is excessively etched to form a narrow one. As a result, the cobalt silicide layer is not uniformly formed for each gate pattern, and thus the resistance value is changed for each gate pattern, thereby degrading the threshold voltage distribution characteristic. In addition, cobalt diffused through the sidewall of the polysilicon film may penetrate into the dielectric film and degrade data retention characteristics of the semiconductor device.

The present invention provides a semiconductor device capable of uniformly forming a metal silicide film and a method of manufacturing the same.

In an embodiment, a semiconductor device may include gate patterns formed by stacking a polysilicon layer and a metal silicide layer on an upper surface of a semiconductor substrate, an insulating layer formed between gate patterns and lower than the gate patterns, and a gate pattern protruding from the insulating layer. And a diffusion barrier pattern formed on the sidewalls.

In an embodiment, a semiconductor device may include gate patterns formed by stacking a polysilicon layer and a metal silicide layer on an upper surface of a semiconductor substrate, an insulating layer formed between gate patterns and lower than the gate patterns, and protruding from the insulating layer. And a diffusion barrier pattern formed in a “U” shape along sidewalls of the gate patterns and an upper surface of the insulating layer.

A method of manufacturing a semiconductor device according to the present invention comprises the steps of forming a stacked pattern comprising a polysilicon film on the semiconductor substrate, forming an insulating film having a lower height than the laminated pattern between the stacked pattern, the surface of the stacked pattern and the insulating film Forming a diffusion barrier along the surface of the substrate; patterning the diffusion barrier to open the top surface of the polysilicon layer; and forming a diffusion barrier pattern to block the sides of the polysilicon layer; Forming a metal film on the surface, and diffusing a metal of the metal film into the polysilicon film to form a metal silicide film.

The stacked pattern further includes a floating gate conductive film, a dielectric film, and a gate insulating film stacked under the polysilicon film.

The forming of the insulating film may include forming a spacer on sidewalls of the stacked pattern, forming an etch stop layer on the surface of the spacer including the surface of the stacked pattern, and forming an interlayer insulating film to completely fill the space between the stacked patterns. Performing a chemical mechanical polishing process until the polysilicon layer of the stacked pattern is exposed, and etching the spacer, the etch stop layer and the interlayer insulating layer so that the heights of the spacer, the etch stop layer and the interlayer insulating layer are lower than those of the polysilicon layer. It includes.

In the forming of the diffusion barrier pattern, an etch back process is performed to remove the diffusion barrier layer formed on the top surface of the insulating layer as well as the top surface of the insulating layer, thereby leaving the diffusion barrier pattern on the sidewall of the polysilicon layer.

The diffusion barrier includes at least one of an oxide film and a nitride film.

In the step of forming the diffusion barrier pattern, a chemical mechanical polishing process is performed to leave the diffusion barrier pattern in a “U” shape along the sidewall of the polysilicon and the top surface of the insulating layer.

After the forming of the metal film, the method may further include forming an antioxidant film on the metal film.

The metal film contains cobalt.

After the forming of the metal film, the method may further include forming an oxide film in which titanium and a titanium nitride film are stacked on the metal film.

Forming the metal silicide film may include performing a primary annealing to react the metal film with the polysilicon film to form a CoSi film, removing the remaining metal film and the antioxidant film, and performing a second annealing at a temperature higher than the first annealing. Performing a phase change of CoSi to CoSi2.

The present invention can prevent the metal from diffusing to the side of the polysilicon film when the annealing process is performed after forming the metal film in a subsequent process by blocking the side of the polysilicon film with the diffusion prevention pattern. That is, the present invention can uniformly control the diffusion thickness by restricting the diffusion of the metal from the upper surface of the polysilicon film to its lower direction. Accordingly, the present invention can uniformly form the metal silicide film, so that the resistance value can be uniform for each gate pattern.

In addition, the present invention can improve the reliability of the semiconductor device by preventing the metal from diffusing through the side of the polysilicon film to improve the phenomenon that the metal penetrates into the dielectric film.

In addition, the present invention can uniformly control the diffusion direction of the metal to equalize the content of the metal contained in the metal silicide film, so that the portion of the metal silicide film is etched through the subsequent etching process due to the high metal content. The necking phenomenon in which the part is narrowly formed can be prevented from occurring.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

1A to 1H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention. Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described using a flash device as an example.

Referring to FIG. 1A, a semiconductor in which a laminated pattern 111 and a junction region 101a in which a first conductive film 105 for a floating gate, a dielectric film 107, and a second conductive film 109 for a control gate are stacked are formed is stacked. The first interlayer insulating layer 119 is formed on the substrate 100.

Specifically, a gate insulating film 103, a floating conductive first conductive film 105, and a dielectric are formed on a semiconductor substrate 101 on which a well is formed and a threshold voltage ion implantation process is performed. A film 107 and a second conductive film 109 for control gate are laminated. The gate insulating film 103 may be formed of an oxide film. The first conductive film 105 may be formed of a polysilicon film. The dielectric film 107 can be formed by stacking an oxide film, a nitride film, and an oxide film. After the dielectric film 107 is formed, a contact hole exposing the first conductive film 105 is exposed in the select line (SSL, DSL) and the dielectric film 107 on the transistor (not shown) region of the peripheral region. 108). The contact hole 108 may be a hole for electrically connecting the second conductive layer 109 and the first conductive layer 105 formed in a subsequent process. The second conductive film 109 is formed of a polysilicon film.

Although not shown in the cross section of the drawing, an isolation layer (not shown) is formed on the semiconductor substrate 100. For example, the device isolation layer (not shown) may be formed by forming a trench in the semiconductor substrate 100 and then filling an oxide film in the trench. After forming the first conductive layer 105, the trench forms an element isolation hard mask pattern on the first conductive layer 105 to form the element isolation hard mask pattern as an etch barrier to form the first conductive layer 105 and the gate insulating layer. It can be formed by etching the 103 and the semiconductor substrate 100. The device isolation hard mask pattern is removed after the device isolation layer is formed. In this case, the dielectric film 107 and the second conductive film 109 are formed on the device isolation film including the patterned first conductive film 105.

Subsequently, a gate hard mask pattern (not shown) is stacked on the second conductive film 109. A plurality of stacked patterns separated by lines by etching the second conductive layer 109, the dielectric layer 107, and the first conductive layer 105 until the gate insulating layer 103 is exposed as the gate hard mask pattern as an etching barrier. 111 can be formed. Subsequently, an ion implantation process is performed to form the junction region 101a in the semiconductor substrate 100 on both sides of the stacked pattern 111 using the stacked pattern 111 as a mask. The gate hard mask pattern (not shown) may be removed after the stacked pattern 111 is formed. Thereafter, a spacer 113 that protects the sidewalls of the stacked pattern 111 may be further formed on the sidewalls of the stacked pattern 111. At this time, the space between the stacked patterns 111 of the region where the word line WL is to be formed is smaller than the space between the stacked patterns 111 of the region where the select lines SSL and DSL are to be formed. The space between the stacked patterns 111 in the region where the WL is to be formed may be filled by the spacer 113. The spacer 113 may be formed of an insulating film such as an oxide film. Impurity ions may be implanted into the surface of the junction region 101a exposed between the spacers 113 in order to improve resistance in forming a contact plug in a subsequent process. Subsequently, an etch stop layer 117 may be further formed on an upper surface of the semiconductor substrate 100 including the surfaces of the spacers 113 and the stack pattern 111 with an insulator such as a self align contact (SAC) nitride layer. Before forming the etch stop layer 117, the buffer layer 115 may be further formed on the semiconductor substrate 100 including the spacer 113 and the stack pattern 111 by using an insulating material such as an oxide layer. Thereafter, the first interlayer insulating layer 119 having a sufficient thickness is formed so that all remaining spaces between the stacked patterns 111 may be filled. The first interlayer insulating layer 119 may be formed using an HDP (High Density Plasma) oxide film.

Referring to FIG. 1B, a planarization process is performed to planarize the surface of the first interlayer insulating layer 119. The planarization process may be performed by a chemical mechanical polishing (hereinafter, referred to as "CMP") process and stops when the second conductive film 109 is exposed. That is, the second conductive film 109 formed of the polysilicon film serves as a stop film of the planarization process.

Referring to FIG. 1C, even after the CMP process described above with reference to FIG. 1B, a portion where the second conductive layer 109 is not exposed may occur due to the step difference of the layered pattern 111. The first interlayer insulating layer 119 is further etched to expose 109. An additional etching process of the first interlayer insulating layer 119 may be performed by an etch back method. As a further etching process of the first interlayer insulating layer 119, not only the first interlayer insulating layer 119 but also the spacer 113, the buffer layer 115, and the etch stop layer 117 may be etched together. As a result, the first interlayer insulating layer 119, the spacer 113, the buffer layer 115, and the etch stop layer 117 remain in the space between the stacked patterns 111 at a height lower than that of the stacked patterns 111. That is, the second conductive layer 109 protrudes and is exposed to a predetermined height than the first interlayer insulating layer 119, the spacer 113, the buffer layer 115, and the etch stop layer 117.

Referring to FIG. 1D, a diffusion barrier layer is formed on surfaces of the first interlayer insulating layer 119 including the exposed second conductive layer 109, the spacer 113, the buffer layer 115, and the etch stop layer 117. (121) is formed. The diffusion barrier 121 is formed to prevent the metal from diffusing through the sidewall of the second conductive layer 109 during the subsequent annealing process, and is formed using at least one of a nitride layer and an oxide layer that do not react with the metal. It is desirable to. The diffusion barrier 121 may be formed by a low pressure chemical vapor deposition (LP-CVD) or a plasma enhanced chemical vapor deposition (PE-CVD) method. In addition, the diffusion barrier 121 is preferably formed to a thickness of 10 ~ 200Å.

Referring to FIG. 1E, the diffusion barrier layer 121 illustrated in FIG. 1D is etched by an etch back method to leave the diffusion barrier pattern 121a on the sidewall of the second conductive layer 109. In the exemplary embodiment of the present invention, the diffusion barrier pattern 121a remains only on the sidewalls of the second conductive layer 109, so that the top surface of the second conductive layer 109, the spacer 113, the etch stop layer 115, and the buffer are formed. The top surface of the film 117 and the first interlayer insulating film 119 is exposed.

Referring to FIG. 1F, a metal layer may be formed along the surfaces of the diffusion barrier pattern 121a including the upper surface of the second conductive layer 109, the spacer 113, the buffer layer 115, and the etch stop layer 117. 123 is formed, and an anti-oxidation film 125 is formed on the metal film 123.

The metal layer 123 may be formed of cobalt (Co) to react with the second conductive layer 109 to form a metal silicide layer in a subsequent annealing process. The anti-oxidation film 125 is formed to prevent the metal film 123 from oxidizing during the subsequent annealing process, and may be formed as a stacked structure of titanium (Ti) and titanium nitride (TiN).

Referring to FIG. 1G, the metal silicide layer 127 is formed on the second conductive layer 109. The metal silicide film 127 is formed by diffusing a metal from the metal film 123 shown in FIG. 1F into the second conductive film 109. The diffusion of the metal is performed through an annealing process such as a rapid temperature process (RTP). The annealing process is carried out stepwise into primary and secondary. Hereinafter, a process of forming the metal silicide film 127 will be described in detail by taking the case where the metal film 123 illustrated in FIG. 1F is formed of a cobalt film.

First, when the metal film 123 of FIG. 1F is formed, cobalt is diffused from the metal film 123 of FIG. 1F into the second conductive film 109 so that a Co 2 Si phase is formed on the second conductive film 109. Subsequently, when the first annealing is performed at a temperature of 500 ° C. or lower, cobalt from Co 2 Si diffuses into the second conductive film 109 to phase change into CoSi. Here, the specific resistance of Co 2 Si is 70 µPa · cm, and the specific resistance of CoSi is 100 µµ · cm to 150 µµ · cm. In addition, cobalt from the metal film 123 of FIG. 1F is not diffused in the lateral direction of the second conductive film 109 by the diffusion prevention pattern 121a. Accordingly, the present invention can limit the diffusion direction of cobalt from the upper surface of the second conductive film 109 to the downward direction, so that the degree of diffusion can be controlled uniformly.

After the primary annealing, the metal film (123 in FIG. 1F) and the antioxidant film (125 in FIG. 1F) remaining without reaction are removed by an etching process. Thereafter, when secondary annealing is performed at a temperature of 500 ° C. or more, CoSi is phase-changed into CoSi 2 . At this time, the specific resistance of CoSi 2 is 14 μm · cm to 17 μm · cm. As a result, a gate pattern 129 including a first conductive film 105, a dielectric film 107, a second conductive film 109, and a metal silicide film 127 in a CoSi 2 state is formed.

Referring to FIG. 1H, after the gate pattern 129 is formed, a second interlayer insulating layer 131 is formed to insulate the gate pattern 129.

As described above, the semiconductor device may include at least one insulating layer (spacer 113 and buffer layer) filling the space between the gate pattern 129 and the gate pattern 129 at a height lower than that of the gate pattern 129. 115, at least one of the etch stop layer 117, and the first interlayer insulating layer 119), and the diffusion barrier pattern 121a formed on sidewalls of the gate pattern 129 protruding above the insulating layer. In addition, in the embodiment of the present invention, when forming the metal silicide layer 127 included in the gate pattern 129, the diffusion direction of the metal is changed from the upper surface of the second conductive layer 109 through the diffusion barrier pattern 121a. Since the diffusion thickness can be made uniform by controlling downward, the metal silicide film 127 can be formed uniformly. In addition, since the diffusion prevention pattern 121a may prevent the metal from being diffused through the sidewall of the second conductive layer 109, the diffusion of the metal may be excessive to prevent the diffusion of the metal into the dielectric layer 107.

2 is a cross-sectional view illustrating a method of manufacturing a semiconductor device in accordance with another embodiment of the present invention. In another embodiment of the present invention, the remaining diffusion pattern is different from the embodiment shown in FIGS. 1A to 1H, but other components are the same, and thus the same description is omitted.

Referring to FIG. 2, in another embodiment of the present invention, the gate insulating film 203 is formed on the semiconductor substrate 200 in the same manner as described above with reference to FIGS. 1A to 1D, and the floating gate is formed on the gate insulating film 203. A lamination pattern is formed in which the first conductive film 205, the dielectric film 207, and the second conductive film 209 for the control gate are stacked. Thereafter, the junction region 201a is formed in the semiconductor substrate 200 on both sides of the stacked pattern. Subsequently, a spacer 213 is formed on sidewalls of the stacked pattern, and a buffer layer 215 and an etch stop layer 217 are formed on surfaces of the stacked pattern and the spacer 213. Thereafter, the surface of the first interlayer insulating film 219 is planarized, and the first interlayer insulating film 219, the spacer 213, the buffer film 215, and the etch stop film 217 are further etched to form a second conductive film ( 209). Subsequently, a diffusion barrier is formed. The specific forming method for each component is the same as in FIGS. 1A-1D. In another embodiment of the present invention, the diffusion barrier is polished by a CMP process. The CMP process is stopped when the second conductive film 209 is exposed, so that the sidewalls of the second conductive film 209, the first interlayer insulating film 219, the etch stop film 217, the buffer film 215, A diffusion prevention pattern 221a having a “U” shape is left along the surface of the spacer 213. Subsequently, a metal film is formed in the same manner as described above with reference to FIGS. 1F to 1H, and then an annealing process is performed to form a metal silicide film such that the metal from the metal film can be diffused into the second conductive film 209. Proceed with the process. During the annealing process for forming the metal silicide layer, the diffusion prevention pattern 221a according to another embodiment of the present invention may prevent the metal from diffusing to the sidewall of the second conductive layer 209. Accordingly, in another embodiment of the present invention, the metal silicide film may be uniformly formed, and the metal may be prevented from penetrating into the dielectric film 207.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1A to 1H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

2 is a cross-sectional view illustrating a method of manufacturing a semiconductor device in accordance with another embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100, 200: semiconductor substrate 103, 203: gate insulating film

105, 205: conductive film for floating gate 107, 207: dielectric film

109, 209 polysilicon film 111 laminated pattern

113, 213: spacer 115, 215: buffer film

117, 217: etch stop film 119, 219: first interlayer insulating film

121, 221: diffusion barrier 121a, 221a: diffusion barrier

123: metal film 125: oxide film

127 and 217 metal silicide films 129 and 219 gate pattern

131 and 231: second interlayer insulating film

Claims (16)

Gate patterns formed by stacking a polysilicon layer and a metal silicide layer on the semiconductor substrate; An insulating layer formed between the gate patterns and lower than the gate patterns; And And a diffusion barrier pattern formed on sidewalls of the gate patterns protruding from the insulating layer. Gate patterns formed by stacking a polysilicon layer and a metal silicide layer on the semiconductor substrate; An insulating layer formed between the gate patterns and lower than the gate patterns; And And a diffusion barrier pattern formed in a “U” shape along a sidewall of the gate patterns protruding from the insulating layer and along an upper surface of the insulating layer. The method according to claim 1 or 2, The diffusion preventing pattern includes at least one of an oxide film and a nitride film. The method according to claim 1 or 2, The metal silicide layer includes CoSi 2. The method according to claim 1 or 2, The gate pattern further includes a floating gate conductive layer, a dielectric layer, and a gate insulating layer stacked under the polysilicon layer. The method according to claim 1 or 2, The insulating layer may include at least one of a spacer formed on a sidewall of the gate pattern, an etch stop layer formed on a surface of the spacer, and an interlayer insulating layer formed on a surface of the etch stop layer. Forming stacked patterns including a polysilicon layer on the semiconductor substrate; Forming an insulating film having a lower height than the stacked pattern between the stacked patterns; Forming a diffusion barrier along the surface of the stacked pattern and the surface of the insulating layer; Patterning the diffusion barrier layer to form a diffusion barrier pattern that opens an upper surface of the polysilicon layer and blocks a side surface of the polysilicon layer; Forming a metal film on a surface of the diffusion barrier pattern including a surface of the polysilicon film that is opened; And Diffusing a metal of the metal film into the polysilicon film to form a metal silicide film. The method of claim 7, wherein The stacking pattern may further include a floating gate conductive film, a dielectric film, and a gate insulating film stacked under the polysilicon film. The method of claim 7, wherein Forming the insulating film Forming a spacer on sidewalls of the stacked pattern; Forming an etch stop layer on a surface of the spacer including the surface of the stacked pattern; Forming an interlayer insulating film so that the space between the stacked patterns is completely filled; Performing a chemical mechanical polishing process until the polysilicon film of the lamination pattern is exposed; And And etching the spacer, the etch stop layer and the interlayer insulating layer so that heights of the spacer, the etch stop layer and the interlayer insulating layer are lower than those of the polysilicon layer. The method of claim 7, wherein In the forming of the diffusion barrier pattern, an etch back process may be performed to remove the diffusion barrier layer formed on the top surface of the insulating layer as well as the top surface of the stack pattern, thereby leaving the diffusion barrier pattern on the sidewall of the polysilicon layer. Method of preparation. The method of claim 7, wherein The diffusion barrier layer comprises at least one of an oxide film and a nitride film. The method of claim 7, wherein And forming a diffusion barrier pattern in the form of a “U” along a sidewall of polysilicon and an upper surface of the insulating layer by performing a chemical mechanical polishing process. The method of claim 7, wherein After forming the metal film, And forming an anti-oxidation film on the metal film. The method of claim 7, wherein The metal film manufacturing method of a semiconductor device containing cobalt. The method of claim 14, After forming the metal film, A method of manufacturing a semiconductor device further comprising forming an anti-oxidation film in which titanium and a titanium nitride film are stacked on the metal film. The method of claim 15, Forming the metal silicide film Performing a primary annealing to react the metal film with the polysilicon film to form a CoSi film; Removing the remaining metal film and the antioxidant film; And And performing a second annealing at a higher temperature than the first annealing to change the CoSi into CoSi2.
KR1020080075742A 2008-08-01 2008-08-01 Semiconductor device and forming method of the same KR20100013978A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020080075742A KR20100013978A (en) 2008-08-01 2008-08-01 Semiconductor device and forming method of the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020080075742A KR20100013978A (en) 2008-08-01 2008-08-01 Semiconductor device and forming method of the same

Publications (1)

Publication Number Publication Date
KR20100013978A true KR20100013978A (en) 2010-02-10

Family

ID=42087900

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020080075742A KR20100013978A (en) 2008-08-01 2008-08-01 Semiconductor device and forming method of the same

Country Status (1)

Country Link
KR (1) KR20100013978A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170017312A (en) * 2015-08-06 2017-02-15 삼성전자주식회사 Method for fabricating semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170017312A (en) * 2015-08-06 2017-02-15 삼성전자주식회사 Method for fabricating semiconductor device

Similar Documents

Publication Publication Date Title
KR101096976B1 (en) Semiconductor device and method of fabricating the same
CN110223982B (en) Dynamic random access memory and manufacturing method thereof
US8309412B2 (en) Method for forming semiconductor device with buried gate structure
JP2006286720A (en) Semiconductor device and its manufacturing method
JP5813447B2 (en) Nand flash memory device and manufacturing method thereof
KR20090107346A (en) Vertical pillar transistor, DRAM device including the same, method for forming the vertical pillar transistor and method for forming a semiconductor layer
US20070128805A1 (en) Semiconductor memory device and method for fabricating the same
US8012849B2 (en) Semiconductor device and manufacturing method thereof
US20160013128A1 (en) Semiconductor device and manufacturing method thereof
US7851290B2 (en) Method of fabricating semiconductor device
US8207560B2 (en) Nonvolatile semiconductor memory device and method of fabricating the same
KR100830591B1 (en) Methods of forming a semiconductor device including openings
KR100807517B1 (en) Method of forming contact of semicontactor memory device
KR20080045960A (en) Method for fabricating landing plug in semiconductor device
KR20100013978A (en) Semiconductor device and forming method of the same
KR101034407B1 (en) Nonvolatile memory device and manufacturing method of the same
KR20080002480A (en) Method of manufacturing semiconductor device
KR20100074675A (en) Manufacturing method of gate patterns for semiconductor device
KR20110109725A (en) Bit line in semiconductor device and method for fabricating the same
KR20100012483A (en) Method of forming a semiconductor device
KR101004693B1 (en) Ferroelectric random access memory and method for manufacturing the same
US9269583B1 (en) Method for fabricating memory device
KR100976673B1 (en) Flash memory device and Manufacturing method thereof
JP2009231318A (en) Semiconductor device and method of manufacturing the same
KR20100135460A (en) Manufacturing method of contact structure in semiconductor device

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination