KR20100013936A - Flash memory device, operating method and manufacturing method thereof - Google Patents

Abstract

PURPOSE: A flash memory device, an operation and a manufacturing method thereof are provided to increase an integration degree and a data storage space in same area by forming a first memory cells turned down in the upper part in a substrate and a second memory cells corresponding to a first memory cells. CONSTITUTION: An inter-layer insulating layer(ILD1) is formed on a semiconductor substrate(SUB), and comprises trenches formed to a first direction. A first memory cells are formed within the trench. A first control gate(CG) of the first memory cells locates at the lower part of a first dielectric film. A first floating gate(FG) is located on surface of the first dielectric film. A silicon layer(USUB) is formed on the semiconductor substrate including the first memory cells. A junction area(S,D) is formed in the silicon layer between first memory cells. A second memory cells are formed on the silicon layer of the domain in which first memory cells are formed.

Description

Flash memory device, operating method and manufacturing method thereof Flash memory device, operating method and manufacturing method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory device, an operation method thereof, and a manufacturing method thereof, and more particularly, to a flash memory device having a structure in which two memory cells are stacked, an operation method thereof, and a manufacturing method thereof.

The NAND flash memory device is a representative nonvolatile memory device in which stored data is not erased even when power supply is interrupted. NAND flash memory devices have better integration than Noah flash memory devices, and the difference in operating speed with NOR flash memory devices is decreasing. However, there is a limit to increasing the degree of integration. For this reason, multi-level chip (MLC) devices that store two bits of data in one memory cell have been developed. Since MLC devices increase data storage capacity, it is impossible to increase physical density.

In order to increase the data storage capacity of the NAND flash memory device, it is essential to increase the physical density.

The present invention provides a flash memory device capable of doubling the physical density by forming two memory cells in a two-layer structure in the same area, an operation method thereof, and a manufacturing method thereof.

The flash memory device according to the first exemplary embodiment of the present invention is formed on a semiconductor substrate, and includes an interlayer insulating film including trenches formed in a first direction, a first conductive film, a first dielectric film, and sequentially stacked in the trenches. A first insulating film, a silicon layer, and a second insulating film sequentially stacked on a semiconductor substrate including a second conductive film and a second conductive film, and a third conductive film and a second dielectric film sequentially stacked on a second insulating film And junction regions formed in the silicon layer between the fourth conductive film and the regions where the third conductive film is formed.

In the above, the first dielectric film may extend between the sidewalls of the second conductive film and the first interlayer insulating film between the first and second conductive films. The second conductive film is preferably divided in the trench and arranged in the first direction. The display device may further include a first isolation layer formed in the trench between the divided second conductive layers. It is preferable that the region where the second conductive film is formed and the region where the third conductive film is formed correspond to each other with the silicon layer interposed therebetween. The fourth conductive film is formed in the first direction in a region corresponding to the region where the first conductive film is formed. The third conductive film may be divided below the fourth conductive film and arranged in the first direction. The silicon layer preferably has a line shape extending from the lower portion of the third conductive film in the second direction crossing the first direction. The display device may further include a second isolation layer formed in the space between the divided third conductive layers and the divided silicon layers.

The flash memory device according to the second embodiment of the present invention is formed on a semiconductor substrate, and includes an interlayer insulating film including trenches formed in a first direction, a trench formed in the trench, and a first control gate disposed below the first dielectric film. First memory cells having a first floating gate on the first dielectric layer, a silicon layer formed on a semiconductor substrate including the first memory cells, junction regions formed in the silicon layer between the first memory cells, and a first Second memory cells formed on the silicon layer of the region where the memory cells are formed.

In the above, the floating gate, the dielectric layer, and the control gate included in the second memory cells are sequentially stacked. The silicon layer is in the form of a line in a second direction crossing the first direction. First and second memory cells formed in the same region of the first and second memory cells share the same junction region and channel region.

A flash memory device according to a third embodiment of the present invention is formed on a semiconductor substrate, an interlayer insulating film including trenches formed in a line shape, and formed in the trenches, respectively, with a control gate under the dielectric film, and a floating gate A plurality of first strings including drain select transistors, memory cells, and source select transistors positioned on the film, a silicon layer formed on the semiconductor substrate including the first strings and including a plurality of junction regions; The plurality of second strings formed on the silicon layer of the region where the strings are formed and the first junction region positioned between the adjacent first strings are electrically connected to each other to form two first strings and two second strings. The second junction region located between the shared bit line and the first strings adjacent to each other And a common source connected to each other to share two first strings and two second strings.

In the above, the memory cells included in the second string are sequentially stacked with a floating gate, a dielectric layer, and a control gate. The silicon layer is in the form of a line in the direction crossing the trench. The first strings are included in different memory cell blocks. The second strings are included in different memory cell blocks. The first string and the second string are included in different memory cell blocks. The first string and the second string positioned in the same region of the first and second strings share the same junction region and channel region.

A flash memory device according to a fourth embodiment of the present invention is formed on a semiconductor substrate, an interlayer insulating film including trenches formed in a line shape, a first memory cell array including first semiconductor elements formed in the trenches; A second layer including a silicon layer formed on a semiconductor substrate including a first memory cell array and including a plurality of junction regions, and second semiconductor elements formed on a silicon layer in a region corresponding to the region in which the first semiconductor elements are formed; Memory cell array.

In the above, the first semiconductor devices have a structure in which the second semiconductor devices are inverted. The junction regions are formed under the silicon layer and are used as junction regions of the first semiconductor elements, and the junction regions of the second semiconductor elements are formed on the silicon layer while being separated from the first junction regions. It may include second bonding regions used as.

A method of operating a flash memory device according to a first embodiment of the present invention includes providing a flash memory device as described in the third embodiment, applying a first voltage to bit lines connected to the first and second strings, And applying a program voltage to selected memory cells among the memory cells included in the first string, applying a second voltage lower than the program voltage to the remaining memory cells, and applying a ground voltage to the memory cells included in the second string. Performing the operation.

In the applying of the first voltage to the bit line, a second voltage is applied to the drain select transistor included in the first string, a ground voltage is applied to the drain select transistor included in the second string, and the first and second It is preferable to apply a ground voltage to the source select transistors included in the string. When programming the selected memory cell, it is preferable to apply the first voltage of the ground level to the bit line, and when not programming the selected memory cell, the first voltage and the second voltage are applied at the same level.

In a method of operating a flash memory device according to a second embodiment of the present invention, a method of operating a flash memory device according to a third embodiment of the present invention may include providing a flash memory device, and selecting a ground voltage to a selected memory cell among memory cells included in the first and second strings. The other memory cells may be configured to perform an erase operation by applying an erase voltage to the well region while maintaining the floating state.

A method of operating a flash memory device according to a third embodiment of the present invention includes providing a flash memory device as claimed in claim 14, and selecting an erase voltage of a negative potential to a selected memory cell among memory cells included in the first and second strings. And applying the erase operation to the other memory cells while maintaining the floating state.

In the above-described second and third embodiments, it is preferable to keep the drain select transistor, the source select transistor, the bit line, and the source line in a floating state during the erase operation.

A method of operating a flash memory device according to a fourth embodiment of the present invention includes providing a flash memory device according to the third embodiment, and applying a first voltage to bit lines connected to the first and second strings. And a ground voltage is applied to selected memory cells among the memory cells included in the first string, a second voltage having a positive potential is applied to the remaining memory cells, and a ground voltage is applied to the memory cells included in the second string. Performing the operation.

In the above, it is preferable that the drain select transistor and the source select transistor included in the first string are turned on by the third voltage during the read operation, and the ground voltage is applied to the drain select transistor and the source select transistor included in the second string. . A fourth voltage may be applied to the negative potential of the memory cells corresponding to the selected memory cells among the memory cells included in the second string.

A method of operating a flash memory device according to a fifth embodiment of the present invention provides a method of operating a flash memory device according to the third embodiment, and program operation of a memory cell included in one of the first and second strings. In operation, the program operation is performed by applying a ground voltage to the drain select transistor, the memory cells, and the source select transistor included in the remaining strings, and erases the memory cells included in one of the first and second strings. Performing an erase operation in a floating state by the drain select transistor, the memory cells, and the source select transistor included in the remaining strings, and the read of the memory cells included in one of the first and second strings. When performing the operation, the drain select transistor, memory cells, and small included in the remaining strings. Performing a read operation by applying a ground voltage to the osselect transistor.

A method of manufacturing a flash memory device according to an embodiment of the present invention includes forming an interlayer insulating film including trenches in a line shape formed in a first direction on a semiconductor substrate, and forming a first conductive film and a first dielectric in the trench. Forming a film and a second conductive film, patterning the second conductive films formed in the trenches to be isolated in a second direction crossing the first direction, and forming an isolation film between the second conductive films; Forming a first insulating film, a silicon layer, a second insulating film, and a third conductive film on a semiconductor substrate including the second conductive film, patterning the third conductive film, the second insulating film, and the silicon layer in a second direction; Forming a second dielectric film and a fourth conductive film on the semiconductor substrate including the third conductive film, and patterning the fourth conductive film, the second dielectric film, and the third conductive film in a first direction.

The method may further include forming a first bonding region in the silicon layer between the third conductive films after the third conductive film is patterned in the first direction.

The method may further include forming a contact plug connected to the first bonding region between the third conductive layers, and forming a metal wire connected to the contact plug.

It is preferable that the region where the patterned third metal film remains corresponds to the region where the patterned second conductive film remains. It is preferable that the region where the first metal film is formed corresponds to the region where the patterned fourth conductive film remains. The first conductive film and the fourth conductive film are made of the same material, and the second conductive film and the third conductive film are formed of the same material. The first conductive film is formed of a laminated structure of a metal film and a polysilicon layer, and the fourth conductive film is formed of a laminated structure of a polysilicon layer and a metal film.

The process of forming the silicon layer may include forming a first silicon layer on the first insulating layer, forming a second junction region in the first silicon layer between the regions where the trench is formed, and the first junction Forming a second silicon layer and a third silicon layer on the first silicon layer including the region, wherein the first junction region is formed in the third silicon layer.

Alternatively, the process of forming the silicon layer may include forming a first silicon layer on the first insulating film, forming a second junction region in the first silicon layer between the regions where the trench is formed, and the first junction Forming a second silicon layer on the first silicon layer including the region, wherein the first junction region may be formed on top of the second silicon layer to be isolated from the second junction region.

According to the present invention, a method of forming first memory cells in an inverted structure on a semiconductor substrate, forming a silicon layer over the entire semiconductor substrate, and then forming second memory cells corresponding to the first memory cells inverted on the silicon layer may be performed. Provided are a flash memory device having a symmetrical structure (mirror structure) and first and second memory cells formed on and under a silicon layer. When the first memory cells above the silicon layer operate, the second memory cells below the silicon layer do not operate. To this end, the first and second memory cells formed above and below the silicon layer of the same region have different conditions. Operating voltages are applied.

As a result, the degree of integration doubles and the data storage capacity doubles in the same area. In particular, since the junction region and the channel region required for the operation of the device are included in the silicon layer between the inverted first memory cells and the second memory cells, the contact hole only needs to be formed up to the silicon layer during the subsequent wiring process. Therefore, the depth of the contact hole can be kept the same as that of the general flash memory device without being deepened twice, so that the difficulty of the subsequent wiring process can be prevented from increasing.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

On the other hand, when a film is described as being "on" another film or semiconductor substrate, the film may exist in direct contact with the other film or semiconductor substrate, or a third film may be interposed therebetween. In the drawings, the thickness or size of each layer is exaggerated for clarity and convenience of explanation. Like numbers refer to like elements on the drawings.

1 is a circuit diagram illustrating a cell array of a flash memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a memory cell array includes a semiconductor device formed of an inverted structure with a first memory cell array (solid line display) including semiconductor devices (eg, drain select transistors, memory cells, and source select transistors) formed in a normal structure. And a second memory cell array (dotted line display) including, for example, a drain select transistor, a memory cell, and a source select transistor. The elements included in the second memory cell array are formed in a form in which the elements included in the first memory cell array are inverted. As a result, the first and second memory cell arrays are formed in a mirror structure, which will be described later.

The first memory cell array includes a plurality of memory cell blocks CB, and each memory cell block CB includes a plurality of strings ST. Each string ST includes a drain select transistor DSTA connected to a bit line BL, a source select transistor SSTA, a drain select transistor DSTA, and a source select transistor SSTA connected to a common source CS. It includes a plurality of memory cells (CA0 to CAn) connected in series between. Gates of the drain select transistors DSTA included in the different strings ST are connected to each other to form the drain select lines DSLA. Gates of the source select transistors SSTA included in the different strings ST are connected to each other to form drain select lines SSLA. Gates of the memory cells CA0 to CAn included in the different strings ST are connected to each other to form word lines WLA0 to WLAn. Operation lines generated for device operation in a voltage generator (not shown) are applied to the respective lines DSLA, WLA0 to WLAn, and SSLA through the first global lines GDSLA, GWLA0 to GWLAn, and GSSLA.

The second memory cell array is formed in the same region and has the same structure as the first memory cell array, and includes the drain select transistor DSTB, the memory cells CB0 to CBn, and the source select transistor SSTB included in the second memory cell array. Is formed in an inverted form. Each of the lines DSLB, WLB0 to WLBn, and SSLB included in the second memory cell array (dotted line display) has operating voltages generated for device operation in a voltage generator (not shown). GWLB0 to GWLBn, GSSLB).

In this case, the block switching unit BS is provided such that the operating voltages are applied only to the selected memory cell block of the selected memory cell array. The block switching unit BS includes global lines GDSLA, GWLA0 to GWLAn, GSSLA, GDSLB, GWLB0 to GWLBn, and GSSLB and lines of the memory cell block DSLA, WLA0 to WLAn, SSLA, DSLB, WLB0 to WLBn, and SSLB. And switching elements SA1 to SAk and SB1 to SBk respectively connected to each other and operating according to the block selection signal BSELA or BSELB. The block selection signals BSELA and BESLB may be generated by a row decoder (not shown).

In the above, the devices DSTA, CA0 to CAn, SSTA, DSTB, CB0 to CBn, and SSTB included in the first and second memory cells share a junction region because they are formed in a symmetrical structure. However, the switching elements SA1 to SAk and SB1 to SBk included in the block switching unit BS are separated from each other and do not share the junction region. The details will be described later.

On the other hand, a second memory cell array (dotted line display) having the same structure as the first memory cell array (solid line display) having the above structure is formed on the semiconductor substrate in the same area. Thereby, two integration degree can be improved. Specifically, it is as follows.

2 is a cross-sectional view illustrating a cell array of a flash memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 2, a silicon layer USUB is formed on the semiconductor substrate SUB, and the channel region CH and the junction regions S, D, and J are formed, and the silicon layer USUB is a first interlayer insulating layer. It is electrically isolated from the semiconductor substrate SUB by IDL1. Here, the semiconductor substrate SUB serves as a support, and the silicon layer USUB serves as a substantial semiconductor substrate on which devices are formed.

The first memory cell array (solid line display) described with reference to FIG. 1 is formed on the silicon layer USUB. Second and third interlayer insulating films IDL2 and IDL3 are formed on the silicon layer USUB, and the common source SL is connected to the junction regions S and D formed in the silicon layer USUB, respectively. And a contact plug such as a bit line contact plug. On the third interlayer insulating layer IDL3, a metal line including bit lines BL connected to the bit line contact plugs is formed. In the case of the contact plug, only the silicon layer USUB is formed, so that even if the memory cells are formed in two layers, the contact plug does not increase in height. Therefore, the difficulty of the contact hole forming process and the conductive film filling process for forming the contact plug does not increase.

Meanwhile, the second memory cell array, which is indicated by a dotted line in FIG. 1, is formed inside the first interlayer insulating layer IDL1 and is isolated from the semiconductor substrate SUB. The second memory cell array is formed in the same structure as the first memory cell array, and is formed in a mirror shape symmetrical with the first memory cell array based on the silicon layer USUB. Specifically, it is as follows.

The second memory cell array may be formed in the trench after forming the trench in the first interlayer insulating layer ILD1. In this case, the drain select transistor, the source select transistor, and the memory cells included in the second memory cell array may have a control gate CG formed under the dielectric layer IGB and float for a symmetrical structure with the first memory cell array. The gate FG is formed on the dielectric film IGB. First and second insulating layers TOXA and TOXb are formed on the upper and lower portions of the silicon layer USUB to serve as tunnel insulating layers.

As the first and second memory cell arrays have a two-layer structure in the same region as the above structure, the junction regions S, in which elements included in the first and second memory cell arrays are formed in the silicon layer USUB, J, D) and the channel region CH are shared. As a result, the bit line BL or the common source SL are electrically connected to the four cell strings STA, STB, STC, and STD at the same time. For example, when a voltage is applied to the bit line BL, the voltage is transferred to the drain D through the bit line contact plug, and the voltage is included in the first memory cell array and is included in different memory cell blocks. The first and third strings STA and STC and the second memory cell array may be simultaneously transferred to the second and fourth strings STB and STD included in different memory cell blocks. The same applies to the common source SL. In particular, the first and second strings STA and STB included in the first and second memory cell arrays are connected together between the bit line BL and the common source CL. Therefore, when a voltage is applied, the memory cells included in the first and second strings STA and STB operate together. In order to prevent this, when the memory cells included in the first string STA operate, the voltage conditions must be changed so that the memory cells included in the second string STB do not operate. For example, the drain select lines DSLA included in the first string STA, the word lines WLA0 to WLAn, and the drain select lines included in the source select lines SSLA and the second string STB. Voltages are applied to the data lines DSLB, the word lines WLB0 to WLBn, and the source select lines SSLB.

Hereinafter, referring to FIGS. 1, 2, and Table 1 below, a memory included in a second memory cell array when a program operation, an erase operation, or a read operation of memory cells included in the first memory cell array is performed. A method of prohibiting program operation, erase operation, or read operation of cells will be described as an example.

program elimination lead  First memory cell array selected WLA Vpgm 0 V (high voltage to Pwell), or negative voltage 0 V unselected WLA Vpass Floating Vread DSLA Vcc Floating Vcc SSLA 0 V Floating Vcc  Second memory cell array selected WLB 0 V Floating 0V or -Vread unselected WLB 0 V Floating 0 V DSLB 0 V Floating 0 V SSLB 0 V Floating 0 V  Common seledted BL 0 V Floating 1V ~ 2V usseledted BL Vcc Floating - SL 0 V Floating 0 V

Program behavior

Conventional operating voltages are applied to the word lines WLA, the drain select line DSLA, and the source select line SSLA of the memory cell block including the selected memory cell during the program operation. Since the memory cells included in the first and second memory cell arrays share the same bit line BL and the source line SL, the same voltage is applied to the first and second memory cell arrays. In this case, in order to prohibit the program operation of the memory cells included in the second memory cell array, the word lines WLB, the drain select line DSLB, and the source select line SSLB included in the second memory cell array are grounded. Apply voltage. The voltage difference approaches 0V between the word line WLB and the channel region CH of the second memory cell array due to the ground voltage. Even though the memory cells included in the first memory cell array are programmed, the second voltage may be reduced by the low voltage difference. Memory cells included in the memory cell array are not programmed.

Typically, in order to prohibit a program during a program operation, a channel boosting phenomenon occurs after precharging the channel region. In this case, when 0 V is applied to the word line WLB to prevent programming in the second memory cell array, even if a voltage difference is generated between the boosted channel region CH and the word line WLB, the program operation time is short. Memory cells to which 0 V is applied to the line WLB are hardly erased.

-Erase operation

In general, OV is applied to the word lines WLA of the memory cell block including the selected memory cell during the erase operation, and the drain select line DSLA and the source select line SSLA maintain a floating state. The bit line BL and the source line SL shared by the first and second memory cell arrays also maintain a floating state. When an erase voltage of 15V to 20V is applied to the well region (318b of FIG. 4), memory cells included in the first memory cell array are erased due to a high voltage difference between the word line WLA and the channel region CH.

In this case, in order to prohibit the erase operation of the memory cells included in the second memory cell array, the word lines WLB, the drain select line DSLB, and the source select line SSLB included in the second memory cell array are floated. Maintain state. In this state, when the erase voltage is applied to the channel region CH, the potentials of the floating lines WLB, DSLB, and SSLB become high due to the capacitor coupling phenomenon, and between the word line WLB and the channel region CH. Since the voltage difference is low, the memory cells included in the second memory cell array are not erased.

Meanwhile, as shown in FIG. 3I, when the well region is not formed, word voltages WLA of the memory cell block including the selected memory cell are erase voltages of negative potential instead of OV (for example, -15V to -20V). You can also apply In general, in order to use a negative voltage, a circuit such as a negative voltage pump must be added, and since the negative voltage pump occupies a large area, the negative voltage is not used. However, when the first and second memory cell arrays are formed in the same region, the integration degree can be doubled, thereby securing an area for forming a negative voltage pump. Therefore, in the present invention, the use of negative voltage is also possible.

Lead operation

Normal operating voltages are applied to the word lines WLA, the drain select line DSLA, and the source select line SSLA of the memory cell block including the selected memory cell during the read operation. Since the memory cells included in the first and second memory cell arrays share the same bit line BL and the source line SL, the same voltage is applied to the first and second memory cell arrays. In this case, the ground voltage is applied to the lines WLB, DSLB, and SSLB included in the second memory cell array so that the memory cells included in the second memory cell array do not affect the read operation.

Meanwhile, the memory cells in the erase state among the memory cells included in the second memory cell array form a channel region because the threshold voltage is low. As a result, if a channel is formed regardless of a program or erase state of the memory cells included in the first memory cell array, an error may occur during the read operation. Therefore, a negative voltage (eg, -Vread) may be applied to the word lines WLB included in the second memory cell array, or a negative voltage may be applied only to the selected word line.

According to the above method, when the program operation, the erase operation, or the read operation are performed, even if the same voltage is applied to the first string STA and the second string STB facing each other through the bit line BL, only the selected string is applied. The program / erase / lead operation is performed and the program / erase / lead operation can be prohibited in the unselected string.

3A to 3I are diagrams for describing a method of manufacturing a flash memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 3A, a first interlayer insulating layer 302 and a first hard mask 304 are formed on the semiconductor substrate 300. The first interlayer insulating film 302 may be formed of an insulating film such as an HDP oxide film, an HTO oxide film, or a TEOS. The hard mask 304 may be formed of a nitride film. Subsequently, the first interlayer insulating layer 302 is etched to form trenches in the first direction. For example, trenches are formed to define regions in which inverted memory cells are to be formed (i.e., regions in which a second memory cell array indicated by dotted lines in FIG. 1 will be formed), and control gates (e.g., , Word lines) are formed parallel to each other (for example, in a direction crossing the bit lines).

The thickness of the first interlayer insulating layer 302 remaining in the lower portion of the trench is preferably controlled to such an extent that an electrical effect applied to the substrate 300 may be minimized during the operation of the memory cell to be formed in the trench.

Referring to FIG. 3B, a first metal layer 306, a first polysilicon layer 308, a first dielectric layer 310, and a second polysilicon layer 312 are sequentially formed in the trenches.

In the above, the first metal layer 306 and the first polysilicon layer 308 become conductive layers for forming the control gate of the inverted memory cells. The metal film 306 includes tungsten, tungsten nitride film or tungsten silicide. The second polysilicon layer 312 becomes a conductive film for forming floating gates of inverted memory cells. As such, in order to form inverted memory cells, the control gate conductive film is formed before the floating gate conductive film. The films are formed in the trenches through a deposition process and a chemical mechanical polishing process.

The first metal layer 306, the first polysilicon layer 308, the first dielectric layer 310, and the second polysilicon layer 312 are formed in the form of lines in the first direction like the trench.

In the above, after the first metal film 306 and the first polysilicon layer 308 are formed, the first metal film 306 and the first polysilicon layer 308 on the upper side of the first interlayer insulating film 302 and the trench sidewalls 308 are formed. ), The first metal layer 306 and the first polysilicon layer 308 may be left only at the bottom of the trench. It is apparent to those skilled in the art that the first metal film 306 and the first polysilicon layer 308 can be formed only on the bottom of the trench by other methods.

Referring to FIG. 3C, the second polysilicon layer 312 is patterned in a second direction crossing the first direction. As a result, the second polysilicon layer 312 is divided into two or more in the trench. For example, the second polysilicon layer 312 is etched to remain only in the region where the flipped memory cells are to be formed. More specifically described as follows.

An etching process using an etching mask (not shown) is performed to etch the second polysilicon layers 308 formed in the respective trenches in the second direction crossing the first direction. In this case, the first interlayer insulating layer 302 between the second polysilicon layers 308 may also be etched. Subsequently, the isolation layer 314 is formed in the space where the second polysilicon layer 308 and the first interlayer insulating layer 302 are etched. The isolation layer 314 is formed of an insulating layer, and serves as an insulating layer spacer formed on both sidewalls of the floating gate in a general flash memory device. In addition, the isolation layer 314 serves to remove the step caused by etching the second polysilicon layer 308 and to planarize the entire surface. As a result, the isolation layer 314 may be formed in a second direction crossing the trench. When the first interlayer insulating layer 302 is not etched and only the second polysilicon layer 308 is etched, the isolation layer 314 is formed only between the second polysilicon layers 308 inside the trench.

Referring to FIG. 3D, the first hard mask 304 is removed and a planarization process is performed. When the first hard mask 304 is formed of a nitride film, it may be removed by phosphoric acid. When the first hard mask 304 is removed, the upper portion of the second polysilicon layer 308 protrudes higher than the first interlayer insulating layer 302, and thus, the protruding portion may be removed so that the entire surface is flattened. Subsequently, to improve the physical / electrical properties of the second polysilicon layer 308, the exposed surface of the second polysilicon layer 308 may be oxidized and then the oxidized portion may be removed.

Subsequently, a first insulating film 316, a silicon layer 318, a second insulating film 320, and a third polysilicon layer 322 are formed on the semiconductor substrate 301 including the second polysilicon layer 308. . The second hard mask 324 is formed on the third polysilicon layer 322.

In the above, the first insulating film 316 becomes a tunnel insulating film of the inverted memory cell. The silicon layer 318 may be formed by a deposition method, and may be formed by a silicon epitaxy growth (SEG) method using a silicon seed or a metal seed. A junction region is formed in the silicon layer 318 in a subsequent process, and the silicon layer 318 serves as an actual semiconductor substrate in which an inverted memory cell and a channel of memory cells to be formed in a subsequent process are formed. Therefore, in order to increase the electron mobility of the channel region and reduce the leakage current, the silicon layer 318 is formed of polysilicon and a nut heat treatment process is performed to adjust the grain size of the silicon layer 318. It is preferable.

The second insulating layer 320 becomes a tunnel insulating layer of memory cells to be formed in a subsequent process.

The third polysilicon layer 322 is a conductive film for forming floating gates of memory cells to be formed on the silicon layer 318.

The second hard mask 324 is formed in the second direction and is formed such that the third polysilicon layer 322 corresponding to the region where the isolation layer 314 is formed is exposed in a line shape. That is, the second hard mask 324 is formed in the direction crossing the word line.

Meanwhile, an ion implantation process for adjusting the threshold voltages of the memory cells may be performed. The ion implantation process is preferably performed before the second insulating film 320 is formed, and the impurity for adjusting the threshold voltage is injected into the silicon layer 318.

Referring to FIG. 3E, the third polysilicon layer 322, the second insulating layer 320, and the silicon layer 318 are patterned by performing an etching process using the second hard mask 324. Here, the silicon layer 318 is etched to electrically isolate memory cells included in different strings. That is, typically, an isolation layer must be formed on a semiconductor substrate. In this case, since the silicon layer 318 serves as a substantial substrate, an isolation layer must also be formed in the silicon layer 318. To this end, the silicon layer 318 is etched, and a second isolation layer (not shown) serving as an isolation layer may be formed in the space between the etched silicon layers 318. As such, since the device isolation region is defined while the third polysilicon layer 322 and the silicon layer 318 are etched together, the self-aligned shallow trench isolation (SA-STI) method is applied.

In the above, it is important to etch the third polysilicon layer 322 so that the region where the third polysilicon layer 322 remains and the region where the second polysilicon layer 312 remains.

Referring to FIG. 3F, the second hard mask 324 is removed. As a result, the upper surface of the third polysilicon layer 322 is exposed. Next, a second dielectric film 326, a fourth polysilicon layer 328, and a second metal film 330 are formed on the semiconductor substrate 300 including the third polysilicon layer 322. The third hard mask 332 is formed on the second metal layer 330.

The fourth polysilicon layer 328 and the second metal layer 330 are conductive layers for forming a control gate of the memory cell. The second metal film 330 may be formed after forming the fourth polysilicon layer 328 and performing a planarization process.

The third hard mask 332 is formed in a first direction crossing the third polysilicon layer 322 and is formed only in a region corresponding to the trench formed in the first interlayer insulating layer 302 in FIG. 3A. This is because the control gates 306 and 308 of the flipped memory cells and the control gates of the memory cells to be formed on the silicon layer 318 are formed in the same region.

Referring to FIG. 3G, the second metal layer 320, the fourth polysilicon layer 328, the second dielectric layer 326, and the third polysilicon layer 322 by an etching process using the third hard mask 332. Etch). As a result, word lines WLAn, drain select lines DSLA, and source select lines (not shown) are formed on the silicon layer 318. By the foregoing processes, word trenches WLAn, drain select lines DSLA, and source select lines (not shown) on the silicon layer 318 may be formed in the trenches of the first interlayer insulating layer 302. The word lines WLBn, the drain select lines DSLB, and the source select lines (not shown) are inverted.

As a result, a first memory cell array and a second memory cell array are formed on the upper and lower portions of the silicon layer 318 in a mirror structure symmetric with each other.

Referring to FIG. 3H, the silicon layer 318 between the word lines WLAn, the drain select lines DSLA, and the source select lines (not shown) form a junction region 334. The junction region 334 between the drain select lines DSLA becomes the drain of the string connected to the bit line, and the junction region 334 between the source select lines (not shown) is the source of the string connected with the common source. Becomes

Referring to FIG. 3I, a planarization process is performed after forming the second interlayer insulating film 336 on the semiconductor substrate 300. Subsequently, although not shown in the drawing, a contact hole exposing the junction region between the source select lines is formed in the second interlayer insulating film 336, and then a common source is formed in the contact hole. Next, after forming the third interlayer insulating film 338, a planarization process is performed. A contact hole exposing the junction region 334 between the drain select lines DSLA is formed in the third interlayer insulating layer 338, and then a contact plug 340 is formed in the contact hole. A plurality of metal wires (eg, bit lines BL) connected to the contact plug 340 are formed on the third interlayer insulating layer 338.

4 is a cross-sectional view for describing a method of manufacturing a flash memory device according to another exemplary embodiment of the present invention.

Referring to FIG. 4, the junction region 334a of the elements included in the first memory cell array and the junction region 334b of the elements included in the second memory cell array may be separated. Specifically, it is as follows.

After the processes described with reference to FIGS. 3A to 3C are performed, the first hard mask 304 is removed and a planarization process is performed. When the first hard mask 304 is formed of a nitride film, it may be removed by phosphoric acid. When the first hard mask 304 is removed, the upper portion of the second polysilicon layer 308 protrudes higher than the first interlayer insulating layer 302, and thus, the protruding portion may be removed so that the entire surface is flattened. Subsequently, to improve the physical / electrical properties of the second polysilicon layer 308, the exposed surface of the second polysilicon layer 308 may be oxidized and then the oxidized portion may be removed.

Next, referring to FIG. 4, the first insulating layer 316 and the silicon layer 318 are formed on the semiconductor substrate 301 including the second polysilicon layer 308. In this case, the silicon layer 318 may be formed in three steps. That is, after forming the first silicon layer 318a on the first insulating layer 316, an ion implantation process is performed to form a junction region 334a in the first silicon layer 318a between the regions where the trench is formed. . Next, a second silicon layer 334b and a third silicon layer 334c are formed on the first silicon layer 334a including the junction region 334.

Subsequently, the second insulating layer 320, the third polysilicon layer 322, and the second hard mask 324 are formed on the silicon layer 318, and the processes described with reference to FIGS. 3D to 3G are performed. Word lines WLAn, drain select lines DSLA, and source select lines (not shown) are formed on the 318. The ion implantation process is performed to form a junction region 334b in the third silicon layer 318c between the word lines WLAn, the drain select lines DSLA, and the source select lines (not shown).

Meanwhile, the third silicon layer 318c may be omitted. For example, the second silicon layer 318b is formed thicker than the first silicon layer 318a, and when the junction region 334b is formed, the ion implantation energy is controlled to bond only to the upper portion of the second silicon layer 318. Area 334b is formed. In this case, even when two silicon layers 318a and 318b are used, the junction regions 334a and 334b can be formed separately. In addition, the silicon layers 318a, 318b, and 318c may be implanted into a silicon layer in which impurities (eg, tetravalent impurities) of opposite types (eg, tetravalent impurities) are implanted into the junction regions 334a and 334b. When formed, the silicon layers 318a, 318b, and 318c in portions where the junction regions 334a and 334b are not formed may be used as well regions (eg, P well regions).

As such, when the junction regions 334a and 334b are separately formed, a contact plug connected to the bit line BL in FIG. 3I should be connected to the upper junction region 334a and the lower junction region 334b, respectively.

1 is a circuit diagram illustrating a cell array of a flash memory device according to an exemplary embodiment of the present invention.

2 is a cross-sectional view illustrating a cell array of a flash memory device according to an exemplary embodiment of the present invention.

3A to 3I are diagrams for describing a method of manufacturing a flash memory device according to an exemplary embodiment of the present invention.

4 is a cross-sectional view for describing a method of manufacturing a flash memory device according to another exemplary embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

300: semiconductor substrate 302, 336, 338: interlayer insulating film

304, 324, 332: hard masks 306, 330: metal film

308, 312, 322, 328: polysilicon layer

310, 326: dielectric film 314: isolation film

316, 320: insulating film 318, 318a, 318b: silicon layer

334, 334a, 334b: junction area 340: contact plug

342: metal wiring

Claims (42)

An interlayer insulating layer formed on the semiconductor substrate and including trenches formed in a first direction; A first conductive film, a first dielectric film, and a second conductive film sequentially stacked in the trenches; A first insulating film, a silicon layer, and a second insulating film that are sequentially stacked on the semiconductor substrate including the second conductive film; A third conductive film, a second dielectric film, and a fourth conductive film sequentially stacked on the second insulating film; And And a junction region formed in the silicon layer between regions where the third conductive layer is formed. The method of claim 1, And the first dielectric layer extends between the sidewalls of the second conductive layer and the first interlayer insulating layer between the first and second conductive layers. The method of claim 1, And the second conductive layer is divided in the trench and arranged in the first direction. The method of claim 3, wherein And a first isolation layer formed in the trench between the divided second conductive layers. The method of claim 1, And a region in which the second conductive film is formed and a region in which the third conductive film is formed correspond to each other with the silicon layer therebetween. The method of claim 1, And a fourth conductive film in a region corresponding to the region where the first conductive film is formed, in the first direction. The method of claim 6, The third conductive film is divided under the fourth conductive film and arranged in the first direction. The method of claim 7, wherein The silicon layer has a line shape extending from the lower portion of the third conductive layer in a second direction crossing the first direction. The method of claim 8, And a second isolation layer formed in the space between the divided third conductive layers and the divided silicon layers. An interlayer insulating layer formed on the semiconductor substrate and including trenches formed in a first direction; First memory cells formed in the trench and having a first control gate under the first dielectric layer and a first floating gate on the first dielectric layer; A silicon layer formed on the semiconductor substrate including the first memory cells; Junction regions formed in the silicon layer between the first memory cells; And And second memory cells formed on the silicon layer in a region where the first memory cells are formed. The method of claim 10, And a floating gate, a dielectric layer, and a control gate included in the second memory cells sequentially stacked. The method of claim 10, The flash memory device of claim 2, wherein the silicon layer has a line shape in a second direction crossing the first direction. The method of claim 10, The first and second memory cells formed in the same region of the first and second memory cells share the same junction region and the channel region. An interlayer insulating layer formed on the semiconductor substrate and including trenches formed in a line shape; A plurality of first strings including drain select transistors, memory cells, and source select transistors respectively formed in the trenches and having a control gate under the dielectric layer and a floating gate over the dielectric layer; A silicon layer formed on the semiconductor substrate including the first strings and including a plurality of junction regions; A plurality of second strings formed on the silicon layer in a region where the first strings are formed; A bit line electrically connected to a first junction region located between the first strings adjacent to each other to share two second strings with two first strings; And And a common source electrically connected to a second junction region located between the first strings adjacent to each other to share the two first strings and the two second strings. The method of claim 14, The memory cells included in the second string may sequentially stack a floating gate, a dielectric layer, and a control gate. The method of claim 14, The flash memory device of claim 1, wherein the silicon layer has a line shape in a direction crossing the trench. The method of claim 14, And the first strings are included in different memory cell blocks. The method of claim 14, And the second strings are included in different memory cell blocks. The method of claim 14, And the first string and the second string are included in different memory cell blocks. The method of claim 14, The flash memory device of claim 1, wherein the first string and the second string positioned in the same region of the first and second strings share the same junction region and channel region. Providing a flash memory device as described in claim 14; Applying a first voltage to bit lines connected to the first and second strings; And A program voltage is applied to selected memory cells among the memory cells included in the first string, a second voltage lower than the program voltage is applied to the remaining memory cells, and a ground voltage is applied to the memory cells included in the second string. And performing a program operation. The method of claim 21, wherein applying the first voltage to the bit line comprises: Applying a second voltage to the drain select transistor included in the first string, applying a ground voltage to the drain select transistor included in the second string, and selecting the source select transistors included in the first and second strings. Method of operating a flash memory device that applies a ground voltage. The method of claim 22, A flash memory device in which the first voltage of a ground level is applied to the bit line when the selected memory cell is programmed, and the first voltage and the second voltage are applied to the same level when the selected memory cell is not programmed. Method of operation. Providing a flash memory device as described in claim 14; And Applying a ground voltage to a selected memory cell among the memory cells included in the first and second strings, and performing an erase operation by applying an erase voltage to a well region while maintaining the floating state. Operating method of a flash memory device. Providing a flash memory device as described in claim 14; And Applying an erase voltage of a negative potential to a selected memory cell among the memory cells included in the first and second strings, and performing an erase operation while maintaining the floating state of the remaining memory cells. Way. The method of claim 24 or 25, And operating the drain select transistor, the source select transistor, the bit line, and the source line in a floating state during the erase operation. Providing a flash memory device as described in claim 14; Applying a first voltage to bit lines connected to the first and second strings; And A ground voltage is applied to selected memory cells among the memory cells included in the first string, a second voltage having a positive potential is applied to the remaining memory cells, and a ground voltage is applied to the memory cells included in the second string. A method of operating a flash memory device comprising performing an operation. The method of claim 27, In the read operation, the drain select transistor and the source select transistor included in the first string are turned on by a third voltage, and the flash memory device to which the ground voltage is applied to the drain select transistor and the source select transistor included in the second string. Method of operation. The method of claim 27, And a fourth voltage is applied to a negative potential of a memory cell corresponding to the selected memory cell among the memory cells included in the second string. Providing a flash memory device as described in claim 14; When performing a program operation of a memory cell included in one of the first and second strings, the program operation may be performed by applying a ground voltage to the drain select transistor, the memory cells, and the source select transistor included in the remaining string. Making; Performing an erase operation in a floating state of the drain select transistor, the memory cells, and the source select transistor included in the remaining string when the erase operation of the memory cell included in one of the first and second strings is performed; ; And When performing a read operation of a memory cell included in one of the first and second strings, the read operation may be performed by applying a ground voltage to the drain select transistor, the memory cells, and the source select transistor included in the remaining string. A method of operating a flash memory device comprising the step. Forming an interlayer insulating film including trenches in a line shape formed in a first direction on the semiconductor substrate; Forming a first conductive layer, a first dielectric layer, and a second conductive layer in the trench; Patterning the second conductive layers formed in the trenches to be isolated in a second direction crossing the first direction; Forming an isolation layer between the second conductive layers; Forming a first insulating film, a silicon layer, a second insulating film, and a third conductive film on the semiconductor substrate including the second conductive film; Patterning the third conductive film, the second insulating film, and the silicon layer in the second direction; Forming a second dielectric film and a fourth conductive film on the semiconductor substrate including the third conductive film; And And patterning the fourth conductive film, the second dielectric film, and the third conductive film in the first direction. The method of claim 31, wherein And forming a first junction region in the silicon layer between the third conductive layers after the third conductive layer is patterned in the first direction. The method of claim 32, Forming a contact plug connected to the first bonding region between the third conductive films; And And forming a metal wire connected to the contact plug. The method of claim 31, wherein And a region where the patterned third metal film remains and a region where the patterned second conductive film remains. The method of claim 31, wherein And a region in which the first metal layer is formed corresponds to a region in which the patterned fourth conductive layer remains. The method of claim 31, wherein And the first conductive film and the fourth conductive film are made of the same material, and the second conductive film and the third conductive film are formed of the same material. The method of claim 31, wherein The first conductive film is formed of a laminated structure of a metal film and a polysilicon layer, and the fourth conductive film is formed of a laminated structure of a polysilicon layer and a metal film. The method of claim 32, wherein the step of forming the silicon layer, Forming a first silicon layer on the first insulating film; Forming a second junction region in the first silicon layer between the trenched regions; And Forming a second silicon layer and a third silicon layer on the first silicon layer including the first junction region, And the first junction region is formed in the third silicon layer. The method of claim 32, wherein the step of forming the silicon layer, Forming a first silicon layer on the first insulating film; Forming a second junction region in the first silicon layer between the trenched regions; And Forming a second silicon layer on the first silicon layer including the first junction region, And the first junction region is formed on the second silicon layer so as to be isolated from the second junction region. An interlayer insulating layer formed on the semiconductor substrate and including trenches formed in a line shape; A first memory cell array including first semiconductor elements formed in the trenches; A silicon layer formed on the semiconductor substrate including the first memory cell array and including a plurality of junction regions; And And a second memory cell array including second semiconductor elements formed on the silicon layer in a region corresponding to the region in which the first semiconductor elements are formed. The method of claim 40, The first semiconductor device has a structure in which the second semiconductor device is inverted. The method of claim 40, The junction region may be formed under the silicon layer to form first junction regions used as junction regions of the first semiconductor devices, and may be formed on the silicon layer while being separated from the first junction regions. A flash memory device comprising second junction regions used as junction regions of semiconductor devices.

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