KR20100008940A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PURPOSE: A semiconductor device and a manufacturing method thereof are provided to minimize the area of a support layer around a capacitor bottom electrode of a capacitor and thereby prevent leaning of the capacitor bottom electrode. CONSTITUTION: A manufacturing method of a semiconductor device comprises the steps of: preparing a semiconductor substrate(100) in which a storage node contact plug is formed, forming a first sacrificial insulating layer on the storage node contact plug, etching a part of the first sacrificial insulating layer using a linear mask pattern, forming a support layer(116) on the protruding part of the first sacrificial insulating layer, forming a second sacrificial insulating layer on the support layer and the first sacrificial insulating layer, etching the second and the first sacrificial insulating layer successively, forming a contact hole exposing the storage node contact plug, forming a conductive layer and a third sacrificial insulating layer successively on the contact hole, the support layer and the first sacrificial insulating layer, filling the contact hole, etching the third sacrificial insulating layer and the conductive layer until the first sacrificial insulating layer is exposed the exposure time, and removing the remaining third and the first sacrificial insulating layer.

Description

Semiconductor device and manufacturing method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device and a method for manufacturing the same, which can prevent leakage of the capacitor lower electrode and at the same time improve the leakage of the capacitor.

A semiconductor device using a capacitor needs to be refreshed. In order to increase the refresh time, it is required to maximize the capacitance, but there is a limit to maximizing the capacitance due to the recent high integration and miniaturization of memory devices. Accordingly, in order to secure the capacitance, the height of the capacitor continues to increase, and the thickness of the capacitor dielectric film becomes thinner. This is because the capacitance is proportional to the electrode area and the dielectric constant of the dielectric film and inversely proportional to the thickness of the dielectric film corresponding to the gap between the electrodes. In reality, however, it is difficult to find a dielectric having a high permittivity without generating leakage current. Therefore, a method of increasing the surface area of an electrode is mainly attempted for a highly integrated semiconductor device.

In general, a cylinder type capacitor having a high aspect ratio is mainly used to increase the surface area of the electrode. Cylindrical capacitors have the advantage that both the inner and outer surfaces of the capacitor lower electrode can be used as the effective surface area of the capacitor, thereby ensuring greater capacitance.

In order to form such a cylindrical capacitor, a wet dip-out process for removing an insulating layer formed between the capacitor lower electrodes is essential. However, when the insulating layer formed between the capacitor lower electrodes is removed by using a wet dip-out process, a problem of leaning of the capacitor lower electrode occurs. In particular, when the aspect ratio of the capacitor is large due to the high integration of the semiconductor device, the tilting phenomenon of the lower electrode of the capacitor is serious.

In order to improve the above-mentioned problem, a recent NFC (Nitride Floating Capacitor) structure has been introduced. This is a method of preventing the inclination of the capacitor lower electrode by tying a plurality of capacitor lower electrodes with a support layer made of a nitride film.

However, since the loss of the lower electrode of the capacitor is caused by NFC etching and the support layer is wrapped around the lower electrode of the capacitor, the dielectric layer is not deposited in the portion where the supporting layer is formed during subsequent deposition of the dielectric film, so that the leakage current of the capacitor ) Is a problem that occurs.

According to the present invention, in forming a cylinder type capacitor having an NFC (Nitride Floating Capacitor) structure, the lower electrode is inclined by forming a line type support layer between capacitor lower electrodes to minimize the area of the support layer around the lower electrode. The present invention provides a semiconductor device and a method of manufacturing the same, which can prevent leaning and improve leakage current of a capacitor.

) 형상으로 형성하는 단계, 제1 희생 절연막의 철부(

)의 측벽에 지지층을 형성하는 단계, 지지층 및 제1 희생 절연막 상에 제2 희생 절연막을 형성하는 단계, 제2 및 제1 희생 절연막을 순차적으로 식각하여 스토리지 노드 콘택 플러그를 노출시키는 콘택홀을 형성하는 단계, 콘택홀, 지지층 및 제1 희생 절연막 상에 도전층 및 제3 희생 절연막을 순차적으로 형성하여 콘택홀을 채우는 단계, 제1 희생 절연막이 노출되는 시점까지 제3 희생 절연막 및 도전층을 평탄화 식각하는 단계 및 잔류된 제3 희생 절연막 및 제1 희생 절연막을 제거하는 단계를 포함한다.According to an embodiment of the present disclosure, a method of manufacturing a semiconductor device may include providing a semiconductor substrate on which a storage node contact plug is formed, forming a first sacrificial insulating layer on the storage node contact plug, and forming a line type mask pattern. 1 A portion of the sacrificial insulating layer is etched to uneven the surface of the first sacrificial insulating layer.

Forming a convex portion of the first sacrificial insulating layer

Forming a support layer on sidewalls of the substrate), forming a second sacrificial insulating film on the support layer and the first sacrificial insulating film, and sequentially etching the second and first sacrificial insulating films to form a contact hole exposing the storage node contact plug. Forming a conductive layer and a third sacrificial insulating layer sequentially on the contact hole, the support layer, and the first sacrificial insulating layer to fill the contact hole; and planarizing the third sacrificial insulating layer and the conductive layer until the first sacrificial insulating layer is exposed. Etching and removing the remaining third sacrificial insulating film and the first sacrificial insulating film.

In the above, the mask pattern is formed in the diagonal direction.

)가 대응되고, 스토리지 노드 콘택 플러그가 형성된 영역 사이에 제1 희생 절연막의 철부(

)가 대응된다.After etching a portion of the first sacrificial insulating layer, recesses of the first sacrificial insulating layer may be formed in a region where the storage node contact plug is formed.

) Corresponds to each other, and a convex portion of the first sacrificial insulating layer is formed between the regions where the storage node contact plug is formed.

) Corresponds.

The first interlayer insulating film is etched to a depth of 700 to 800 으로부터 from the surface of the first interlayer insulating film.

The support layer is formed of a material having an etching selectivity different from that of the first and second sacrificial insulating films.

The support layer is formed of a nitride film.

The support layer formed on the sidewall of the convex portion of the first sacrificial insulating film has a spacer shape of a line type.

Forming the support layer on the sidewall of the convex portion of the first sacrificial insulating film includes forming a support layer along a step of the first sacrificial insulating film including irregularities and etching the support layer by a spacer etching process.

After contact hole formation, the support layer remains on both sides of the contact hole sidewalls.

The remaining third sacrificial insulating film and the first sacrificial insulating film are removed by a wet dip out process.

After the removal of the remaining third sacrificial insulating film and the first sacrificial insulating film, the supporting layer is formed by being connected in an oblique line type along the outer walls of the even-numbered and odd-numbered capacitor lower electrodes.

After removing the remaining third sacrificial insulating film and the first sacrificial insulating film, an empty space is generated between the support layers between the even and odd capacitor lower electrodes.

An etch stop layer is further formed between the first sacrificial insulating layer and the storage node contact plug.

A semiconductor device according to an embodiment of the present disclosure includes a capacitor lower electrode arranged in a matrix form on a semiconductor substrate and a support layer connected in a line type along an outer wall of an upper portion of an even-numbered and odd-numbered capacitor lower electrode.

The support layer is formed in the diagonal direction. The support layer is formed of a nitride film.

The capacitor lower electrode is formed in a cylinder structure.

) 형상으로 형성한 후 그 상부에 단차를 따라 지지층을 형성한 다음 스페이서 식각 공정으로 지지층을 식각하여 희생 절연막의 철부(

)의 양측벽에 라인 타입의 지지층을 잔류시킴으로써, 커패시터 하부 전극의 기울어짐(leaning)을 방지하고, 아울러 후속에서 커패시터 하부 전극 주위의 지지층의 면적을 최소화하여 후속한 유전체막의 증착을 용이하게 하여 커패시터의 누설 전류(leakage)를 개선할 수 있다.In the present invention, when forming a cylinder-type capacitor of a NFC (Nitride Floating Capacitor) structure, the surface of the sacrificial insulating film is uneven using a mask pattern of a line type.

After forming in the shape of a support layer along the step on the upper portion, and then etching the support layer by a spacer etching process to the convex portion of the sacrificial insulating film (

By retaining the line-type support layer on both side walls of the c), it prevents the lowering of the capacitor lower electrode and subsequently minimizes the area of the support layer around the capacitor lower electrode to facilitate deposition of subsequent dielectric films. It is possible to improve the leakage current (leakage) of.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. . The same reference numerals denote the same elements throughout the specification.

1 is a layout diagram of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1, a capacitor lower electrode 128a having a cylinder structure arranged in a matrix form on a semiconductor substrate 100 and an outer wall of an upper portion of an even-numbered and odd-numbered capacitor lower electrode 128a may be formed. The support layer 116 is formed in a diagonal line type. An empty space 132 is formed between the support layers between the even and odd capacitor lower electrodes.

2A to 2I are cross-sectional views illustrating the manufacturing method in a state cut along the line II ′ of FIG. 1, and FIG. 3 is a perspective view illustrating a first mask pattern applied to FIG. 2A. .

2A and 3, a first sacrificial insulating layer 110 is formed on a semiconductor substrate 100 on which an interlayer insulating layer 102 including a storage node contact plug 104 is formed. The storage node contact plugs 104 may be arranged in a matrix form at regular intervals, and may include a conductive material such as polysilicon or metal (eg, tungsten (W)) to penetrate the interlayer insulating layer 102. It can be formed by a conventional method for manufacturing a semiconductor device using. Although not shown, a predetermined structure such as a gate, a landing plug, and a bit line is formed under the storage node contact plug 104 by a conventional method of manufacturing a semiconductor device.

The first sacrificial insulating film 110 may be formed of an oxide film as an insulating film which is removed when the capacitor lower electrode is subsequently formed. Undoped oxides such as doped oxide, high density plasma (HDP), Undoped Silicate Glass (USG), or Tetra Ethyl Ortho Silicate (TEOS), etc. It can be formed as a double layer. The thickness of the first sacrificial insulating layer 110 is formed in consideration of the height of the target capacitor lower electrode.

The buffer insulating layer 106 and the etch stop layer 108 may be further formed under the first sacrificial insulating layer 110. The buffer insulating layer 106 is to reduce stress of the etch stop layer 108 and may be formed of a silicon oxide layer (SiO ₂ ). In addition, the etch stop layer 108 may be used as an etch stopper in a subsequent sacrificial insulating layer removal process around the lower electrode of the capacitor, and may have a different etch selectivity from the first sacrificial insulating layer 110. And a nitride film, for example, a silicon nitride film (Si ₃ N ₄ ), a silicon oxynitride film (SiON), or the like.

Thereafter, a first mask pattern 114 is formed on the first sacrificial insulating layer 110. The first mask pattern 114 is conventionally a hole type, but in an embodiment of the present invention, as shown in FIG. 3, the first mask pattern 114 is formed in a line type in a diagonal direction. The first mask pattern 114 may be formed of a photoresist film. In this case, the first mask pattern 114 may be formed by coating a photoresist on the first sacrificial insulating film 110 and then patterning the photoresist with exposure and development.

Before forming the first mask pattern 114, a first bottom anti-reflective coating layer (BARC) 112 may be further formed on the first sacrificial insulating layer 110 to prevent diffuse reflection in the exposure process.

Referring to FIG. 2B, the first bottom anti-reflection film 112 (in FIG. 2A) and a portion of the first sacrificial insulating layer 110 are sequentially etched using the first mask pattern (114 in FIG. 2A). The etching process may be performed by a dry etch process, and may be etched to a depth of 700 to 800 으로부터 from the surface of the first interlayer insulating layer 110 to prevent cracks due to subsequent thermal. have.

, 오목부(concave)와 돌출부(convex)) 형상을 가진다.Thereafter, the patterned first bottom anti-reflection film (not shown) and the first mask pattern (114 of FIG. 2A) are removed. As a result, the surface of the first sacrificial insulating film 110 is uneven (

, Concave and convex shapes.

Referring to FIG. 2C, the support layer 116 is formed along the step of the first sacrificial insulating layer 110 including irregularities. The support layer 116 is to prevent the leakage and leakage current of the capacitor lower electrode to be formed later. The support layer 116 is formed of a material having a different etching selectivity from the first sacrificial insulating layer 110. It can be formed as a nitride film.

, 돌출부) 측벽에 라인 타입의 스페이서 형태로 지지층(116)이 잔류된다. 이러한 지지층(116)이 커패시터 하부 전극의 기울어짐과 누설 전류를 방지하게 된다.Referring to FIG. 2D, the support layer 116 of FIG. 2C is etched by a conventional spacer etching process. Preferably, the spacer etching process may be performed by an etch back process. As a result, all the horizontal portions of the support layer 116 of FIG. 2C are removed by the spacer etching process, and the vertical portions formed thicker than the horizontal portions remain to form the convex portions of the first sacrificial insulating layer 110.

The support layer 116 remains on the sidewalls of the protrusions in the form of line-type spacers. The support layer 116 prevents the inclination and leakage current of the capacitor lower electrode.

Referring to FIG. 2E, the second sacrificial insulating film 118, the hard mask film 120, and the second bottom anti-reflection film (on the first sacrificial insulating film 110 including the support layer 116 remaining in the form of a line-type spacer) 122) are formed sequentially.

, 돌출부)와 평탄화 되도록 형성할 수 있다.The second sacrificial insulating layer 118 may be formed of a material having the same or similar etching selectivity as that of the first sacrificial insulating layer 110, and may be preferably formed of an oxide layer. After the deposition, the second sacrificial insulating layer 118 may be planarized to form convex portions of the first sacrificial insulating layer 110.

And protrusions) to be planarized.

The hard mask layer 120 may be used as an etching mask when forming a contact hole for forming a subsequent capacitor lower electrode, and may be formed of an amorphous carbon layer. The second bottom anti-reflection film 122 may be omitted.

Thereafter, a second mask pattern 124 is formed on the second bottom anti-reflection film 122. The second mask pattern 124 is to form a contact hole for forming a capacitor lower electrode, and is formed in a hole type. In this case, the hole of the second mask pattern 124 is formed to expose the region where the capacitor lower electrode contact hole is to be formed in a matrix form. The second mask pattern 124 may be formed of a photoresist film. In this case, the second mask pattern 124 may be formed by applying a photoresist on the second bottom anti-reflection film 122 and patterning the photoresist with exposure and development.

Referring to FIG. 2F, a second bottom anti-reflection film (122 in FIG. 2E), a hard mask film (120 in FIG. 2E), over the storage node contact plug 104 using the second mask pattern (124 in FIG. 2E), The second and first sacrificial insulating layers 118 and 110, the etch stop layer 108, and the buffer insulating layer 106 are sequentially etched.

As a result, the capacitor lower electrode contact hole 126 exposing the storage node contact plug 104 is formed. In this case, the support layer 116 remains on both sides of the sidewalls of the capacitor lower electrode contact hole 126 as it is.

In the process of forming the capacitor lower electrode contact hole 126, the second mask pattern 124 of FIG. 2E, the second bottom anti-reflection film 122 of FIG. 2E, and the hard mask film 120 of FIG. 2E are etched together. Can be removed and, if remaining, removed.

Referring to FIG. 2G, the conductive layer 128 is formed on the support layer 116 including the capacitor lower electrode contact hole 126 and the first sacrificial insulating layer 110 to fill a portion of the capacitor lower electrode contact hole 126. do. The conductive layer 128 is used as a capacitor lower electrode, and is formed in a liner shape along the step between the supporting layer 116 including the capacitor lower electrode contact hole 126 and the second sacrificial insulating layer 110. It may be formed of a nitride film (TiN).

Then, a third sacrificial insulating layer 130 is formed on the conductive layer 128 to fill the capacitor lower electrode contact hole 126. The third sacrificial insulating layer 130 is an insulating layer which is removed when the capacitor lower electrode is subsequently formed, and is formed of a material having the same or similar etching selectivity as the first sacrificial insulating layer 110. Preferably, the third sacrificial insulating layer 130 may be formed of an oxide film, and preferably, the third sacrificial insulating layer 130 is formed by a spin on dielectric (SOD) method having good buried characteristics .

Referring to FIG. 2H, the third sacrificial insulating layer 130 and the conductive layer (128 of FIG. 2G) are planarized and etched until the first sacrificial insulating layer 110 is exposed. The planarization etching process may be performed by an etch back process or a chemical mechanical polishing (CMP) process.

Thus, as the conductive layer (128 in FIG. 2G) is separated by the planarization etching process, a cylinder is connected to the storage node contact plug 104 inside the capacitor lower electrode contact hole 126 and surrounds the support layer 116. The capacitor lower electrode 128a of the structure is formed. At this time, the capacitor lower electrode 128a is arranged in a matrix form.

Referring to FIG. 2I, the first sacrificial insulating film 130 (in FIG. 2H) remaining inside the capacitor lower electrode contact hole (126 in FIG. 2H) and the first sacrificial insulating film (110 in FIG. 2H) between the capacitor lower electrode 128a may be used. Remove it. The removal process of the first and third sacrificial insulating films 110 and 130 of FIG. 2H is preferably performed by a wet dip-out process. In this case, the wet dip-out process may be performed using an etch recipe having a higher etch rate ratio with respect to the first and third sacrificial insulating layers 110 and 130 of FIG. 2H than the etch stop layer 108 of FIG. 2H.

In the embodiment of the present invention, since the first and third sacrificial insulating layers 110 and 130 of FIG. 2H are formed of an oxide film, the wet dip-out process may be performed using an HF solution. This wet dip-out process is performed by the surface of the etch stop film (108 in FIG. 2H) due to the different etch rate ratio between the etch stop film (108 in FIG. 2H) and the first and third sacrificial insulating films (110, 130 in FIG. 2H). Etch stops at.

Next, the etch stop film (108 in FIG. 2H) is removed. The etch stop film (108 in FIG. 2H) may be removed using a phosphoric acid (H ₃ PO ₄ ) solution. Meanwhile, in the process of removing the etch stop layer (108 of FIG. 2H), the buffer insulating layer (106 of FIG. 2H) may be etched and removed together, and may be removed by using BOE (Buffered Oxide Etchant) or HF solution. .

As a result, the first and third sacrificial insulating films 110 and 130 of FIG. 2H, the etch stop film 108 and FIG. 2H, and the buffer insulating film 106 of FIG. 2H are removed, so that the inside and the outside of the capacitor lower electrode 128a are removed. Exposed. In this case, the support layer 116 is formed by being connected in a diagonal line type along the outer wall of the upper part of the even-numbered and odd-numbered capacitor lower electrodes 128a. That is, since the support layer 116 is formed to have a floating structure on the upper portion of the capacitor lower electrode 128a, the support layer 116 becomes an empty space 132 between the support layers 116 between the capacitor lower electrodes 128a.

As such, in the wet deep-out process of exposing the capacitor lower electrode 128a, the plurality of capacitor lower electrodes 128a are bundled and fixed by the support layer 116 floating on the upper portion of the capacitor lower electrode 128a. Therefore, the removal of the first and third sacrificial insulating layers 110 and 130 of FIG. 2H may prevent the lowering of the capacitor lower electrode 128a.

Subsequently, although not shown, a dielectric film is formed along the surfaces of the capacitor lower electrode 128a and the interlayer insulating layer 102 exposed on the capacitor lower electrode 128a and the interlayer insulating layer 102 with the inner and outer sides exposed, and the dielectric A capacitor upper electrode (plate electrode) is formed on the film to complete a capacitor having a stacked structure of the capacitor lower electrode 128a, the dielectric film, and the capacitor upper electrode.

In the past, since the support layer was wrapped around the lower electrode of the capacitor in a wide range, there was a problem in that the leakage current of the capacitor was generated because the dielectric film was not deposited in the portion where the support layer was formed during the subsequent deposition of the dielectric film. However, in an embodiment of the present invention, the line type first mask pattern (114 in FIG. 2A) is used to be connected in a diagonal line type along the outer wall of the upper portion of the even-numbered and odd-numbered capacitor lower electrodes 128a. By forming the support layer 116, the area occupied by the support layer 116 around the capacitor lower electrode 128a can be reduced by the area occupied by the empty space 132 between the support layer 116 between the capacitor lower electrodes 128a. Can be. Accordingly, the leakage current of the capacitor can be improved by minimizing the area of the support layer 116 around the capacitor lower electrode 128a to facilitate deposition of subsequent dielectric films.

The present invention is not limited to the above-described embodiments, but may be implemented in various forms, and the above embodiments are intended to complete the disclosure of the present invention and to completely convey the scope of the invention to those skilled in the art. It is provided to inform you. Therefore, the scope of the present invention should be understood by the claims of the present application.

1 is a layout diagram of a semiconductor device according to an embodiment of the present invention.

2A to 2I are cross-sectional views shown in order of process in order to explain the manufacturing method of the state cut along the line II ′ of FIG. 1.

FIG. 3 is a perspective view illustrating a first mask pattern applied to FIG. 2A.

<Explanation of symbols for the main parts of the drawings>

100 semiconductor substrate 102 interlayer insulating film

104: storage node contact plug 106: buffer insulating film

108: etching stop film 110: first sacrificial insulating film

112: first bottom antireflection film 114: first mask pattern

116: support layer 118: second sacrificial insulating film

120: hard mask film 122: second bottom antireflection film

124: second mask pattern 126: capacitor lower electrode contact hole

128: conductive layer 128a: capacitor lower electrode

130: third sacrificial insulating film 132: empty space

Claims (17)

Providing a semiconductor substrate having a storage node contact plug formed thereon; Forming a first sacrificial insulating film on the storage node contact plug; Etching a portion of the first sacrificial insulating layer by using a mask pattern of a line type to form a surface of the first sacrificial insulating layer in an uneven shape; Forming a support layer on sidewalls of the convex portion of the first sacrificial insulating film; Forming a second sacrificial insulating film on the support layer and the first sacrificial insulating film; Sequentially etching the second and first sacrificial insulating layers to form a contact hole exposing the storage node contact plug; Filling the contact hole by sequentially forming a conductive layer and a third sacrificial insulating film on the contact hole, the support layer, and the first sacrificial insulating film; Planarization etching the third sacrificial insulating film and the conductive layer until a time point at which the first sacrificial insulating film is exposed; And Removing the remaining third sacrificial insulating film and the first sacrificial insulating film. The method of claim 1, The mask pattern is a manufacturing method of a semiconductor device formed in an oblique direction. The method of claim 1, After etching a portion of the first sacrificial insulating layer, recesses of the first sacrificial insulating layer correspond to regions where the storage node contact plugs are formed, and convex portions of the first sacrificial insulating layers are formed between regions where the storage node contact plugs are formed. Corresponding method for manufacturing a semiconductor device. The method of claim 1, And the first interlayer insulating film is etched to a depth of 700 to 800 으로부터 from the surface of the first interlayer insulating film. The method of claim 1, The support layer may be formed of a material having an etching selectivity different from that of the first and second sacrificial insulating layers. The method of claim 5, wherein The support layer is a manufacturing method of a semiconductor device formed of a nitride film. The method of claim 1, The support layer formed on sidewalls of the convex portion of the first sacrificial insulating film has a line-type spacer form. The method of claim 1, Forming a support layer on sidewalls of the convex portion of the first sacrificial insulating film, Forming a support layer along a step of the first sacrificial insulating layer including the unevenness; And And etching the support layer by a spacer etching process. The method of claim 1, And after the contact hole is formed, the support layer remains on both sides of the contact hole sidewalls. The method of claim 1, The remaining third sacrificial insulating film and the first sacrificial insulating film is removed by a wet dip out process. The method of claim 1, After removing the remaining third sacrificial insulating film and the first sacrificial insulating film, the support layer is formed in a diagonal line-type along the outer wall of the upper and lower odd-numbered capacitor lower electrode. The method of claim 1, And removing the remaining third sacrificial insulating film and the first sacrificial insulating film, and a void space is generated between the support layers between the even and odd-numbered capacitor lower electrodes. The method of claim 1, And a etch stop layer is further formed between the first sacrificial insulating layer and the storage node contact plug. A capacitor lower electrode arranged in a matrix form on the semiconductor substrate; And And a support layer connected in a line type along an outer wall of an even-numbered and odd-numbered capacitor lower electrode. The method of claim 14, The support layer is a semiconductor device formed in an oblique direction. The method of claim 14, The support layer is a semiconductor device formed of a nitride film. The method of claim 14, The capacitor lower electrode is a semiconductor device formed in a cylinder structure.

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