KR20100005594A - Multi-layer filter - Google Patents

Abstract

PURPOSE: A multi-layer filter is provided to reduce a size of a circuit by performing a design in consideration of parasitic effect of an inductor and a capacitor. CONSTITUTION: A multi-layer filter includes a resonator, upper and lower ground units(20a,20b), an input electrode(21a), and an output electrode(21b). The resonator is formed by stacking a plurality of dielectric sheets and includes an inducer and a capacitor. The upper and lower ground units are positioned on an upper side and a lower side of the resonator. The input electrode and the output electrode are formed on one of the upper and lower ground units. An input signal inputted through the input electrode is outputted to the output electrode through the inducer, the capacitor, and the stub of each dielectric sheet.

Description

Multi-layer Filters {Multi-layer filter}

The present invention relates to a laminated filter.

In the manufacture and application of small insertion filters, it is generally known that the selection of passive components with less frequency dependence is suitable for an ideal filter design.

To this end, structures with less parasitic effects have been in the spotlight. Therefore, a parasitic structure is used to implement an ideal filter, which is composed of a signal conductor and a ground plane spaced more than a certain distance in the configuration of an inductor or a capacitor, or a structure having no ground plane or a defective ground plane. Structures and the like have been proposed.

However, such a design method has a problem that, firstly, it is impossible to design an element that operates ideally in a wideband, and secondly, interference with external circuits, and third, miniaturization of the overall circuit is difficult.

The present invention can achieve a miniaturized structure of the laminated filter, and is a laminated filter capable of exhibiting high performance over a wide band by using parasitic effects according to the laminated structure.

An embodiment of the present invention is formed by stacking a plurality of dielectric sheets, a resonator including an inductor and a capacitor that resonate with each other, a ground part provided on each of the upper and lower parts of the resonator, and the ground part. And an input electrode and an output electrode to be formed.

The ground portion, the input signal through the input electrode flows to the output electrode through the inductor, capacitor, stub of each dielectric sheet.

The inductors are provided in a plurality of dielectric sheets, and the inductors of each sheet are formed to face each other symmetrically from side to side. The inductor is stacked and includes a first conductive pattern spirally formed on the first dielectric sheet and a second conductive pattern spirally formed on the second dielectric sheet.

The first conductive pattern is formed on the first dielectric sheet through the input electrode and the output electrode and via holes, respectively, the input first conductive pattern and the output first conductive pattern and the second conductive pattern are formed on the surface of the second dielectric sheet. An input second lead pattern and an output second lead pattern formed through the via hole are respectively formed with the input electrode and the output electrode.

A third lead pattern having a 'c' pattern is formed on the third dielectric sheet surface, and each end of the third lead pattern is connected to the input second lead pattern and the output second lead pattern through via holes of the second lead pattern sheet, respectively. Is formed.

The capacitors are provided in a plurality of dielectric sheets in an electrode plate shape, the capacitors of each sheet are symmetrically formed up and down, and the shape size of the capacitors is asymmetrically formed left and right.

The capacitor includes a first capacitor electrode formed on the first dielectric sheet and a second capacitor electrode symmetrically formed at a point opposite to the first capacitor electrode on the second dielectric sheet.

The capacitor may be symmetrical with respect to the input and output first capacitor electrodes formed on the surface of the first dielectric sheet and symmetrically with the input and output first lead patterns and with respect to the input and output second lead patterns on the surface of the second dielectric sheet. And an input and an output second capacitor electrode.

The first capacitor electrode is connected to the first lead pattern on the same dielectric sheet surface as the first lead pattern, and the second capacitor electrode is connected to the third lead pattern through a via hole on the second dielectric sheet surface. .

And an input capacitor formed by connecting the input first capacitor electrode and the second input electrode, and an output capacitor formed by connecting the output first capacitor electrode and the output second capacitor electrode.

The apparatus may further include an input capacitor formed symmetrically at a position facing the input inductor and resonating with each other, and an output capacitor formed symmetrically at a position facing the output inductor and resonating with each other.

And a stub for performing impedance matching to the resonator unit. The stub includes a first stub connected to the inside of the first conductor pattern on the first dielectric sheet and a third stub connected to the inside of the third conductor pattern on the third dielectric sheet.

The first stub and the third stub form electrodes to perform impedance matching.

The first stub includes an input first stub and an output first stub, wherein the input first stub is connected to the input first lead pattern to match input impedance, and the output first stub is the output first stub pattern. Is connected to perform output impedance matching.

The present invention not only reduces the size of the laminated filter through the design in consideration of the parasitic effects of the inductor and the capacitor, but may also have a high-performance effect over a wide bandwidth by considering the parasitic effect of the laminated structure.

Hereinafter, the detailed description of the preferred embodiments of the present invention will be described with reference to the accompanying drawings. In the following description of the reference numerals to the components of the drawings it should be noted that the same reference numerals as possible even if displayed on different drawings.

Prior to the description of the present invention, an equivalent circuit of an ideal filter is shown in FIG. 1 and the parasitic effect generated when the filter is actually implemented as a filter will be described.

1 is a general equivalent circuit diagram of a low pass filter (LPF) composed of ideal passive components.

The equivalent circuit of a low pass filter composed of ideal passive elements generally consists of two series resonators 11, 12 and three parallel capacitors 13, 14, 15. The role of the two series resonators 11, 12 lies in suppressing signals of unwanted frequencies. That is, the positions of the resonant frequencies of the two series resonators 11 and 12 are the same as the transmission zero generation positions for frequency blocking, respectively. In addition, the role of the three parallel capacitors 13, 14 and 15 has a purpose for impedance matching.

Conventionally, a method of eliminating parasitic capacitance effects between the ground plane and the signal conductor has been used to implement the ideal devices of FIG. 1. In this way, a structure in which a ground plane does not exist or a method of forming a distance between the ground plane and the signal conductor at a predetermined interval has been widely known. However, such a conventional design method has a problem in that it is impossible to design an element that operates ideally in a wide band, and also, it is difficult to interfere with external circuits, to miniaturize the entire circuit, and the like.

The present invention proposes a method of controlling by using parasitic capacitance effect present in a non-ideal device, and proposes a design structure that achieves ideal operation in a wide band and at the same time miniaturizes a circuit.

To this end, the equivalent circuit of FIG. 1 is re-expressed as parallel as in FIG. 2 of the present invention. In other words, Cpp1, Cpp2, Cpp3 is the same as the parallel capacitor configuration according to the prior art. Ccp1, Ccp2, Ccp3, and Ccp4 represent the parasitic capacitance effects of the series capacitor configuration inside the series resonator. CLp1, CLp2, CLp3, and CLp4 represent the parasitic capacitance effects caused by the series inductor configuration inside the series resonator. These are additional capacitive effects caused by the potential difference between the series capacitor and the ground plane, respectively.

 On the other hand, CLs1 and CLs2 are parasitic dose effects occurring in the inducer structure itself. The present invention configures an equivalent circuit such that the capacitors have a parallel connection relationship as shown in FIG. 2 in order to use such parasitic capacitance effects positively. The capacitance values of the paralleled capacitors can be added circuitally. That is, parasitic capacitance effects of the series inductor and the series capacitor constituting the series resonator may be added to the parallel capacitor effect through the equivalent circuit configuration of FIG. 2. 3 and 4, the parallel capacitance values of FIG. 3 are equivalent to the sum of the parasitic capacitance values and the parallel capacitance values in FIG. 4. That is, as compared with the structural implementation of the parallel capacitors of FIG. 1 according to the conventional configuration method, as shown in FIG. 2, the parasitic effect is not only reduced, but also the shielding size. Even the effects of adding a ground plane for this may be taken into account.

The design pattern when the equivalent circuit of FIG. 2 is actually implemented as a laminated filter on the laminated sheet surface will be described. Hereinafter, an example of implementing a low pass filter (LPF) as a stacked filter will be described, but it will be apparent that other types of filters can also be implemented as a stacked filter having the same concept as the structure of the present invention.

5 is a diagram illustrating an external perspective view of a stacked filter according to an exemplary embodiment of the present invention, and FIG. 6 is an exploded cross-sectional view of the stacked filter according to an exemplary embodiment of the present invention.

The stacked filter of the present invention forms resonators and capacitors formed in a plurality of dielectric sheets so that resonance occurs between the inductors and capacitors, a ground part provided respectively above and below these resonators, and an upper part of the ground parts. Or an input electrode and an output electrode formed on any one of the lower portions.

Insulated and separated input electrodes and output electrodes are formed in the ground portion, and the input signals flowing through the input electrodes flow through the inductors, capacitors, and stubs of the dielectric sheets to the output electrodes.

Thus, the ground portion includes an upper ground plane 20a positioned above the plurality of dielectric sheets on which the resonator is formed to provide potential ground and a lower ground plane 20b positioned below the plurality of dielectric sheets.

An input electrode 21a and an output electrode 21b are formed on any one of the upper ground plane 20a or the lower ground plane 20b. In an embodiment of the present invention, an input is input to the upper ground plane 20a. An example in which the electrode 21a and the output electrode 21b are formed will be described.

Although the input electrode 21a and the output electrode 21b are formed on the ground plane, the input electrode 21a and the output electrode 21b are formed on the ground plane by being insulated from the potential ground.

The input signal flowing through the input electrode 21a flows to the output electrode 21b through inductors, capacitors, and stubs formed in the plurality of dielectric sheets through via holes of each dielectric sheet.

The resonator is implemented by a plurality of dielectric sheets in which inductors and capacitors are formed. The dielectric sheet may be generally implemented as a rectangular ceramic dielectric sheet, but may be implemented in other shapes and materials. These multiple dielectric sheets form a laminate 30 (hereinafter referred to as a "laminated dielectric sheet") having a plurality of internal dielectric sheets forming an interior. Via holes are formed in each dielectric sheet, thereby providing an input signal to each dielectric sheet.

The laminated dielectric sheet will be described with an example consisting of a first dielectric sheet 31, a second dielectric sheet 32, and a third dielectric sheet 33 in order to explain the present invention. It will be apparent that the present invention can be applied not only in the state in which the dielectric sheets are stacked but also in the state in which a plurality of dielectric sheets are stacked.

In addition, a patternless dielectric sheet 34 (hereinafter, referred to as a “patternless dielectric sheet”) in which no inductor or a capacitor is formed may be further inserted between the upper ground plane 20a and the first dielectric sheet 31. This may be used to maintain the gap between the upper ground plane 20a and the first dielectric sheet 31 in an actual product implementation.

The laminated dielectric sheets 30, 31, 32, 33, and 34 are implemented as capacitors having a shape in which a spiral inductor and a capacitor electrode face each other, thereby forming two resonance electrodes. The spiral inductor is implemented on the first dielectric sheet 31 and the second dielectric sheet 32, and the capacitor is implemented on the first dielectric sheet 31 and the second dielectric sheet 32.

The inductors are provided in a plurality of dielectric sheets, and the inductors of each sheet are formed to face each other symmetrically. That is, the input lead pattern and the output lead pattern are formed on the first dielectric sheet 31 and the second dielectric sheet 32 so as to be symmetrical to face each other.

In detail, the first dielectric sheet 31 is formed with a first conductive pattern formed such that the conductive material pattern is spirally formed on the surface of the first dielectric sheet. In the first conductive pattern, an input first conductive pattern 41a and an output first conductive pattern 41b are formed on the first dielectric sheet through via holes and the input electrode and the output electrode, respectively. The input first lead pattern 41a is connected through the via hole of the input electrode 21a and the unpatterned dielectric sheet 34, and the output first lead pattern 41b is connected through the via hole like the output electrode 21b. Connected.

Similarly, the second dielectric sheet 32 is formed with a spiral second conductive pattern. The second lead pattern is formed of an input second lead pattern 42a and an output second lead pattern 42b. The input second lead pattern 42a and the output second lead pattern 42b are connected to the input first lead pattern 41a and the output first lead pattern 41b through via holes of the first dielectric sheet 31, respectively. do.

Meanwhile, an input first capacitor electrode 51a and an output first capacitor electrode 51b are formed symmetrically with the input and output first conductive patterns 41a and 41b on the first dielectric sheet surface. That is, the input first capacitor electrode 51a having the shape of an electrode plate is connected to the input first lead pattern 41a, and the output first capacitor electrode 51b is similarly formed to the output first lead pattern ( And connected to 41b).

Similarly, an input second capacitor electrode 52a and an output second capacitor electrode 52b are formed symmetrically with the input and output second lead patterns 42a and 42b on the second dielectric sheet surface. That is, the input second capacitor electrode 52a having the shape of an electrode plate is connected to the input second lead pattern 42a, and the output second capacitor electrode 52b is similarly formed to the output second lead pattern ( 42b).

The input second capacitor electrode 52a is formed at a position where the input first capacitor electrode 51a of the first dielectric sheet 31 faces up and down with each other, and the output second capacitor electrode 52b is also formed as the second capacitor electrode 52b. 1 is formed at a position where the output first capacitor electrode 51a of the dielectric sheet 31 faces up and down with each other. The input second capacitor electrode 52a and the output second capacitor electrode 52b are connected to the third lead pattern 43 of the third dielectric sheet 33 through a via hole to receive an electrode.

A third conductive pattern 43 having a 'c' pattern is formed in the third dielectric sheet 33, and each end of the third conductive pattern is input through the via hole of the second dielectric sheet 32. 42a and an output second lead pattern 42b, respectively.

When the first dielectric sheet 31, the second dielectric sheet 32, and the third dielectric sheet 33 formed as described above are stacked, as a result, the input first conductor pattern 41a and the input second conductor pattern ( 42a) is connected through the via hole to have a spiral wire pattern to perform the function of an input inductor, and likewise, the output first conductor pattern 41b and the output second conductor pattern 42b are connected to each other. Do this.

On the other hand, the input first capacitor electrode 51a and the input second capacitor electrode 52a are located at positions facing each other up and down to perform the function of the input capacitor, and the output first capacitor electrode 51b and the output second The capacitor electrode 52b is also positioned at the position facing each other up and down to perform the function of the output capacitor.

The size of the capacitor electrodes 51a and 52a of the input capacitor and the size of the capacitor electrodes 51b and 52b of the output capacitor may be different in size to reduce reflection loss. For example, the reflection loss can be reduced by making the size of the input capacitor larger than the output capacitor.

An input inductor implemented with an input first lead pattern 41a and an input second lead pattern 42a, and an input capacitor including an input first capacitor electrode 51a and an input second capacitor electrode 52a are located at positions facing each other. It is formed symmetrically to perform resonance (input resonance) with each other.

Similarly, an output inductor implemented with an output first lead pattern 41b and an output second lead pattern 42b and an output capacitor including an output first capacitor electrode 51b and an input second capacitor electrode 52b face each other. It is formed symmetrically in position to perform resonance (output resonance) with each other.

As described above, the resonance frequency of the input resonator and the resonance frequency of the output resonator serve to generate respective attenuation poles. If the resonant frequencies of the two resonators are equal to each other, a symmetrical circuit configuration is possible and one attenuation pole is generated. However, in the present invention, asymmetry is required because different resonant frequencies must be generated for the frequency blocking characteristic of the wide band. It consists of.

Therefore, for the impedance matching according to the asymmetric configuration, the stub connected to the input electrode and the output electrode should also be formed asymmetrically with different sizes. The stub for performing such impedance matching is composed of first stubs 61a and 61b implemented on the first dielectric sheet 31 and a third stub 63 implemented on the third dielectric sheet 33. The first stub and the third stub may be formed to be located inside the conductive pattern formed on the dielectric sheet so that an efficient area configuration design may be achieved.

The first stubs 61a and 61b and the third stub 63 are connected to conductive patterns formed on the respective dielectric sheets 31 and 33 to form electrodes to perform impedance matching. That is, the first stub is connected to the inside of the first conductive pattern on the first dielectric sheet, and the third stub is connected to the inside of the third conductive pattern on the third dielectric sheet.

The first stub has an input first stub 61a and an output first stub 61b. The input first stub 61a is connected to the input first lead pattern 41a to perform input impedance matching, and the output first stub 61b is connected to the output first lead pattern 41b to output impedance matching. Do this.

However, since the impedance matching due to the asymmetry between the input side and the output side is different, the sizes of the input first stub 61a and the output first stub 61b are asymmetrically implemented.

Meanwhile, in the resonator configuration, the parallel capacitance (capacitance) effect due to the potential difference between the resonator structure and the ground plane is in parallel with the capacitance (capacitance) effect between the stub and the ground plane in FIG. The parasitic capacitance (capacitance) effect due to the potential difference between the planes is in addition to the capacitance (capacitance) effect between the stub and the ground plane, thereby indirectly implementing the ideal capacitance value of FIG. For reference, when the equivalent circuit of FIG. 2 is implemented in the circuit pattern of FIG. 6, a corresponding figure of each pattern implementation is shown in FIG. 2.

On the other hand, since the parasitic capacitances of the stub and the resonator on the equivalent circuit share the nodes, the position of the stub can be mounted in a spiral inductor, resulting in a more efficient area configuration. As a result, the parasitic capacitance (capacitance) inside the inductor and the capacitor serves to reduce the size of the stub, thereby having a positive effect of reducing the size of the overall filter circuit by the pattern design according to the preferred embodiment of the present invention. Come.

In the above description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the present invention is not to be determined by the embodiments described above, but will be apparent in the claims as well as equivalent scope.

1 is a general equivalent circuit diagram of a low pass filter composed of ideal passive elements.

2 is an equivalent circuit diagram of a low pass filter considering parasitic capacitance effect according to an embodiment of the present invention.

3 is a table showing parallel capacitance values in an equivalent circuit of a low pass filter.

4 is a table that is equivalent to the sum of parasitic dose values and parallel dose values.

5 is a diagram illustrating an external perspective view of a stacked filter according to an exemplary embodiment of the present invention.

6 is an exploded cross-sectional view of a multilayer filter according to an exemplary embodiment of the present invention.

FIG. 7 is a graph showing that the resonant frequencies of two resonators in a stacked filter generate attenuation poles according to an exemplary embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

20a; Upper ground plane 20b: Lower ground plane

21a: input electrode 21b: output electrode

30: laminated dielectric sheet 31: first dielectric sheet

32: second dielectric sheet 33: third dielectric sheet

34: patternless dielectric sheet 41a; Input first lead pattern

41b: output first lead pattern 42a: input second lead pattern

42b: output second lead pattern 43: third lead pattern

51a: input first capacitor electrode 51b: output first capacitor electrode

52a: input second capacitor electrode 52b: output second capacitor electrode

61a: input first stub 61b: output first stub

63: third stub

Claims (23)

A resonator including a plurality of dielectric sheets stacked on each other and including an inductor and a capacitor resonating with each other; A ground part provided on the upper and lower parts of the resonator part, respectively; And Input electrode and output electrode formed in any one of the ground portion Laminated filter comprising a. The method of claim 1, wherein the ground portion, A stacked filter in which the input signal coming through the input electrode flows through the inductor, capacitor and stub of each dielectric sheet to the output electrode. The method of claim 2, And a via hole in each of the dielectric sheets. The laminated filter according to claim 1, wherein the inductors are provided in a plurality of dielectric sheets, and the inductors of each sheet are formed to face each other symmetrically. The method of claim 4, wherein the induction machine is stacked, A first conductive pattern spirally formed on the first dielectric sheet; And Second lead pattern spirally formed on the second dielectric sheet Laminated filter comprising a. The third dielectric sheet of claim 5, wherein the third dielectric sheet is formed by being laminated under the second dielectric sheet. Laminated filter comprising a. The method of claim 5, The first conductive pattern may include an input first conductive pattern and an output first conductive pattern formed on the first dielectric sheet through via holes and the input electrode and the output electrode, respectively; And The second lead pattern may include an input second lead pattern and an output second lead pattern formed on the surface of the second dielectric sheet through the via holes and the input electrode and the output electrode, respectively. Stacked filter to form a. The method of claim 6, A third lead pattern having a 'c' pattern is formed on the third dielectric sheet surface, and each end of the third lead pattern is connected to the input second lead pattern and the output second lead pattern through via holes of the second lead pattern sheet, respectively. Stacked filter formed by. The method of claim 7, wherein An input inductor formed by connecting the input first lead pattern and the input second lead pattern; And An output inductor formed by connecting the output first lead pattern and the output second lead pattern Laminated filter comprising a. The method of claim 1, wherein the capacitor A laminated filter provided in a plurality of dielectric sheets in the form of an electrode plate, wherein the capacitors of each sheet are symmetrically formed up and down, and the shape size of the capacitors is asymmetrically formed from side to side. The method of claim 10, wherein the capacitor And a first capacitor electrode formed on the first dielectric sheet and a second capacitor electrode symmetrically formed at a point opposite to the first capacitor electrode on the second dielectric sheet. The method of claim 11, wherein the capacitor Input and output first capacitor electrodes formed on the surface of the first dielectric sheet to be symmetrical with the input and output first conductive patterns; And Input and output second capacitive electrodes formed symmetrically with the input and output second lead patterns on the second dielectric sheet surface Laminated filter including The method of claim 12, wherein the first capacitor electrode, The multilayer filter connected to the first conductive pattern on the same dielectric sheet surface as the first conductive pattern, and the second capacitor electrode is connected to the third conductive pattern through a via hole on the surface of the second dielectric sheet. The method of claim 13, An input capacitor formed by connecting the input first capacitor electrode and the input second capacitor electrode; And An output capacitor formed by connecting the output first capacitor electrode and the output second capacitor electrode; Laminated filter comprising a. The method of claim 14, An input capacitor formed symmetrically at a position facing the input inductor and resonating with each other; And Output capacitors formed symmetrically in a position facing the output inductor and resonating with each other Laminated filter comprising a. 16. The stacked filter of claim 15, further comprising a capacitor that varies a size of the capacitor electrode of the input capacitor and the size of the capacitor electrode of the output capacitor. The stub of claim 1, wherein the stub performs impedance matching to the resonator unit. Laminated filter comprising a. The method of claim 17, wherein the stub, A first stub connected to the first conductive pattern on the first dielectric sheet; And A third stub connected to and formed in a third conductive pattern on the third dielectric sheet Laminated filter comprising a. 19. The multilayer filter of claim 18, wherein the first stub and the third stub form electrodes to perform impedance matching. The method of claim 19, wherein the first stub, A multilayer filter comprising an input first stub and an output first stub. The method of claim 20, wherein the stub, The input first stub is connected to the input first lead pattern to match an input impedance; And The output first stub is connected to the output first lead pattern stacked filter for output impedance matching. The method of claim 21, The stacked filter, wherein the mutual size of the input stub and the output stub are formed asymmetrically. 2. The laminated filter of claim 1, further comprising a conductive patternless sheet inserted to maintain a gap between the ground portion and the first dielectric sheet.

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