KR20100002875A - Semiconductor package - Google Patents

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KR20100002875A
KR20100002875A KR1020080062924A KR20080062924A KR20100002875A KR 20100002875 A KR20100002875 A KR 20100002875A KR 1020080062924 A KR1020080062924 A KR 1020080062924A KR 20080062924 A KR20080062924 A KR 20080062924A KR 20100002875 A KR20100002875 A KR 20100002875A
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semiconductor package
substrate
electromagnetic
semiconductor chip
semiconductor
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KR1020080062924A
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Korean (ko)
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조철호
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주식회사 하이닉스반도체
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Priority to KR1020080062924A priority Critical patent/KR20100002875A/en
Publication of KR20100002875A publication Critical patent/KR20100002875A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE: A semiconductor package is provided to block an electromagnetic wave emitted from the semiconductor package by forming an electromagnetic interference shield unit with an electromagnetic interference shield film. CONSTITUTION: A substrate has a ground line. A semiconductor chip is attached on an upper side of the substrate. An electromagnetic interference shield encapsulation unit(160) covers the semiconductor on the upper side of the substrate. The electromagnetic interference shield encapsulation unit includes a thermosetting resin(140) and an electromagnetic interference shield film(150).

Description

반도체 패키지{Semiconductor package}Semiconductor Package {Semiconductor package}

본 발명은 반도체 패키지에 관한 것으로서, 보다 상세하게는, 반도체 패키지에서 방출되는 전자파를 차단함과 아울러 전체 높이를 줄일 수 있는 반도체 패키지에 관한 것이다. The present invention relates to a semiconductor package, and more particularly, to a semiconductor package capable of blocking an electromagnetic wave emitted from a semiconductor package and reducing the overall height.

오늘날 전자 산업의 추세는 경량화, 소형화, 고속화, 다기능화, 고성능화되고 높은 신뢰성을 갖는 제품을 저렴하게 제조하는 것이다. 이와 같은 제품 설계의 목표 달성을 가능하게 하는 중요한 기술 중의 하나가 바로 패키지 조립 기술이다.The trend in today's electronics industry is to make products that are lighter, smaller, faster, more versatile, more powerful and more reliable. One of the key technologies that enables these product design goals is package assembly technology.

이러한 패키지 조립 기술은 웨이퍼 조립 공정을 거쳐 집적회로가 형성된 반도체 칩을 외부 환경으로부터 보호하고, 기판 상에 용이하게 실장되도록 하여 반도체 칩의 동작 신뢰성 확보하기 위한 기술이다. 종래 반도체 패키지는 칩 부착 공정, 와이어 본딩 공정, 몰딩, 트림/포밍 공정 등의 다양한 공정들을 포함하고 있다.This package assembly technique is a technique for securing the operation reliability of the semiconductor chip by protecting the semiconductor chip on which the integrated circuit is formed through the wafer assembly process from the external environment and easily mounted on the substrate. The conventional semiconductor package includes various processes such as a chip attaching process, a wire bonding process, a molding, and a trim / forming process.

한편, 최근에는 메모리 반도체 소자의 속도가 계속 향상됨에 따라 상기 반도체 패키지에서는 다량의 전자파가 발생하게 되며, 상기 다량의 전자파는 반도체 패키지가 부착되는 메모리 모듈의 신뢰성을 악화시킨다. On the other hand, in recent years, as the speed of a memory semiconductor device continues to improve, a large amount of electromagnetic waves are generated in the semiconductor package, and the large amount of electromagnetic waves deteriorates the reliability of the memory module to which the semiconductor package is attached.

즉, 고속으로 구동하는 고집적화된 소자들이 구비된 반도체 칩의 내부는 많은 금속 배선들이 형성되어 있어 상기 반도체 칩으로부터의 전자파 발생에 따른 전자방해(Electromagnetic interference : EMI)가 증가되고 있는 추세이다. 자세하게, 반도체 패키지는 고속 동작 및 저전압으로 구동될수록 신호 슬루율(Signal Slew Rate) 및 커런트(Current)가 증가되며, 다층 금속 배선으로 인해 상기 금속 배선들 간의 역방향 커런트 패스(Current Return Path)가 제대로 확보되지 못하여 전자방해가 증가되고 있다. 또한, 반도체 칩의 전원(Power)과 그라운드(Ground) 사이의 공진과 고속 동작 및 동시에 동작하는 입출력 단자가 많아짐에 따라 전원과 그라운드의 노이즈가 증가하게 되어 반도체 칩의 전자방해가 증가되고 있다. That is, since many metal wires are formed in the semiconductor chip including the highly integrated devices that drive at high speed, electromagnetic interference (EMI) due to the generation of electromagnetic waves from the semiconductor chip is increasing. In detail, as the semiconductor package is driven at high speed and low voltage, the signal slew rate and current are increased, and the reverse current path between the metal wires is properly secured due to the multi-layered metal wires. There is an increase in electromagnetic interference. In addition, as the resonance between the power supply and the ground of the semiconductor chip and the high speed operation and the input / output terminals which operate simultaneously increase the noise of the power supply and the ground, the electromagnetic interference of the semiconductor chip is increased.

게다가, 반도체 칩들이 스택되면, 상기 하나의 반도체 칩에서 발생하였던 영향이 스택된 반도체 칩의 수에 따라 증가하게 되고, 상기 반도체 칩 간의 영향이 더해져 상기 전자파의 발생량은 더욱 증가되어 전자방해를 유발하며, 이로 인해, 반도체 칩의 동작 특성 문제 및 다른 전자 부품의 전기적 특성을 열화시킨다.In addition, when the semiconductor chips are stacked, the influence that has occurred in the one semiconductor chip increases with the number of stacked semiconductor chips, and the influence between the semiconductor chips is added to generate the electromagnetic waves further, causing electromagnetic interference. As a result, the operation characteristics of the semiconductor chip and the electrical characteristics of other electronic components are deteriorated.

아울러, 반도체 패키지 측면에서 상기 전자방해를 방지하기 위하여 반도체 패키지의 봉지부 내에 전도성 파티클을 첨가하는 방법이 개발되고 있으나, 반도체 패키지의 내의 금속와이어들의 전기적인 쇼트(Short)를 막기 위해 함유량이 1 ~ 2% 수준으로 제한되어 있어 실제 전자방해의 개선 효과는 거의 없는 수준이다.In addition, in order to prevent the electromagnetic interference from the semiconductor package side, a method of adding a conductive particle into the encapsulation portion of the semiconductor package has been developed, but the content is 1 to prevent electrical short of the metal wires in the semiconductor package. As it is limited to 2% level, there is almost no improvement in actual electromagnetic interference.

본 발명은 반도체 패키지에서 방출되는 전자파를 차단함과 아울러 전체 높이 를 줄일 수 있는 반도체 패키지를 제공한다.The present invention provides a semiconductor package that can block the electromagnetic waves emitted from the semiconductor package and reduce the overall height.

본 발명에 따른 반도체 패키지는, 그라운드 라인을 갖는 기판; 상기 기판의 상면에 부착된 반도체 칩; 및 상기 기판의 상면에 상기 반도체 칩을 덮도록 형성된 전자파 차폐 봉지 부재를 포함한다. A semiconductor package according to the present invention includes a substrate having a ground line; A semiconductor chip attached to an upper surface of the substrate; And an electromagnetic shielding encapsulation member formed on an upper surface of the substrate to cover the semiconductor chip.

상기 전자파 차폐 봉지 부재는 열경화성 수지 및 전자파 차폐 필름을 포함하여 이루어진다.The electromagnetic wave shielding sealing member includes a thermosetting resin and an electromagnetic wave shielding film.

상기 전자파 차폐 필름은 금속판이다.The electromagnetic wave shielding film is a metal plate.

상기 금속판은 상기 기판의 그라운드 라인과 연결된다.The metal plate is connected to the ground line of the substrate.

상기 전자파 차폐 필름은 상기 열경화성 수지의 측면을 덮도록 형성된다.The electromagnetic wave shielding film is formed to cover the side surface of the thermosetting resin.

상기 전자파 차폐필름 상에 구비된 EMC로 이루어진 캡핑부를 더 포함한다.The capping unit further comprises an EMC provided on the electromagnetic shielding film.

상기 반도체 칩은 상기 기판과 금속와이어로 연결된다.The semiconductor chip is connected to the substrate by metal wires.

상기 반도체 칩은 상기 기판과 범프로 연결된다.The semiconductor chip is connected to the substrate by a bump.

본 발명은 반도체 패키지를 형성하기 위하여 기판의 상면에 반도체 칩을 보호하기 위한 필름 형태의 열경화성 수지와 상기 열경화성 수지 상에 형성된 얇은 두께의 전자파 차폐필름을 포함하는 전자파 차폐부재를 형성함으로써 상대적으로 넓은 면적을 갖는 반도체 패키지의 상부로 전자파가 방출되는 것을 방지할 수 있다.The present invention provides a relatively large area by forming an electromagnetic shielding member including a thermosetting resin in the form of a film for protecting the semiconductor chip on the upper surface of the substrate to form a semiconductor package and an electromagnetic shielding film having a thin thickness formed on the thermosetting resin. It is possible to prevent the electromagnetic wave is emitted to the upper portion of the semiconductor package having a.

또한, 종래 EMC로 이루어진 봉지부를 형성하기 위한 복잡한 공정을 진행할 필요가 없으며, 몰드 금형 장치가 필요 없어 반도체 패키지의 제조 비용을 절감할 수 있고, 제조 라인의 공간을 효과적으로 활용할 수 있으며, 반도체 패키지 제조 공정을 단순화할 수 있다.In addition, there is no need to proceed with a complicated process for forming an encapsulation part made of conventional EMC, and there is no need for a mold mold apparatus, thereby reducing the manufacturing cost of the semiconductor package, effectively utilizing the space of the manufacturing line, and manufacturing the semiconductor package. Can be simplified.

아울러, 상기 봉지부 형성을 위한 일정 수준의 높이 확보가 필요하지 않아 얇은 두께의 반도체 패키지를 형성할 수 있다. In addition, it is not necessary to secure a certain level of height for forming the encapsulation portion, so that a semiconductor package having a thin thickness can be formed.

그리고, 상기 전자파 차폐필름을 열전도도가 우수한 금속막으로 형성할 수 있으며, 이에 따라, 전자파 차폐는 물론 반도체 패키지의 열방출 능력을 향상시킬 수 있다.In addition, the electromagnetic shielding film may be formed of a metal film having excellent thermal conductivity. As a result, the electromagnetic shielding as well as the heat dissipation capability of the semiconductor package may be improved.

이하에서는, 본 발명의 실시예에 따른 반도체 패키지를 상세히 설명하도록 한다.Hereinafter, a semiconductor package according to an embodiment of the present invention will be described in detail.

도 1은 본 발명의 일 실시예에 따른 반도체 패키지를 도시한 도면이며, 도 2는 본 발명의 다른 실시예에 따른 반도체 패키지를 도시한 도면이다.1 is a view showing a semiconductor package according to an embodiment of the present invention, Figure 2 is a view showing a semiconductor package according to another embodiment of the present invention.

도 1 및 도 2를 참조하면, 본 발명에 따른 반도체 패키지(100)는 필름 형태의 열경화성 수지(140) 및 전자파 차폐필름(150)을 포함하는 전자파 차폐 봉지 부재(160)가 구비된다. 1 and 2, the semiconductor package 100 according to the present invention is provided with an electromagnetic shielding member 160 including a thermosetting resin 140 and an electromagnetic shielding film 150 in a film form.

자세하게, 도 1을 참조하면, 상면에 다수의 접속 패드(미도시) 및 그라운드 라인(미도시)이 구비된 기판(110) 상에 반도체 칩(120)이 배치되고, 상기 반도체 칩(120)은 범프(122)를 매개로 상기 기판(110)과 전기적으로 연결된다. 상기 기판(110)과 반도체 칩(120) 간에 상기 범프(122)를 보호하기 위한 충진재(130)가 개 재되며, 상기 충진재(130)는 경우에 따라 형성되지 않을 수 있다. In detail, referring to FIG. 1, a semiconductor chip 120 is disposed on a substrate 110 having a plurality of connection pads (not shown) and ground lines (not shown) on an upper surface thereof. The bump 122 is electrically connected to the substrate 110. A filler 130 may be interposed between the substrate 110 and the semiconductor chip 120 to protect the bumps 122, and the filler 130 may not be formed in some cases.

상기 반도체 칩(120)은, 도 2에 도시된 바와 같이, 금속와이어(124)를 매개로 상기 기판(110)과 전기적으로 연결될 수 있다. As illustrated in FIG. 2, the semiconductor chip 120 may be electrically connected to the substrate 110 through a metal wire 124.

도 1 및 도 2에 도시된 바와 같이, 상기 기판(110)의 상면에는 상기 반도체 칩(120)을 덮도록 소프트(Soft)한 물성을 갖는 필름 형태의 열경화성 수지(140) 및 전자파 차폐필름(150)을 포함하는 전자파 차폐 봉지 부재(160)가 형성된다. 1 and 2, a thermosetting resin 140 and an electromagnetic wave shielding film 150 having a film form having a soft property to cover the semiconductor chip 120 on an upper surface of the substrate 110. An electromagnetic wave shielding encapsulation member 160 is formed.

상기 소프트한 물성의 열경화성 수지(140)는 온도가 상승하면 점도가 급격히 저하되어 흐름성이 좋아지고, 이에 따라, 상기 반도체 칩(120)을 용이하게 봉지한다. 상기 필름 형태의 열경화성 수지(140)는 일정 시간 이상 지속적으로 열을 받게 되면 경화가 진행되며, 이에 따라, 상기 열경화성 수지(140)은 종래 EMC(Epoxy molding compound)와 유사한 수준의 강도를 갖게 된다. When the temperature of the soft thermosetting resin 140 rises, the viscosity decreases rapidly, thereby improving flowability. Accordingly, the semiconductor chip 120 is easily encapsulated. When the thermosetting resin 140 in the form of film is continuously heated for a predetermined time or more, the curing proceeds. Accordingly, the thermosetting resin 140 has a strength similar to that of the conventional epoxy molding compound (EMC).

상기 열경화성 수지(140) 상에 형성된 상기 전자파 차폐필름(150)은 휴대폰 등 전자파에 민감한 전자 기기의 전자파 방출을 막기 위해 사용되는 전자파 차폐필름이 사용된다.The electromagnetic shielding film 150 formed on the thermosetting resin 140 may be an electromagnetic shielding film used to prevent electromagnetic wave emission of electronic devices sensitive to electromagnetic waves such as mobile phones.

아울러, 상기 전자파 차폐필름(150)은 금속막으로 형성할 수 있으며, 바람직하게, 열전도도가 우수한 금속막으로 형성할 수 있다. 이러한 경우, 전자파 차폐는 물론 반도체 패키지의 열방출 능력을 향상시킬 수 있다.In addition, the electromagnetic shielding film 150 may be formed of a metal film, preferably, a metal film having excellent thermal conductivity. In this case, not only the electromagnetic shielding but also the heat dissipation capability of the semiconductor package can be improved.

상기 기판(110)의 하면에는 외부와의 전기적인 연결을 위한 솔더볼과 같은 외부접속단자(170)가 부착된다.An external connection terminal 170 such as a solder ball for electrical connection with the outside is attached to the bottom surface of the substrate 110.

그리고, 도 3에 도시된 바와 같이, 본 발명에 따른 반도체 패키지(200)은 전 자파 차폐필름(250)의 손상을 방지하기 위하여 상기 전자파 차폐필름(250) 상에 EMC로 이루어진 캡핑부(280)를 형성할 수 있다.And, as shown in Figure 3, the semiconductor package 200 according to the present invention is a capping part 280 made of EMC on the electromagnetic shielding film 250 to prevent damage to the electromagnetic shielding film 250 Can be formed.

아울러, 도 4에 도시된 바와 같이, 상기 전자파 차폐필름(350)은 상기 열경화성 수지(340)의 측면에 배치되도록 연장되어 형성되며, 상기 열경화성 수지(140)의 측면에 배치된 전자파 차폐필름(350)은 상기 기판(110)에 배치되며, 상기 외부접속단자(170)와 전기적으로 연결된 그라운드 라인에 부착되어 전자파를 외부로 방출시킨다. In addition, as shown in FIG. 4, the electromagnetic shielding film 350 is formed to extend on the side of the thermosetting resin 340, and the electromagnetic shielding film 350 is disposed on the side of the thermosetting resin 140. ) Is disposed on the substrate 110 and attached to a ground line electrically connected to the external connection terminal 170 to emit electromagnetic waves to the outside.

이상에서와 같이, 본 발명은 반도체 패키지를 형성하기 위하여 기판의 상면에 반도체 칩을 보호하기 위한 필름 형태의 열경화성 수지와 상기 열경화성 수지 상에 형성된 전자파 차폐필름을 포함하는 전자파 차폐 봉지 부재를 포함하여 이루어진다. As described above, the present invention comprises an electromagnetic wave shielding encapsulation member including a thermosetting resin in the form of a film for protecting the semiconductor chip on the upper surface of the substrate to form a semiconductor package and an electromagnetic shielding film formed on the thermosetting resin. .

이에 따라, 본 발명에 따른 반도체 패키지는 상부에 얇은 두께의 전자파 차폐 필름을 구비함으로써 상대적으로 넓은 면적을 갖는 반도체 패키지의 상부로 전자파가 방출되는 것을 방지할 수 있다.Accordingly, the semiconductor package according to the present invention can be prevented from emitting the electromagnetic wave to the upper portion of the semiconductor package having a relatively large area by having a thin electromagnetic shielding film of the upper portion.

또한, 종래 EMC로 이루어진 봉지부를 형성하기 위한 복잡한 공정을 진행할 필요가 없으며, 몰드 금형 장치가 필요 없어 반도체 패키지의 제조 비용을 절감할 수 있고, 제조 라인의 공간을 효과적으로 활용할 수 있으며, 반도체 패키지 제조 공정을 단순화할 수 있다.In addition, there is no need to proceed with a complicated process for forming an encapsulation part made of conventional EMC, and there is no need for a mold mold apparatus, thereby reducing the manufacturing cost of the semiconductor package, effectively utilizing the space of the manufacturing line, and manufacturing the semiconductor package. Can be simplified.

아울러, 종래 반도체 패키지는 반도체 칩을 보호하는 EMC로 이루어진 봉지부를 형성하기 위하여 반도체 칩의 상부로 일정 수준 이상의 봉지부 형성 높이가 필 요하였으나, 본 발명에 따른 반도체 패키지는 필름 형태의 열경화성 수지으로 상기 반도체 칩을 보호함으로써 상기 봉지부 형성을 위한 일정 수준의 높이 확보가 필요하지 않아 얇은 두께의 반도체 패키지를 형성할 수 있다. In addition, in the conventional semiconductor package, although a certain level or more is required to form an encapsulation portion formed above the semiconductor chip to form an encapsulation portion formed of EMC protecting the semiconductor chip, the semiconductor package according to the present invention is a thermosetting resin in the form of a film. By protecting the semiconductor chip, it is not necessary to secure a certain level of height for forming the encapsulation portion, thereby forming a thin semiconductor package.

그리고, 상기 전자파 차폐필름을 열전도도가 우수한 금속막으로 형성할 수 있으며, 이에 따라, 전자파 차폐는 물론 반도체 패키지의 열방출 능력을 향상시킬 수 있다.In addition, the electromagnetic shielding film may be formed of a metal film having excellent thermal conductivity. As a result, the electromagnetic shielding as well as the heat dissipation capability of the semiconductor package may be improved.

이상, 여기에서는 본 발명을 특정 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다. As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

도 1 및 도 2는 본 발명의 일 실시예에 따른 반도체 패키지를 도시한 도면.1 and 2 illustrate a semiconductor package according to an embodiment of the present invention.

도 3은 본 발명의 다른 실시예에 따른 반도체 패키지를 도시한 도면.3 illustrates a semiconductor package in accordance with another embodiment of the present invention.

도 4는 본 발명의 또 다른 실시예에 따른 반도체 패키지를 도시한 도면.4 illustrates a semiconductor package in accordance with another embodiment of the present invention.

Claims (8)

그라운드 라인을 갖는 기판;A substrate having a ground line; 상기 기판의 상면에 부착된 반도체 칩; 및A semiconductor chip attached to an upper surface of the substrate; And 상기 기판의 상면에 상기 반도체 칩을 덮도록 형성된 전자파 차폐 봉지 부재; An electromagnetic shielding encapsulation member formed to cover the semiconductor chip on an upper surface of the substrate; 을 포함하는 것을 특징으로 하는 반도체 패키지.A semiconductor package comprising a. 제 1 항에 있어서,The method of claim 1, 상기 전자파 차폐 봉지 부재는 열경화성 수지 및 전자파 차폐 필름을 포함하여 이루어지는 것을 특징으로 하는 반도체 패키지.The electromagnetic wave shielding encapsulation member includes a thermosetting resin and an electromagnetic wave shielding film. 제 2 항에 있어서,The method of claim 2, 상기 전자파 차폐 필름은 금속판인 것을 특징으로 하는 반도체 패키지.The electromagnetic wave shielding film is a semiconductor package, characterized in that the metal plate. 제 3 항에 있어서,The method of claim 3, wherein 상기 금속판은 상기 기판의 그라운드 라인과 연결된 것을 특징으로 하는 반도체 패키지.And the metal plate is connected to a ground line of the substrate. 제 2 항에 있어서,The method of claim 2, 상기 전자파 차폐 필름은 상기 열경화성 수지의 측면을 덮도록 형성된 것을 특징으로 하는 반도체 패키지.The electromagnetic wave shielding film is formed to cover the side surface of the thermosetting resin. 제 1 항에 있어서,The method of claim 1, 상기 전자파 차폐필름 상에 구비된 EMC로 이루어진 캡핑부를 더 포함하는 것을 특징으로 하는 반도체 패키지.And a capping part made of EMC provided on the electromagnetic shielding film. 제 1 항에 있어서,The method of claim 1, 상기 반도체 칩은 상기 기판과 금속와이어로 연결된 것을 특징으로 하는 반도체 패키지.And the semiconductor chip is connected to the substrate by metal wires. 제 1 항에 있어서,The method of claim 1, 상기 반도체 칩은 상기 기판과 범프로 연결된 것을 특징으로 하는 반도체 패키지.And the semiconductor chip is connected to the substrate by bumps.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8872319B2 (en) 2010-12-02 2014-10-28 Samsung Electronics Co., Ltd. Stacked package structure including insulating layer between two stacked packages
WO2018053208A1 (en) * 2016-09-15 2018-03-22 Skyworks Solutions, Inc. Through-mold features for shielding applications

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8872319B2 (en) 2010-12-02 2014-10-28 Samsung Electronics Co., Ltd. Stacked package structure including insulating layer between two stacked packages
US9520387B2 (en) 2010-12-02 2016-12-13 Samsung Electronics Co., Ltd. Stacked package structure and method of forming a package-on-package device including an electromagnetic shielding layer
WO2018053208A1 (en) * 2016-09-15 2018-03-22 Skyworks Solutions, Inc. Through-mold features for shielding applications

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