KR20100002872A - Method of manufacturing semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to prevent short between a gate and a contact by preventing the loss of the gate when forming a cobalt silicide gate. CONSTITUTION: A gate structure stacking a first hard mask layer on an upper side and including a silicon layer is formed on a semiconductor substrate. An interlayer insulation layer(116) is formed between the gate structures. The first hard mask layer is removed. A metal silicide layer is formed on the gate structure without the first hard mask layer with the lower height than the interlayer insulation layer. A second hard mask layer is formed to fill the space between the interlayer insulation layers on the metal silicide layer.

Description

Manufacturing method of semiconductor device {METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE}

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device using a damascene process in forming a metal silicide gate.

In general, a gate of a semiconductor device includes a gate conductive film made of an oxide film and a polysilicon film, and a laminated film of a protective film formed on the gate conductive film. This is because the polysilicon film satisfies physical properties required as a gate such as high melting point, ease of thin film formation, ease of line pattern, stability to an oxidizing atmosphere, and flat surface formation.

However, in accordance with the recent trend of high integration of semiconductor devices, as the design rule decreases, the channel length becomes smaller than the gate width when the width of the gate electrode is 0.35 μm or less, thereby lowering the resistance. In order to form the gate having the gate conductive film, a metal gate structure composed of a laminated film of a polysilicon film and a metal film has been converted. Research is being actively conducted.

Such metal silicide gates have a higher resistivity than conventional metal gates, but have more advantageous properties in terms of retention, and thus are used as very useful techniques for improving process yield and improving gate stability.

However, although not shown and described in detail, in the case of the aforementioned tungsten silicide (WSix) gate, the tungsten silicide is applied as the gate material as the spacing between the gates decreases because the specific resistance of the tungsten silicide (WSix) material itself is large. It's getting harder to do.

In addition, the tungsten silicide gate requires a complicated stack structure and a sidewall structure at the time of gate formation to improve its surface oxidation and interfacial properties due to the property that the tungsten is a metal.

Meanwhile, in order to solve the above problems, a cobalt silicide (CoSix) gate structure has been proposed, but when the cobalt silicide layer is formed by a method of forming a gate of a conventional stack structure, after forming the cobalt silicide gate, it serves as a hard mask. Since it is not possible to form a material capable of performing, there is a concern that a short circuit between the gate and the contact may occur as a loss occurs at a portion of the gate in a subsequent contact process.

The present invention provides a method of manufacturing a semiconductor device capable of forming a hard mask on the gate when forming a cobalt silicide gate.

In addition, the present invention provides a method of manufacturing a semiconductor device that can prevent the occurrence of a loss of the gate when forming the cobalt silicide gate to prevent a short circuit between the gate and the contact.

According to an aspect of the present invention, there is provided a method of fabricating a semiconductor device, the method including: forming a gate structure including a silicon film and a first hard mask film stacked on an upper surface thereof; Forming an interlayer insulating film between the gate structures; Removing the first hard mask layer; Forming a metal silicide layer on the gate structure from which the first hard mask layer has been removed to a height lower than that of the interlayer insulating layer; And forming a second hard mask layer on the metal silicide layer to fill the interlayer insulating layer.

The semiconductor device may further include spacers formed on both sidewalls of the gate structure and the first hard mask layer.

The first hard mask film is formed of a nitride film, and the interlayer insulating film is formed of an oxide film.

The forming of the interlayer dielectric layer may include forming an interlayer dielectric layer on the semiconductor substrate to cover the gate structure and the first hard mask layer; First CMP the interlayer insulating film; And performing secondary CMP on the first CMP interlayer insulating layer until the first hard mask layer is exposed.

The removing of the first hard mask layer may be performed by wet etching using phosphoric acid.

The forming of the metal silicide film may include depositing a metal film on a semiconductor substrate including a gate structure from which the first hard mask film is removed; Performing heat treatment at a temperature of 300 to 700 ° C. to react with the gate structure on the semiconductor substrate on which the metal film is deposited; And removing the unreacted metal film by the heat treatment.

The metal film is formed of cobalt (Co).

The step of removing the unreacted metal film is performed by wet etching using sulfuric acid to which fruit water is added at a temperature of 80 to 150 ° C.

After the step of removing the unreacted metal film, performing a heat treatment at a temperature of 500 ~ 900 ℃; further includes.

The second hard mask film is formed of a nitride film.

The forming of the second hard mask layer may include depositing a second hard mask layer on a semiconductor substrate including a gate structure on which the metal silicide layer is formed; And removing the second hard mask layer with CMP until the interlayer dielectric layer is exposed.

In the depositing of the second hard mask film, the second hard mask film is formed to a thickness of 1000 to 3000 GPa.

The removing of the second hard mask film is performed by adding 1 to 10% of phosphoric acid to a slurry used to remove the second hard mask film.

The slurry is characterized in that the selectivity ratio of nitride to oxide film has a range of 30: 1 to 50: 1.

In the present invention, when the metal silicide gate is formed, a hard mask layer may be easily formed on the metal silicide layer by using a damascene process.

Accordingly, the present invention can prevent the occurrence of loss of the metal silicide gate in a subsequent contact process, thereby preventing a short circuit between the gate and the contact.

Furthermore, the present invention maintains the existing gate structure by forming a hard mask film on the metal silicide film as described above, so that subsequent semiconductor processing such as a contact or bit line forming process may be performed without changing the process or the like. It can apply to the manufacturing process of an element.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

1A to 1G are cross-sectional views illustrating processes for manufacturing a semiconductor device according to an embodiment of the present invention, which will be described below.

Referring to FIG. 1A, a gate insulating film 106, a gate conductive film 108, and a first hard layer are formed on a semiconductor substrate 102 having a device isolation film 104 and an active region partitioned by the device isolation film 104. The mask film 110 is formed.

Here, the gate insulating film 102, the gate conductive film 108 and the first hard mask film 110 are formed of an oxide film, a polysilicon film, and a nitride film, respectively, wherein the gate conductive film 108 is a subsequent metal It is preferable to form in thickness of 1000-2000 micrometers in consideration of the thickness in which a silicide film is formed.

Referring to FIG. 1B, the first hard mask film 110, the gate conductive film 108, and the gate insulating film 102 are etched to form a first hard mask film 110 on an upper surface of the semiconductor substrate 102. ) Is formed to form a gate structure 112 composed of a gate insulating film 102 and a gate conductive film 108.

Then, a spacer 114 is formed on the surfaces of the gate structure 112 and the first hard mask layer 110.

In this case, the spacer 114 is formed of at least one of an oxide film and a nitride film, and preferably, has a stacked structure of an oxide film, a nitride film, and an oxide film.

Referring to FIG. 1C, an interlayer insulating layer may be formed on the gate structure 112 and the first hard mask layer 110 on which the spacer 114 is formed to cover the first hard mask layer 110 and the gate structure 112. 116) to a thickness of 3000 to 6000 mm 3.

Referring to FIG. 1D, a first chemical mechanical polishing (CMP) is performed such that the interlayer insulating film 116 remains on the first hard mask film 110 by a thickness of 600 to 1000 GPa, and then the first CMP is deposited. The interlayer insulating layer 116 is subjected to secondary CMP until the first hard mask layer 110 is exposed.

Here, the primary CMP is performed by using a silica-based slurry, and the secondary CMP is formed on the surface of the first hard mask layer 110 by using a ceria-based high selectivity slurry having a high selectivity between oxide films and nitride films. The secondary CMP for the oxide film is stopped.

Referring to FIG. 1E, portions of the first hard mask layer 110 exposed by the first and second CMPs are removed until the gate structure 112 is exposed.

Removal of the portion of the first hard mask layer 110 is performed by wet etching using phosphoric acid.

Referring to FIG. 1F, a metal film 118 is formed on the semiconductor substrate 102 including the gate structure 112 exposed by the removal of the portion of the first hard mask film 110.

Here, the metal film 118 is formed of cobalt (Co), wherein the cobalt is preferably formed in a thickness of 200 to 500 kPa so as to be formed by a thickness of about 30 to 50% of the subsequent metal silicide film. Do.

Referring to FIG. 1G, a heat treatment may be performed at a temperature of 300 to 700 ° C. on a semiconductor substrate 102 on which a metal film 118 such as coantt is formed, such as a cobalt silicide layer on the gate structure 112. The metal silicide film 120 is formed.

Then, the unreacted metal film 118 is removed by wet etching using sulfuric acid added with fruit water.

At this time, in order to improve the removal rate of the unreacted metal film 118 may be performed at a temperature of 80 ~ 150 ℃.

Meanwhile, after the formation of the metal silicide layer 120 such as the cobalt silicide layer, heat treatment may be further performed at a temperature of 500 to 900 ° C. to improve the stability of the metal silicide layer 120.

Referring to FIG. 1H, a nitride film is formed on a semiconductor substrate 102 including a gate structure 112 on which the unreacted metal film 118 is removed and the metal silicide film 120 is formed thereon. A second hard mask film 122 having a thickness of 3000 GPa is formed.

Referring to FIG. 1I, the second hard mask 122 film is removed by CMP until the interlayer insulating film 116 and the spacer 114 are exposed to remove the gate insulating film 106, the gate conductive film 108, and the metal silicide film. A gate 124 composed of the 120 and the second hard mask film 122 is formed.

Here, the removal of the second hard mask film 122 is performed using a slurry having a selectivity ratio of nitride oxide to oxide film in the range of 30: 1 to 50: 1, wherein the second hard mask film 122 In order to further facilitate the removal, 1 to 10% of phosphoric acid may be added to the slurry.

As described above, the present invention, unlike the conventional method of forming a metal silicide gate having a general stack structure by forming a metal silicide gate using the damascene process as described above, facilitates a hard mask film on the metal silicide layer. Can be formed.

Therefore, since the hard mask film can be easily formed on the metal silicide film as described above, the occurrence of loss of the gate can be prevented in a subsequent contact process, so that a short circuit between the gate and the contact can be prevented.

In addition, by forming a hard mask layer on the metal silicide layer as described above, the existing gate structure is maintained as it is, so that subsequent processes such as a contact or bit line forming process may be performed without changing the process or the like. It is applicable to a manufacturing process.

In the above-described embodiments of the present invention, the present invention has been described and described with reference to specific embodiments, but the present invention is not limited thereto, and the scope of the following claims is not limited to the scope of the present invention. It will be readily apparent to those skilled in the art that the present invention may be variously modified and modified.

1A to 1I are cross-sectional views illustrating processes for manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Claims (14)

Forming a gate structure on the semiconductor substrate, the gate structure including a silicon film and a first hard mask film stacked on an upper surface thereof; Forming an interlayer insulating film between the gate structures; Removing the first hard mask layer; Forming a metal silicide layer on the gate structure from which the first hard mask layer has been removed to a height lower than that of the interlayer insulating layer; And Forming a second hard mask layer on the metal silicide layer to fill the interlayer dielectric layer; Method of manufacturing a semiconductor device comprising a. The method of claim 1, The semiconductor device manufacturing method of claim 1, further comprising a spacer formed on both sidewalls of the gate structure and the first hard mask film. The method of claim 1, And the first hard mask film is formed of a nitride film, and the interlayer insulating film is formed of an oxide film. The method of claim 1, Forming the interlayer insulating film, Forming an interlayer insulating film on the semiconductor substrate to cover the gate structure and the first hard mask film; First CMP the interlayer insulating film; And Performing secondary CMP on the first CMP interlayer insulating film until the first hard mask film is exposed; Method of manufacturing a semiconductor device comprising a. The method of claim 1, The removing of the first hard mask layer may be performed by wet etching using phosphoric acid. The method of claim 1, Forming the metal silicide film Depositing a metal film on a semiconductor substrate including the gate structure from which the first hard mask film is removed; Performing heat treatment at a temperature of 300 to 700 ° C. to react with the gate structure on the semiconductor substrate on which the metal film is deposited; And Removing the unreacted metal film by the heat treatment; Method of manufacturing a semiconductor device comprising a. The method of claim 6, The metal film is a method of manufacturing a semiconductor device, characterized in that formed with cobalt (Co). The method of claim 6, The removing of the unreacted metal film is a method of manufacturing a semiconductor device, characterized in that the wet etching is performed using sulfuric acid added with fruit water at a temperature of 80 ~ 150 ℃. The method of claim 6, After removing the unreacted metal film, Performing heat treatment at a temperature of 500-900 ° C .; Method of manufacturing a semiconductor device further comprising. The method of claim 1, The second hard mask film is a semiconductor device manufacturing method, characterized in that formed as a nitride film. The method of claim 1, Forming the second hard mask film, Depositing a second hard mask layer on the semiconductor substrate including the gate structure on which the metal silicide layer is formed; And Removing the second hard mask film with CMP until the interlayer insulating film is exposed; Method of manufacturing a semiconductor device comprising a. The method of claim 11, And depositing the second hard mask film to a thickness of 1000 to 3000 GPa. The method of claim 11, The removing of the second hard mask layer is performed by adding 1 to 10% phosphoric acid to a slurry used to remove the second hard mask layer. The method of claim 13, The slurry is a method for manufacturing a semiconductor device, characterized in that the selectivity ratio of nitride to oxide film ranges from 30: 1 to 50: 1.

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