KR20070013726A - Method of forming a recessed channel transistor - Google Patents

Abstract

A method of manufacturing a recess channel transistor is provided to prevent the migration in first and second polysilicon layers by forming a gate electrode structure composed of the first polysilicon layer crystallized in a first temperature range and the second polysilicon layer crystallized in a second temperature range in an enhanced recess structure. A first recess(255) and an oval type second recess(270) under the first recess are formed in a substrate(200). A gate insulating layer(275) is formed along an upper surface of the resultant structure including the recess structure. A first pre-polysilicon layer is uniformly formed on the gate insulating layer. A first polysilicon layer(280) is formed by performing a first crystallization on the first pre-polysilicon layer. A second pre-polysilicon layer for filling the recess structure is formed thereon. A second polysilicon layer(285) is formed by performing a second crystallization on the second pre-polysilicon layer. The temperature range of the second crystallization is lower than that of the first crystallization.

Description

Method of manufacturing recessed channel transistor {Method of forming a recessed channel transistor}

1 is a photograph showing a defect of a gate electrode of a conventional recess channel transistor.

2 to 8 are cross-sectional views illustrating a method of manufacturing a recess channel transistor according to an exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

200: semiconductor substrate 205: device isolation film

230: pad oxide film 235: hard mask layer

240: photoresist pattern 250: hard mask pattern

255: first recess 260: protective film

265: protective film pattern 270: second recess

275: gate insulating film 280: first polysilicon film

285: second polysilicon film 290: gate electrode

The present invention relates to a method of manufacturing a recess channel transistor, and more particularly, to a method of manufacturing a recess channel transistor including a gate electrode in which no migration phenomenon occurs.

As semiconductor devices become more integrated, the line width and pattern spacing of patterns are significantly narrowed. As the line width of the pattern decreases, the channel length of the transistor also decreases. If the channel length is formed to be smaller than the channel length (effective channel length) required for the operation of the transistor, a short channel effect causes a problem that the electrical characteristics of the transistor are degraded. Accordingly, various types of transistors have been attempted to secure the effective channel length.

A transistor having a recessed channel has been developed as one of methods for maximizing transistor performance while having an effective channel length capable of preventing the short channel effect. For example, US Pat. No. 6,150,670 (Faltermeier et al.) Discloses a method of forming a vertical transistor in which a gate electrode is vertically embedded on a substrate.

However, in the vertical transistor as described above, as the design rule is reduced to 90 nm or less, the width of the bottom surface of the recess in which the gate electrode is located may gradually decrease, thereby causing two problems. First, when the bottom of the recess becomes sharp, a phenomenon in which an electric field is concentrated on the bottom occurs. In addition, the channel length of the transistor is reduced. These problems can be suppressed by extending the bottom of the recess.

For example, US Pat. No. 6,476,444 (Min et al.) Discloses a gate electrode embedded in a recess extending in an ellipse shape and a method of manufacturing the same in order to efficiently increase the channel region.

In order to form the gate electrode, a preliminary recess is first formed, and the substrate under the bottom of the preliminary recess is isotropically etched to form a recess having an extended ellipse shape. Thereafter, a gate oxide film is formed in the recess, and polysilicon having a substantially uniform thickness is deposited on the side of the recess to bury the recess. Thereafter, an annealing process for crystallizing the polysilicon is performed at about 700 to 1000 ° C. As a result, the gate electrode is completed.

However, the gate electrode is defective in the gate electrode due to the migration phenomenon of the polysilicon as shown in the SEM photograph shown in FIG. 1 during the annealing process. That is, the phenomena of the polysilicon crushing cause poor electrical characteristics of the recess transistor.

Accordingly, it is a first object of the present invention to provide a method of manufacturing a recess channel transistor capable of preventing migration of polysilicon gate electrodes.

According to an embodiment of the present invention for achieving the above object, a method of manufacturing a recess channel transistor may include a first recess extending below a surface of a substrate and an ellipse having a larger width than the first recess while communicating with the first recess. A substrate having a second recess formed thereon is formed. A gate insulating layer having a substantially uniform thickness is formed on the top surface of the substrate and the inner sidewalls of the first and second recesses. A first preliminary polysilicon film having substantially the same thickness is formed on an upper surface of the substrate on which the gate insulating film is formed, and inner walls of the first recess and the second recess. The first preliminary polysilicon film is first crystallized to form a first polysilicon film. A second preliminary polysilicon film covering the substrate is formed while the first recess and the second recess in which the first polysilicon film is formed are buried. The second preliminary polysilicon film is second crystallized at a temperature lower than the first crystallization temperature to form a second polysilicon film. As a result, the gate electrode of the recess channel transistor is formed.

In the method of manufacturing a recess channel transistor of the present invention, the first polysilicon film is formed to have a thickness of 20 to 50% of the thickness of the second polysilicon film, and a first crystallization temperature for forming the first polysilicon film. Is preferably from 700 to 1100 ° C. The second crystallization temperature for forming the second polysilicon film is preferably 700 to 1000 ° C.

In addition, in one embodiment of the present invention, the protective film pattern is made of silicon oxide or silicon nitride, the first cleaning to remove the impurities remaining in the first polysilicon film after forming the first polysilicon film The process can be carried out further. After the forming of the second polysilicon film, a second cleaning process for removing impurities remaining in the second polysilicon film is performed, and a second polysilicon film exposed to the hardmask by applying a hard mask; The first polysilicon layer may be sequentially patterned to form a gate electrode.

According to the method as described above, the technical configuration is to perform the two-stage polysilicon film deposition process and the two-stage crystallization step of the polysilicon film to form the gate electrode. As a result, the gate electrode may not effectively migrate due to thermal stress in the recess, thereby effectively preventing an electrical defect of the recess channel transistor formed.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, but the present invention is not limited to the following embodiments, and those skilled in the art will appreciate the technical spirit of the present invention. The present invention may be embodied in various other forms without departing from the scope of the present invention. In the accompanying drawings, the dimensions of the substrates, layers (films), regions, pads, patterns or structures are shown in greater detail than actual for clarity of the invention. In the present invention, each layer (film), region, pad, pattern or structures is formed to be "on", "top" or "bottom" of the substrate, each layer (film), region, pad or patterns. When mentioned, each layer (film), region, pad, pattern or structure is meant to be directly formed over or below the substrate, each layer (film), region, pad or patterns, or other layers (film), Other regions, different pads, different patterns or other structures may be additionally formed on the substrate. In addition, where each layer (film), region, pad, pattern or structure is referred to as " first " and / or " second ", only each layer (film), region, pad is not intended to limit these members. , To distinguish between patterns or structures. Thus, "first" and / or "second" may be used selectively or interchangeably for each layer (film), region, pad, pattern or structure, respectively.

2 to 8 are cross-sectional views illustrating a method of manufacturing a recess channel transistor according to an exemplary embodiment of the present invention.

Referring to FIG. 2, an isolation layer 205 is formed on the substrate 200. Due to the formation of the isolation layer 205, the substrate 200 defines active regions in which transistors are formed and field regions for electrically separating the active regions.

The device isolation layer 205 is formed using a device isolation process such as a shallow trench isolation (STI) process. The isolation layer 205 is formed by forming an isolation trench under the surface of the plate and then embedding an oxide in the isolation trench. Examples of the oxide for forming the device isolation layer 205 include PSG (phosphor silicate glass), tetraethylorthosilicate (TEOS), undoped silicate glass (USG), boro-phosphorous silicate glass (BPSG), high density plasma (HDP) oxide or SOG. spin on glass.

Referring to FIG. 3, a first hard mask pattern 250 defining a portion where a first recess 255 is to be formed is formed on a substrate on which the pad oxide layer 230 is formed.

Specifically, the pad oxide layer 230 is formed on the substrate 200 on which the device isolation layer 205 is formed. The pad oxide layer 105 serves to relieve stress generated between the hard mask layer 110 and the substrate 100 during the subsequent formation of the hard mask layer 110. For example, the pad oxide layer 105 may be formed of an oxide such as silicon oxide (SiO ₂ ), and may be a thermal oxidation process, a chemical vapor deposition (CVD) process, or a high density plasma chemical vapor deposition (HDP-CVD). It can be formed using a process.

Subsequently, a hard mask layer 235 is formed on the pad oxide film 230. The hard mask layer 235 is formed using a material having an etch selectivity with respect to the substrate 200 and the pad oxide layer 230. For example, the hard mask layer 235 may be formed using a nitride such as silicon nitride or an oxynitride such as silicon oxynitride. In addition, the hard mask layer 110 may be formed on the pad oxide layer 230 using a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition process (PE-CVD), or an atomic layer deposition (ALD) process. .

Next, the photoresist pattern 240 is formed on the hard mask layer 235.

Referring to FIG. 4, the hard mask layer 325 is selectively etched using the photoresist pattern 240 as an etching mask. As a result, a hard mask pattern 250 is formed on the pad oxide layer 230 to define a region where the first recess 255 is to be formed.

Thereafter, the photoresist pattern 240 is removed by an ashing process and / or a stripping process.

Next, a first etching process of sequentially etching the pad oxide layer 230 and the substrate 200 is performed by applying the hard mask pattern 250 as an etching mask. Through the first etching process, the pad oxide layer 230 and the substrate 200 are partially etched to form a first recess 255 in the substrate 200, and the pad oxide layer may include the pad oxide layer pattern 245. Is formed.

Examples of the first etching process may include a reactive ion etching (RIE) process or a chemical dry etch (CDE) process. The first recess 255 formed by the first etching process is formed in a direction substantially perpendicular to the surface of the substrate 200.

Subsequently, a passivation layer 260 is formed on the side surface of the first recess 255 and the surface of the hard mask pattern 250. The passivation layer 260 is made of a material having an etching selectivity with respect to the substrate 200. For example, the protective film 260 is formed using an oxide such as silicon oxide or a nitride such as silicon nitride or titanium nitride.

In addition, the passivation layer 260 may include a chemical vapor deposition (CVD) process, a thermal oxidation process, a plasma enhanced chemical vapor deposition (PE-CVD) process, a high density plasma chemical vapor deposition (HDP-CVD) process, or an atomic layer deposition (ALD) process. It forms using a process. For example, when the first recess 255 has a width of about 500 kPa to about 900 kPa, the passivation layer 260 is formed to a thickness of about 40 kPa to about 100 kPa.

Referring to FIG. 5, the protective layer 260 may be removed on the sidewalls of the first recess 255 by removing the protective layer 260 existing on the upper surface of the first hard mask pattern 250 and the bottom surface of the first recess 130. 265). As the passivation layer pattern 265 is formed only on the sidewall of the first recess 255, the substrate 200 is exposed through the bottom surface of the first recess 255.

The substrate 200 exposed through the first recess 255 is etched using the passivation pattern 265 as an etching mask by performing a second etching process. The second etching process corresponds to an isotropic etching process. According to the second etching process, a second recess 270 having a width greater than the width of the first recess 255 is formed under the first recess 255. The second recess 270 has the shape of an ellipse or the shape of a track. For example, the second recess 270 is formed to have a width W of about 500 kPa to 1350 kPa. In this case, the ratio of the width H to the depth H of the second recess 270 is about 1: 1.0 to about 1.5.

Referring to FIG. 6, the first hard mask pattern 250, the pad oxide layer pattern 245, and the passivation layer pattern 265 are removed. The first hard mask pattern 250, the pad oxide layer pattern 245, and the protective layer pattern 265 may use a wet etching process using an etchant including phosphoric acid (H ₂ PO ₄ ) and / or a diluted hydrofluoric acid (HF) solution. Is removed through. As the pad oxide layer pattern 245 and the passivation layer pattern 245 are removed, the surface of the substrate 200 around the first recess 255 is exposed, and at the same time, the bottom surfaces of the first and second recesses 255 and 270. The substrate 200 is exposed through the fields and sidewalls.

A gate insulating film 275 is formed on the exposed substrate 200. The gate insulating layer 275 is formed on the bottoms and sidewalls of the first and second recesses 255 and 270 and the active region of the substrate 200. The gate insulating film 275 is formed using an oxide such as silicon oxide or a metal oxide having high dielectric constant (high-k). The gate insulating film 275 is formed using a thermal oxidation process, a chemical vapor deposition (CVD) process, or an atomic layer deposition (ALD) process.

In one embodiment of the present invention, when the gate insulating film 275 is made of silicon oxide, the gate insulating film 275 is formed to a thickness of about 40 kPa to about 100 kPa. According to another embodiment of the present invention, the gate insulating film 275 may be formed using titanium oxide (TiO ₂ ), zirconium oxide (ZrO ₂ ) or hafnium oxide (HfO ₂ ).

A first preliminary polysilicon film having a substantially uniform thickness on the upper surface of the substrate on which the gate insulating film 275 is formed and the inner sidewalls of the first recess 255 and the second recess 270 on which the gate insulating film is formed. C). The first preliminary polysilicon film may be a low pressure chemical vapor deposition (LPCVD) process, a chemical vapor deposition (CVD) process, a sputtering process, a plasma enhanced chemical vapor deposition (PE-CVD) process, a pulsed laser deposition (PLD) process, or an atomic layer ( ALD) can be formed using a lamination process.

Subsequently, the first preliminary polysilicon film is first crystallized at a predetermined temperature to form a crystallized first polysilicon film 280. The first crystallization process for forming the crystallized first polysilicon film is to anneal the first preliminary polysilicon film at a temperature of about 700 to 1100 ° C. and in an atmosphere provided with an inert gas. The first polysilicon layer 280 formed by performing the first crystallization process is applied to prevent migration from occurring under the gate electrode during the annealing process for forming the gate electrode. In addition, the thickness of the first polysilicon film preferably has 20 to 50% of the thickness of the second polysilicon film formed thereafter.

Thereafter, a first cleaning process for removing impurities remaining in the first polysilicon film 280 is performed. Examples of the first cleaning process include a dry cleaning process or a wet cleaning process.

Referring to FIG. 7, the second preliminary polysilicon covering the top surface of the substrate 200 on which the first polysilicon film 280 is formed while the first and second recesses on which the first polysilicon film is formed is buried. A film (not shown) is formed.

Specifically, the second preliminary polysilicon film may be a low pressure chemical vapor deposition (LPCVD) process, a chemical vapor deposition (CVD) process, a sputtering process, a plasma enhanced chemical vapor deposition (PE-CVD) process, a pulsed laser deposition (PLD) process, or an atomic layer. It can be formed using an (ALD) lamination step.

Subsequently, the second polysilicon film 285 is formed by second crystallizing the second preliminary polysilicon film (not shown) at a temperature lower than a first crystallization temperature for forming the first polysilicon film 2800. . A second crystallization process for forming the crystallized second polysilicon film 285 is to anneal the second preliminary polysilicon film (not shown) at a temperature of about 650 to 1050 ° C. and an inert gas. .

Since the second polysilicon layer 285 crystallized at a temperature lower than the first crystallization temperature has a more stable state than the first polysilicon layer 280, migration may be prevented from occurring at the gate electrode. Thereafter, a second cleaning process for removing impurities remaining in the second polysilicon film 280 is performed. Examples of the first cleaning process may include a dry cleaning or a wet cleaning process.

As another example, a conductive film (not shown) may be further formed on the second polysilicon film. The conductive film includes a metal silicide film or a metal film. In addition, the conductive film may have a multilayer structure including both a metal silicide film and a metal film. For example, the conductive film is formed using tungsten silicide (WSi ₂ ), titanium silicide (TiSi ₂ ), cobalt silicide (CoSi ₂ ), tungsten (W), titanium (Ti) and / or cobalt (Co).

Referring to FIG. 8, a second hard mask pattern (not shown) is formed on the second polysilicon film 285 to partially expose the second polysilicon film 285. Thereafter, the second polysilicon layer and the first polysilicon layer, which are derived by using the second hard mask pattern as an etching mask, are sequentially etched to include the first polysilicon pattern 282 and the second polysilicon pattern 288. The gate electrode 290 is formed. In detail, the gate electrode 290 is formed using a reactive ion etching process or a dry etching process.

Subsequently, the source / drain regions 295 are formed by implanting impurities into the active region of the substrate 200 using the gate electrode 290 as an ion implantation mask. Source / drain regions 295 are formed from the surface of the substrate 200 to a portion where the gate electrode 290 has a substantially maximum width.

As the gate electrode 290 and the source / drain regions 295 adjacent to the gate electrode are formed, a recess including the gate insulating layer 275, the gate electrode 290, and the source / drain regions 295 is formed. The channel transistor is completed.

As described above, according to the present invention, a first polysilicon film crystallized at a first temperature in a first recess and a second recess of a substrate and a second polysilicon film crystallized at a temperature lower than the first crystallization temperature. Since the gate electrode is formed under conditions where the second polysilicon film is stabilized than the first polysilicon film, migration between the first polysilicon film and the second polysilicon film may be prevented. In other words, it is possible to prevent the formation of the gate electrode short-circuited in the recess.

As a result, the characteristics of the semiconductor device including the gate electrode having such a structure can be improved. Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be able to variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. It will be appreciated.

Claims (8)

Providing a substrate having a first recess extending below the surface of the substrate and an elliptical second recess in communication with the first recess, the second recess having a larger width than the first recess; Forming a gate insulating film having a substantially uniform thickness on an upper surface of the substrate and inner sidewalls of the first and second recesses; Forming a first preliminary polysilicon film having substantially the same thickness on an upper surface of the substrate on which the gate insulating film is formed, and inner walls of the first recess and the second recess; First crystallizing the first preliminary polysilicon film to form a first polysilicon film; Forming a second preliminary polysilicon film covering the substrate while the first recess and the second recess in which the first polysilicon film is formed are buried; And And second crystallizing the second preliminary polysilicon film at a temperature lower than the first crystallization temperature to form a second polysilicon film. The method of claim 1, wherein the thickness of the first polysilicon film is 20 to 50% of the thickness of the second polysilicon film. The method of claim 1, wherein the first crystallization temperature is 700 to 1100 ° C. The method of claim 1, wherein the second crystallization temperature is 650 to 1050 ℃. The method of claim 1, wherein the first recess and the second recess is Anisotropically etching the substrate to form a first recess extending below the surface of the substrate; Forming a protective film pattern on sidewalls of the first recesses; Isotropically etching the bottom surface of the substrate exposed to the first recesses; And And removing the passivation layer pattern to form the recess channel transistor. The method of claim 5, wherein the protective layer pattern is formed of silicon oxide or silicon nitride. The method of claim 1, wherein after the forming of the first polysilicon film, a first cleaning process of removing impurities remaining in the polysilicon film is further performed. The method of claim 1, wherein after the forming of the second polysilicon film, Performing a second cleaning process of removing impurities remaining in the second polysilicon film; And And applying a hard mask to sequentially pattern the second polysilicon film and the first polysilicon film exposed to the hard mask to form a gate electrode.

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