KR20100002656A - Sense amplifier driving circuit for semiconductor memory apparatus - Google Patents

Abstract

PURPOSE: A sense amplifier driving circuit for semiconductor memory apparatus is provided to improve efficiency by refreshing enough while reducing power consumption of a refresh operation. CONSTITUTION: In a device, a first driver(110) includes a first inverter(111) and a second inverter(112). A first and the second inverter generate swing signal between a driving voltage and a ground voltage according to a first driving signal. A second driver(120) includes a third inverter(121) and a fourth inverter(122). A first and the second inverter generate a signal swing between the driving voltage and the ground according to a second driving signal. The third driver(130) includes a fifth inverter(131) and a sixth inverter(132). The first and the second inverter generate a signal swing between the driving voltage and the ground according to a third driving signal. A signal selection unit(140) includes a first and a second gate.

Description

Sense amplifier driving circuit of semiconductor memory device {Sense Amplifier Driving Circuit for Semiconductor Memory Apparatus}

The present invention relates to the design of a semiconductor memory device, and more particularly, to a sense amplifier driving circuit of a semiconductor memory device.

In general, when a word line is activated in a semiconductor memory device, charge sharing occurs between the bit line and the bit bar line, and then the sense amplifier operates. At this time, the sense amplifier initially performs an overdrive operation using the external voltage VDD for a predetermined pulse period so that the bit line or the bit bar line can quickly reach the target voltage (core voltage) level.

1 is a view illustrating a driving signal controller 10 of a sense amplifier driving circuit according to the related art.

The driving signal controller 10 of the sense amplifier driving circuit according to the related art receives the first driving signal SAP1_O and generates the first control signal SAP1_C, and the first driver 11 and the second driving signal SAP2_O. And a second driver 12 for generating the second control signal SAP2_C and a third driver 13 for receiving the third driving signal SAN_O and generating the third control signal SAN_C.

The first driving signal SAP1_O is a high level pulse signal that allows the semiconductor memory device to perform an overdrive operation when an active command is input from the outside. The second driving signal SAP2_O is a signal that is enabled low immediately after the first driving signal SAP1_O is disabled so that the bit line or the bit bar line maintains the core voltage level. The third driving signal SAN_O is a signal that is enabled high when an active command is input to lower the bit line or the bit bar line to the ground voltage level.

The first driver 11 generates the first control signal SAP_C by raising the first driving signal SAP1_O to the driving voltage VPP level, and the second and third drivers 12 and 13 generate a second voltage. And raising the third control signals SAP2_O and SAN_O to the external voltage VDD level, respectively, to generate second and third control signals SAP2_C and SAN_C.

FIG. 2 is a diagram illustrating a sense amplifier driver 20 and a sense amplifier receiving the control signals SAP1_C, SAP2_C, and SAN_C.

The first control signal SAP1_C is input to the gate of the first NMOS transistor N1 of the sense amplifier driver 20. When the first control signal SAP1_C is enabled, the first NMOS transistor N1 is turned on to provide an external voltage VDD to the first power terminal RTO of the sense amplifier, and the sense amplifier is overdrive. Perform the action.

The second control signal SAP2_C is input to the first PMOS transistor P1 of the sense amplifier driver 20. When the second control signal SAP2_C is enabled, the first PMOS transistor P1 is turned on to provide a core voltage VCORE to the first power supply terminal RTO of the sense amplifier, and may be a bit line or a bit. Allow barain to maintain the core voltage level.

The third control signal SAN_C is input to the second NMOS transistor N2 of the sense amplifier driver 20. When the third control signal SAN_C is enabled, the second NMOS transistor N2 is turned on to provide a ground voltage to the second power terminal SB of the sense amplifier and provide a bit line or a bit bar line. Lower to ground voltage level.

3 is a timing diagram of each control signal SAP1_C, SAP2_C, and SAN_C according to the related art.

The first control signal SAP1_C is enabled at the level of the driving voltage VPP by the first driver 11 receiving the first driving signal SAP_O, and the second control signal SAP2_C is the second driving signal. The low voltage is enabled by the second driver 12 receiving the SAP2_O, and the third control signal SAN_C is connected to the external voltage VDD by the third driver 13 receiving the third driving signal SAN_O. ) Is enabled at the level.

The first driver 11 receives the first driving signal SAP1_O and generates a first control signal SAP_C enabled at the driving voltage VPP level to generate a first NMOS of the sense amplifier driver 20. By providing the transistor N1, the external voltage VDD is sufficiently provided to the first power supply terminal RTO of the sense amplifier. A signal having a driving voltage VPP level higher than the external voltage VDD is input to the gate of the first NMOS transistor N1, so that the external voltage (V) is not lost due to the threshold voltage of the first NMOS transistor N1. VDD) may be provided to the first power supply terminal RTO as it is. The overdrive operation is performed by applying the first control signal SAP1_C of the driving voltage VPP level, thereby enabling fast sensing.

Meanwhile, the semiconductor memory device periodically performs a refresh operation to maintain data stored in a cell. In the refresh operation, since fast sensing is not required, driving the first driving signal SAP1_O to the driving voltage VPP level and performing the overdrive operation using the driven first control signal SAP1_C are performed. One causes unnecessary current consumption. In order to overcome the above problem, a method of generating the first control signal SAP1_C by driving the first driving signal SAP1_O to the external voltage VDD level has been used. However, in this case, the voltage supply is not sufficient. There is a problem that the refresh operation cannot be performed sufficiently.

SUMMARY OF THE INVENTION An object of the present invention is to provide a sense amplifier driving circuit of a semiconductor memory device capable of sufficiently performing a refresh operation while reducing current consumption to solve the above problems.

The sense amplifier driving circuit of the semiconductor memory device according to the present invention receives the first to third driving signals to generate an overdrive signal, first and second control signals, and generates the overdrive signal that varies according to an operation mode. A driving signal controller; And a sense amplifier driver which receives the overdrive signal and the first and second control signals to drive a sense amplifier. It includes.

According to the present invention, in the normal operation, the sense amplifier is driven in the same manner as in the conventional art, and the fast performance of the semiconductor memory device is ensured, and in the refresh operation, the refresh operation can be sufficiently performed while reducing the current consumption.

4 is a block diagram of a sense amplifier driving circuit of a semiconductor memory device according to an embodiment of the present invention.

The sense amplifier driving circuit of the semiconductor memory device according to the embodiment of the present invention includes a driving signal controller 100 and a sense amplifier driver 20.

The driving signal controller 100 receives the first to third driving signals SAP1_O, SAP2_O, and SAN_O to receive the first to third driving signals SAP1_O, SAP2_O, and SAN_O to drive voltage VPP or external voltage ( VDD) level, and the pulled-up signals are selected according to whether the refresh signal REF is enabled to generate an overdrive signal, first and second control signals SAP1_C, SAP2_C, and SAN_C.

The first to third driving signals SAP1_O, SAP2_O, and SAN_O are signals for driving the sense amplifier driver 20. The driving voltage VPP is a voltage at which the external voltage VDD is pumped for use in a semiconductor memory device, and is a voltage higher than the external voltage VDD. In addition, the refresh signal REF is a signal indicating that the semiconductor memory device performs a refresh operation. For example, when the semiconductor memory device performs a self refresh operation, the refresh signal REF is enabled and is a signal that is disabled when the self refresh operation is not performed.

FIG. 5 is a circuit diagram of the driving signal controller 100 shown in FIG. 4.

The drive signal controller 100 includes first to third drivers 110, 120, and 130 and a signal selector 140. The first driver 110 receives the first driving signal SAP1_O and outputs a signal swinging between the driving voltage VPP and the ground voltage. The second and third drivers 120 and 130 receive the second and third driving signals SAP2_O and SAN_O, respectively, and output a swinging signal between the external voltage VDD and the ground voltage. The signal selector 140 provides the output of the first driver 110 or the output of the third driver 130 to the overdrive signal SAP1_C in response to the refresh signal REF. The output of the second driver 120 is provided as the first control signal SAP2_C, and the output of the third driver 130 is provided as the second control signal SAN_C.

A detailed configuration of a sense amplifier driving circuit of a semiconductor memory device according to an embodiment of the present invention will be described with reference to FIG. 5.

The first driver 110 includes two inverters 111 and 112 connected in series to receive the first driving signal SAP1_O and output a swinging signal between the driving voltage VPP and the ground voltage. The second and third drivers 120 and 130 respectively receive two second and third driving signals SAP2_O and SAN_O, and output two signals connected in series between the external voltage VDD and the ground voltage. Dogs 121 and 122 and 131 and 132.

As mentioned above, the signal selector 140 may be configured of the first and second pass gates PG1 and PG2 having inputs of the refresh signal REF and the outputs of the first and third drivers 110 and 130. Can be. An output of the refresh signal REF and the first driver 110 is input to the first pass gate PG1, and an output of the refresh signal REF and the third driver 130 is applied to the second pass gate ( PG2).

The sense amplifier driver 20 includes first and second pull-up drivers 21 and 22 and a pull-down driver 23. The first pull-up driver 21 supplies a voltage to the sense amplifier in response to an overdrive signal SAP1_C to drive the sense amplifier. The second pull-up driver 22 supplies the core voltage VCORE to the sense amplifier in response to the first control signal SAP2_C to drive the sense amplifier. The pull-down driver 23 provides a ground voltage to the sense amplifier in response to the second control signal SAN_C. The sense amplifier driver 20 will not be described in detail except for the above description in the related art.

6 is a timing diagram of an overdrive signal SAP1_C and control signals SAP2_C and SAN_C generated according to an exemplary embodiment of the present invention. The operation of the sense amplifier driving circuit of the semiconductor memory device according to the embodiment of the present invention will be described with reference to FIG. 6.

When an active command is input from the outside, the first to third driving signals SAP1_O, SAP2_O, and SAN_O are generated to drive the sense amplifier. The first driving signal SAP1_O is a signal for overdrive operation and is a high level pulse signal. The second driving signal SAP2_O is a signal enabled low when the first driving signal SAP1_O is disabled to maintain the bit line or the bit bar line at the core voltage VCORE level. The third driving signal SAN_O is a signal that is enabled high when an active command is input to lower the bit line or the bit bar line to the ground voltage level. The first to third driving signals SAP1_O, SAP2_O, and SAN_O are input to the first to third drivers 110, 120, and 130, respectively. The first driver 110 drives the first driving signal SAP1_O to the driving voltage VPP level, and the second and third drivers 120 and 130 drive the second and third driving signals SAP2_O and SAN_O. ) Are driven to the external voltage (VDD) level, respectively.

In the normal operation (operation except for the refresh operation) of the semiconductor memory device, the refresh signal REF is disabled low. In response to the refresh signal REF, the first pass gate PG1 is turned off and the second pass gate PG2 is turned off. Accordingly, the output of the first driver 110 driven at the driving voltage VPP level through the turned-on first pass gate PG1 is generated as the overdrive signal SAP1_C. The output of the third driver 130 is generated as the second control signal SAN_C.

In the normal operation of the semiconductor memory device, the overdrive signal SAP1_C driven at the driving voltage VPP level is input to the first pull-up driver 21 of the sense amplifier driver 20. Accordingly, the first pull-up driver 21 provides an external voltage to the sense amplifier so that the sense amplifier can perform an overdrive operation. In addition, the external voltage VDD is applied only during the short enable period to reduce current consumption.

In contrast to the above, in the refresh operation of the semiconductor memory device, the refresh signal REF is enabled high. In response to the refresh signal REF, the first pass gate PG1 is turned off and the second pass gate PG2 is turned on. Therefore, the output of the third driver 130 is generated as the overdrive signal SAP1_C through the turned-on second pass gate PG2. In addition, the output of the third driver 130 is generated as the second control signal SAN_C.

In the refresh operation of the semiconductor memory device, the overdrive signal SAP1_C driven at the external voltage VDD level is input to the first pull-up driver 21 of the sense amplifier driver 20. Therefore, the first pull-up driver 21 provides a voltage having a level lower than the external voltage VDD to the sense amplifier and drives the sense amplifier. Instead of providing a voltage having a level lower than the external voltage VDD as the sense amplifier, the semiconductor memory device may sufficiently perform the refresh operation by providing the voltage for a long enable period.

The first to second control signals SAP2_C and SAN_C are input to the sense amplifier driver 20 as in the prior art, and the sense amplifier driver 20 drives the sense amplifier.

In the normal operation, the overdrive operation and the like can be performed using the same control signal as in the prior art, thereby ensuring the performance of the semiconductor memory device. In addition, in the refresh operation, by using the output of the third driver driven to the external voltage level and having a large pulse width as the overdrive signal, it is possible to reduce current consumption and ensure a stable refresh operation.

As those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features, the embodiments described above should be understood as illustrative and not restrictive in all aspects. Should be. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

1 is a detailed circuit diagram of a driving signal controller according to the prior art;

2 is a view illustrating a sense amplifier driver and a sense amplifier receiving a control signal;

3 is a timing diagram of a control signal generated according to the prior art;

4 is a block diagram of a sense amplifier driving circuit of a semiconductor memory device according to an embodiment of the present invention;

5 is a detailed circuit diagram of a driving signal controller of FIG. 4;

6 is a timing diagram of a control signal generated according to an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

10/100: drive signal control unit 20: sense amplifier driver

11/110: first driver 12/120: second driver

13/130: third driver 140: signal selector

Claims (16)

A drive signal controller configured to receive the first to third drive signals, generate an overdrive signal, first and second control signals, and generate the overdrive signal that varies according to an operation mode; And A sense amplifier driver configured to drive the sense amplifier by receiving the overdrive signal and the first and second control signals; A sense amplifier driving circuit of a semiconductor memory device comprising a. The method of claim 1, The driving signal controller generates a first voltage as the overdrive signal in a refresh operation mode, and generates a second voltage as the overdrive signal in a normal operation mode. in. The method of claim 1, And the driving signal controller generates the overdrive signal having a longer enable period than when the refresh signal is disabled when the refresh signal is enabled. The method according to any one of claims 1 to 3, The driving signal controller may include: a first driver configured to receive the first driving signal and generate a signal swinging between the second voltage and the ground voltage; A second driver receiving the second driving signal and generating a signal swinging between the first voltage and the ground voltage to provide the first control signal; A third driver that receives the third driving signal and generates a signal swinging between the first voltage and the ground voltage and provides the signal as the second control signal; And A signal selector configured to selectively provide outputs of the first to third drivers as the overdrive signal in response to the refresh signal; A sense amplifier driving circuit of a semiconductor memory device comprising a. The method of claim 4, wherein The signal selector outputs the output of the first driver as the overdrive signal when the refresh signal is disabled, and outputs the output of the third driver as the overdrive signal when the refresh signal is enabled. A sense amplifier driving circuit of a semiconductor memory device. The method of claim 4, wherein The signal selector may include: a first pass gate configured to determine whether to turn on the refresh signal to generate an output of the first driver as the overdrive signal; And A second pass gate configured to be turned on according to whether the refresh signal is enabled to generate the overdrive signal from the output of the third driver; A sense amplifier driving circuit of a semiconductor memory device, characterized in that consisting of. The method of claim 2, And the second voltage is greater than the first voltage. The method of claim 2, The first amplifier is a sense amplifier driving circuit of the semiconductor memory device, characterized in that the external voltage. The method of claim 2, And the second voltage is a driving voltage. A first pull-up driver providing a first voltage or a second voltage to a sense amplifier in response to an overdrive signal, a second pull-up driver and a second control signal providing a core voltage to the sense amplifier in response to a first control signal; A sense amplifier driving circuit comprising a pull-down driver for providing a ground voltage to the sense amplifier in response, and driving the sense amplifier during a first period and a second period, When the refresh signal is enabled, the first pull-up driver provides the first voltage to drive the sense amplifier during the first period and the second period, and the second pull-up driver drives the core during the second period. And a sense amplifier driving circuit for driving the sense amplifier by providing a voltage. The method of claim 10, When the refresh signal is disabled, the first pull-up driver provides the second voltage to drive the sense amplifier during the first period, and the second pull-up driver provides the core voltage during the second period. And a sense amplifier driving circuit for driving the sense amplifier. The method of claim 10, And a control signal generator configured to receive the first to second driving signals and to generate the overdrive signal and the first and second control signals. The method of claim 12, The control signal generator may include a first driver configured to receive the first driving signal and generate a swinging signal between a driving voltage and a ground voltage; A second driver which receives the second driving signal and generates a signal swinging between an external voltage and a ground voltage to provide the first control signal; A third driver that receives the third driving signal and generates a signal swinging between an external voltage and a ground voltage and provides the signal as the second control signal; And A signal selector configured to selectively provide an output of the first driver and an output of a third driver as the overdrive signal in response to the refresh signal; A sense amplifier driving circuit of a semiconductor memory device comprising a. The method of claim 13, The signal selector may provide an output of the first driver as the overdrive signal when the refresh signal is disabled, and provide an output of the third driver as the overdrive signal when the refresh signal is enabled. A sense amplifier driving circuit of a semiconductor memory device. The method of claim 13, The signal selector may include: a first pass gate configured to determine whether to turn on the refresh signal to generate an output of the first driver as the overdrive signal; And A second pass gate configured to be turned on according to whether the refresh signal is enabled to generate the overdrive signal from the output of the third driver; A sense amplifier driving circuit of a semiconductor memory device, characterized in that consisting of. The method of claim 10, And the second voltage is greater than the first voltage.

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