KR20100002640A - Sense amplifier driving circuit for semiconductor memory apparatus and driving method thereof - Google Patents

Sense amplifier driving circuit for semiconductor memory apparatus and driving method thereof Download PDF

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Publication number
KR20100002640A
KR20100002640A KR1020080062607A KR20080062607A KR20100002640A KR 20100002640 A KR20100002640 A KR 20100002640A KR 1020080062607 A KR1020080062607 A KR 1020080062607A KR 20080062607 A KR20080062607 A KR 20080062607A KR 20100002640 A KR20100002640 A KR 20100002640A
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South Korea
Prior art keywords
sense amplifier
voltage
overdrive
high voltage
terminal
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KR1020080062607A
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Korean (ko)
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원형식
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주식회사 하이닉스반도체
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Priority to KR1020080062607A priority Critical patent/KR20100002640A/en
Publication of KR20100002640A publication Critical patent/KR20100002640A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/08—Control thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2227—Standby or low power modes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dram (AREA)

Abstract

PURPOSE: A sense amplifier driving circuit for a semiconductor memory apparatus and a driving method thereof are provided to secure the performance of a semiconductor memory device by supplying a high level voltage at an early sensing time. CONSTITUTION: In a device, an overdrive signal generator(110) generates a first and a second overdrive signal according to a sense amp enable signal. A high voltage driver(200) supplies a first high voltage for a section where the first overdrive signal is enabled to a sense amplifier. The high voltage driver supplies the second high voltage for a section where the second overdrive signal is enabled to the sense amplifier. The overdrive signal generator enables the second overdrive signal later than the first overdrive signal. The overdrive signal generator firstly disables the second overdrive signal earlier than first overdrive signal.

Description

Sense amplifier driving circuit of semiconductor memory device and driving method thereof {Sense Amplifier Driving Circuit for Semiconductor Memory Apparatus and Driving Method}

The present invention relates to the design of a semiconductor memory device, and more particularly, to a sense amplifier driving circuit and a method of driving the semiconductor memory device.

In general, when a word line is activated in a semiconductor memory device, charge sharing occurs between the bit line and the bit bar line, and then the sense amplifier operates. In this case, the sense amplifier initially performs an overdrive operation using the external voltage VDD for a predetermined pulse period so that the bit line or the bit bar line can quickly reach the target voltage level.

1 is a circuit diagram illustrating a sense amplifier driving circuit of a semiconductor memory device according to the prior art.

When an active command is externally applied, charge sharing occurs between the bit line and the bit bar line, and the overdrive signal SAP1 and the second control signal SAN are enabled. When the overdrive signal SAP1 is enabled, the first NMOS transistor N1 is turned on and the external voltage VDD is supplied to the driving power supply terminal RTO of the sense amplifier. The sense amplifier receives an external voltage VDD and performs an overdrive operation to quickly increase the bit line or the bit bar line connected to the sense amplifier to the core voltage VCORE level. When the second control signal SAN is enabled, the third NMOS transistor N3 is turned on and the ground voltage is supplied to the ground power terminal SB of the sense amplifier. The sense amplifier receives the ground voltage and lowers the bit line or bit bar line to the ground voltage level. The first control signal SAP2 is enabled when the overdrive signal SAP1 is disabled. After the overdrive operation is performed by the overdrive signal SAP1, the first control signal SAP2 is enabled so that the bit line or the bit bar line maintains the core voltage VCORE level. That is, when the first control signal SAP2 is enabled, the second NMOS transistor N2 is turned on, and the core voltage VCORE is supplied to the driving power supply terminal RTO of the sense amplifier, thereby providing a bit line or a bit bar line. It is possible to maintain this core voltage (VCORE) level.

Subsequently, when the precharge command is applied, the bit line equalization signal BLEQ is enabled. When the bit line equalization signal BLEQ is enabled, the fourth to sixth NMOS transistors N4, N5, and N6 are turned on, and the driving power terminal RTO and the ground power terminal SB of the sense amplifier are turned on. The bit line and the bit bar line have a bit line precharge voltage (VBLP, 1/2 VCORE) level. When the next active command comes in, the same operation is repeated.

On the other hand, the external voltage may be a high voltage or a low voltage depending on the system. When the external voltage is a high voltage, if the overdrive operation is performed without considering the level of the external voltage, the bit line or the bit bar line is excessively overshooted, which causes unnecessary current consumption and noise. . On the contrary, performing the same overdrive operation when the external voltage is low has a problem in that the level of the bit line or the bit bar line does not sufficiently increase to ensure the performance of the semiconductor memory device.

SUMMARY OF THE INVENTION In order to solve the above problems, an object of the present invention is to provide a sense amplifier driving circuit of a semiconductor memory device capable of preventing unnecessary current consumption, reducing noise, and ensuring the performance of the semiconductor memory device.

According to an embodiment of the present invention, a sense amplifier driving circuit may include: an overdrive signal generator configured to receive a sense amplifier enable signal and generate first and second overdrive signals; And receiving the first and second overdrive signals, providing a first high voltage to a sense amplifier during a period in which the first overdrive signal is enabled, and a second during a period in which the second overdrive signal is enabled. A high voltage driver for supplying a high voltage to the sense amplifier to drive the sense amplifier; It includes.

In addition, the method of driving a sense amplifier according to the present invention is a method of driving a sense amplifier for performing an overdrive operation by applying a voltage to a driving power supply terminal and a ground power supply terminal in the first to the third section, the first section Driving the sense amplifier by providing a first high voltage and a first low voltage to the driving power terminal and the ground power terminal, respectively; Driving the sense amplifier by providing a second high voltage and a second low voltage to the driving power terminal and the ground power terminal, respectively, in the second section; And driving the sense amplifier by providing only the first high voltage and the first low voltage to the driving power terminal and the ground power terminal, respectively, in the third section. It includes.

According to the present invention, in the overdrive operation of a sense amplifier, a low level high voltage is initially provided to minimize noise generation, and a high level high voltage is additionally provided when fast sensing is required to improve performance of a semiconductor memory device. After a sufficient amount of sensing is performed, the low level high voltage is again provided to perform the remaining overdrive operation to reduce current consumption due to overshooting.

2 is a view illustrating a sense amplifier driving circuit of a semiconductor memory device according to an embodiment of the present invention.

The sense amplifier driving circuit of the semiconductor memory device according to an exemplary embodiment of the present invention includes an overdrive signal generator 110 and a high voltage driver 200.

The overdrive signal generator 110 includes a plurality of pulse generators and receives the sense amplifier enable signal SAP to generate the first and second overdrive signals SAP1 and SAPS. The sense amplifier enable signal SAP is a signal that is activated when a word line is activated when an active command is received from the outside. Conventionally, an overdrive signal is generated through a pulse generator for receiving the sense amplifier enable signal SAP, and the first overdrive signal SAP1 is the same as the conventional overdrive signal. The first pulse generator 111 receives the SAP). The second overdrive signal SAPS is also generated by the second pulse generator 112 receiving the sense amplifier enable signal SAP. The first and second pulse generators 111 and 112 may be configured as general pulse generators that generate pulse signals by performing different delays, and a detailed description thereof will be omitted.

The overdrive signal generator 110 generates a first overdrive signal SAP1 and a second overdrive signal SAPS, and the second overdrive signal SAPS is converted into a first overdrive signal SAP1. It is enabled later than the time when it is enabled, and is disabled before the time when the first overdrive signal SAP1 is disabled. In other words, when the sense amplifier performs the overdrive operation, the first overdrive signal SAP1 is enabled during the overdrive operation period, and the second overdrive signal SAPS is turned on during the overdrive operation period. Enabled and disabled. For example, the second overdrive signal SAPS is enabled at a time when fast sensing is required to guarantee the speed of the semiconductor memory device, and is not limited to 80% to prevent excessive current consumption. ) May be disabled at the time when the above sensing is completed. In addition, the enable time and the disable time of the second overdrive signal SAPS may be adjusted through the test mode to find an optimal timing.

The high voltage driver 200 receives the first and second overdrive signals SAP1 and SAPS in the overdrive period so that the sense amplifier can perform an overdrive operation, and receives the first high voltage and the second high voltage. It is provided to the driving power supply terminal (RTO) of the sense amplifier. When the first overdrive signal SAP1 is enabled, the first high voltage is provided to the sense amplifier to drive the sense amplifier. When the second overdrive signal SAPS is enabled, the second high voltage is supplied to the sense amplifier. Drive the sense amplifier.

The high voltage driver 200 includes a first switching unit 210 and a second switching unit 220. The first switching unit 210 receives the first overdrive signal SAP1 to provide a first high voltage to the sense amplifier, and the second switching unit 220 supplies the second overdrive signal SAPS. Receives a second high voltage to the sense amplifier.

The first switching unit 210 receives the first overdrive signal SAP1 through a gate, receives an external voltage VDD through one of a source terminal and a drain terminal, and applies the first high voltage to the other terminal. The first MOS transistor is provided to the amplifier. The second switching unit 220 receives the second overdrive signal SAPS through a gate, receives an external voltage VDD through either one of a source terminal and a drain terminal, and applies the second high voltage to the other terminal. A second MOS transistor is provided to the amplifier.

In the exemplary embodiment of the present invention, it is particularly preferable that the first switching unit 210 and the second switching unit 220 are formed of NMOS transistors having different channel lengths. The first switching unit 210 may be configured as a long channel NMOS transistor NLC1 having a long channel, and the second switching unit 220 may be configured as a short channel NMOS transistor NSC1 having a short channel. Can be.

The channel length refers to a size of a transistor. In general, a long channel transistor refers to a transistor having a long length, and a short channel transistor refers to a transistor having a short length. In addition, the threshold voltage of the long channel transistor is greater than the threshold voltage of the short channel transistor. Therefore, when the same gate voltage is applied, the long channel transistor performs slower but more stable operation than the short channel transistor.

In order to achieve the object of the present invention, the first switching unit 210 and the second switching unit 220 is composed of transistors having different channel lengths are as follows. When the first overdrive signal SAP1 is enabled, the first high voltage equal to the size of the external voltage VDD minus the threshold voltage of the long channel NMOS transistor NLC1 is obtained through the first switching unit 210. When the second overdrive signal SAPS is enabled as a sense amplifier and the second overdrive signal SAPS is enabled, the size of the external voltage VDD minus the threshold voltage of the short channel NMOS transistor NSC1 through the second switching unit 220. This is to provide as many second high voltages as the sense amplifier. Thus, the first high voltage is a voltage having a level lower than the second high voltage.

3 is a timing diagram of signals of a sense amplifier driving circuit of a semiconductor memory device according to an embodiment of the present invention. The operation of the sense amplifier driving circuit of the semiconductor memory device according to the embodiment of the present invention will be described with reference to FIG. 3.

In the semiconductor memory device, when an active command is applied from the outside, the word line is activated and charge sharing occurs between the bit line and the bit bar line. At the time when the charge sharing is completed, the sense amplifier enable signal SAP is enabled high in order to perform the overdrive operation of the sense amplifier, and the first overdrive signal SAP1 is driven high in synchronization with the sense amplifier. Is enabled. When the first overdrive signal SAP1 is enabled high, the long channel NMOS transistor NLC1 constituting the first switching unit 210 is turned on, and the long channel NMOS transistor N1 is turned on at an external voltage VDD. A first high voltage equal to the size of the NLC1 minus the threshold voltage is provided to the sense amplifier to drive the sense amplifier. Thereafter, the second overdrive signal SAPS is enabled high. When the second overdrive signal SAPS is enabled high, the short channel NMOS transistor NSC1 constituting the second switching unit 220 is turned on, and the short channel NMOS transistor is turned on at an external voltage VDD. A second high voltage equal to the size of the NSC1 minus the threshold voltage is provided to the sense amplifier to drive the sense amplifier.

When the sufficient overdrive operation is completed to some extent, the second overdrive signal SAPS is disabled, and the second high voltage is not provided to the sense amplifier. After that, the first overdrive signal SAP1 remains enabled, and the long channel NMOS transistor NLC1 provides the first high voltage to the sense amplifier until the remaining overdrive operation is completed. Will be driven.

When the overdrive operation of the sense amplifier is completed, the first overdrive signal SAP1 is disabled and the power control signal SAP2 is enabled to provide the power voltage VCORE to the sense amplifier to drive the sense amplifier. do. After the pre-initiation command, the bit line equalization signal BLEQ is enabled and the bit line and the bit bar line are equalized through the fourth to sixth NMOS transistors N4, N5, and N6. The above operations after the overdrive operation of the sense amplifier are the same as before.

In the overdrive operation of the sense amplifier, a low level high voltage is initially provided to minimize noise generation, and a high level high voltage is additionally provided when fast sensing is required to ensure the performance of the semiconductor memory device. After sufficient sensing is performed, it can be understood that the current consumption due to overshooting can be reduced by providing only the low voltage high voltage to perform the remaining overdrive operation.

4 is a view illustrating a sense amplifier driving circuit of a semiconductor memory device according to still another embodiment of the present invention. Yet another embodiment of the present invention further includes a control signal generator 120 and a low voltage driver 300.

The control signal generator 120 receives the sense amplifier enable signal SAP and generates first and second control signals SAN and SANS. The first control signal SAN is enabled at the time when the sense amplifier enable signal SAP is enabled, as in the prior art. The control signal generator 120 may enable the second control signal SANS later than a time point at which the first control signal SAN is enabled.

The first control signal SAN may be generated through the third pulse generator 121, and the second control signal SANS may be generated through the fourth pulse generator 122. The third pulse generator 121 and the fourth pulse generator 122 may be configured as a general pulse generator for generating a pulse signal by performing a different delay. As described in the above embodiment, an optimal time point at which the second control signal SANS is enabled may be adjusted through a test mode.

The low voltage driver 300 receives the first and second control signals SAN and SANS and provides the first low voltage and the second low voltage to the ground power terminal SB of the sense amplifier.

The low voltage driver 300 includes a third switching unit 310 and a fourth switching unit 320. The third switching unit 310 receives the first control signal (SAN) to provide a first low voltage to the sense amplifier to drive the sense amplifier, and the fourth switching unit 320 is a second control signal ( SANS) is input to provide a second low voltage to the sense amplifier.

The third switching unit 310 receives the first control signal SAN through a gate, and one of the source terminal and the drain terminal is connected to the ground voltage terminal, and the other terminal provides the first low voltage to the sense amplifier. It is composed of a third MOS transistor. The fourth switching unit 320 receives the second control signal SANS through a gate, and either one of a source terminal and a drain terminal is connected to a ground voltage terminal, and provides the second low voltage to the other terminal as the sense amplifier. Is composed of a fourth MOS transistor.

In particular, in order to achieve the object of the present invention, the third switching unit 310 is composed of a long channel NMOS transistor (NLC2), the fourth switching unit 320 is composed of a short channel NMOS transistor (NSC2). Can be. Thus, the first low voltage has a higher voltage level than the second low voltage.

That is, when the first control signal SAN is enabled at the beginning of sensing, the first low voltage is supplied through the long channel NMOS transistor NLC2 to drive the sense amplifier to reduce noise due to a sudden level change in the bit line or the bit bar line. Then, a second low voltage is further provided through the short channel transistor NSC2 to drive the sense amplifier.

As those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features, the embodiments described above should be understood as illustrative and not restrictive in all aspects. Should be. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

1 is a sense amplifier driving circuit of a semiconductor memory device according to the prior art;

2 is a sense amplifier driving circuit of a semiconductor memory device according to an embodiment of the present invention;

3 is an operation timing diagram of a sense amplifier driving circuit of a semiconductor memory device according to an embodiment of the present invention;

4 is a sense amplifier driving circuit of a semiconductor memory device according to still another embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

110: overdrive signal generator

120: control signal generator

200: high voltage driver

300: low voltage driver

Claims (16)

An overdrive signal generator configured to receive the sense amplifier enable signal and generate first and second overdrive signals; And Receiving the first and second overdrive signals, providing a first high voltage to a sense amplifier during a period during which the first overdrive signal is enabled, and a second high voltage during a period during which the second overdrive signal is enabled A high voltage driver for providing the sense amplifier to drive the sense amplifier; A sense amplifier driving circuit of a semiconductor memory device comprising a. The method of claim 1, The overdrive signal generator may enable the second overdrive signal later than a time point at which the first overdrive signal is greater than an enable time, and disable the first overdrive signal before the time point at which the first overdrive signal is disabled. A sense amplifier driving circuit of a semiconductor memory device. The method of claim 2, The high voltage driver may include: a first switching unit configured to provide the first high voltage to the sense amplifier in response to the first overdrive signal; And A second switching unit configured to provide the second high voltage to the sense amplifier in response to the second overdrive signal; A sense amplifier driving circuit of a semiconductor memory device, characterized in that consisting of. The method of claim 3, wherein The first switching unit may include a first MOS transistor configured to receive the first overdrive signal through a gate, receive an external voltage through either one of a source terminal and a drain terminal, and provide the first high voltage to the sense amplifier through the other terminal. Consisting of, A second MOS transistor configured to receive the second overdrive signal through a gate, receive an external voltage through one of a source terminal and a drain terminal, and provide the second high voltage to the sense amplifier to the other terminal; A sense amplifier driving circuit of a semiconductor memory device, characterized in that consisting of. The method according to any one of claims 1 to 4, And wherein the first high voltage is a voltage having a level lower than that of the second high voltage. The method of claim 4, wherein And said first MOS transistor has a longer channel length than said second MOS transistor. The method of claim 1, A control signal generator configured to receive the sense amplifier enable signal and generate a first control signal and a second control signal; And The first and second control signals are input, the first low voltage is provided to the sense amplifier during the period in which the first control signal is enabled, and the second low voltage is sensed during the period in which the second control signal is enabled. A low voltage driver provided to an amplifier to drive the sense amplifier; The sense amplifier driving circuit of the semiconductor memory device further comprising. The method of claim 7, wherein And the control signal generation unit enables the second control signal later than a time point at which the first control signal is enabled. The method of claim 8, The low voltage driver may include: a first switching unit configured to provide the first low voltage to the sense amplifier in response to the first control signal; And A second switching unit configured to provide the second low voltage to the sense amplifier in response to the second control signal; A sense amplifier driving circuit of a semiconductor memory device, characterized in that consisting of. The method of claim 9, The first switching unit includes a first MOS transistor configured to receive the first control signal through a gate, and one of the source terminal and the drain terminal is connected to the ground voltage terminal, and the other terminal provides the first low voltage to the sense amplifier. Become, The second switching unit includes a second MOS transistor configured to receive the second control signal through a gate, and one of the source terminal and the drain terminal is connected to a ground voltage terminal, and the other terminal provides a second low voltage to the sense amplifier. And a sense amplifier driving circuit of the semiconductor memory device. The method according to any one of claims 7 to 10, And wherein the first low voltage is a voltage having a level higher than that of the second low voltage. The method of claim 10, And said first MOS transistor has a longer channel length than said second MOS transistor. In the first to third period, the method for driving a sense amplifier for performing an overdrive operation by applying a voltage to the driving power supply terminal and the ground power supply terminal, Driving the sense amplifier in the first section by providing a first high voltage and a first low voltage to the driving power terminal and the ground power terminal, respectively; Driving the sense amplifier by providing a second high voltage and a second low voltage to the driving power terminal and the ground power terminal, respectively, in the second section; And In the third section, driving the sense amplifier by providing only the first high voltage and the first low voltage to the driving power terminal and the ground power terminal, respectively; Sense amplifier driving method comprising a. The method of claim 13, And the second section is a section requiring faster amplification than the first section and the third section. The method of claim 13, And wherein the first high voltage is a voltage having a level lower than that of the second high voltage. The method of claim 13, The first low voltage is a voltage of a level higher than the second low voltage.
KR1020080062607A 2008-06-30 2008-06-30 Sense amplifier driving circuit for semiconductor memory apparatus and driving method thereof KR20100002640A (en)

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KR1020080062607A KR20100002640A (en) 2008-06-30 2008-06-30 Sense amplifier driving circuit for semiconductor memory apparatus and driving method thereof

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