KR100706828B1 - Bit-line Sense Amplifier Driver and Bit-line Sensing Method Using the Same - Google Patents

Abstract

A bit line sense amplifier driver capable of performing a high speed bit line sensing operation of a semiconductor memory device and a bit line sensing method using the same are provided.

The bit line sense amplifier driver of the present invention is connected between a sense amplifier ground line signal output terminal and a substrate bias voltage terminal, and in response to an input of a second enable signal, the sense amplifier ground line signal output terminal is connected to the substrate bias voltage terminal. It includes an auxiliary drive for connecting to.

According to the present invention, by rapidly increasing the voltage difference applied to a pair of bit lines, the bit line sensing operation can be performed at high speed, and when applied to a device requiring high speed operation, the overall performance of the device can be improved.

Bitline, Sense Amplifier Driver, Board Bias Voltage

Description

Bit-line Sense Amplifier Driver and Bit-line Sensing Method Using the Same}

1 is a circuit diagram of a general bit line sense amplifier driver,

2 is a circuit diagram of a typical memory cell and bit line sense amplifier;

3 is a timing diagram for explaining a general bit line sensing operation;

4 is a configuration diagram of a bit line sense amplifier driver according to an embodiment of the present invention;

FIG. 5 is a detailed circuit diagram of an embodiment of the voltage level fast transition unit and the main driver unit illustrated in FIG. 4;

6 is a detailed circuit diagram of an example of a pulse generator shown in FIG. 4;

7 is a timing diagram illustrating a bit line sensing operation using a bit line sense amplifier driver according to the present invention;

8 is a flowchart illustrating a bit line sensing method according to the present invention.

<Description of the symbols for the main parts of the drawings>

10: memory cell 20: sense amplifier

30: auxiliary drive unit 40: main drive unit

32: pulse generator 34: voltage level high speed transition unit

The present invention relates to a sense amplifier driver, and more particularly, to a bit line sense amplifier driver capable of performing a bit line sensing operation of a semiconductor memory device at high speed, and a bit line sensing method using the same.

In general, a memory cell block is composed of a plurality of memory cells comprising one transistor and one capacitor, and the memory cell is selected by a word line connected to the gate terminal of the transistor, and the memory cell block is selected from a capacitor connected to the drain terminal of the transistor. The sensing process is performed by amplifying the voltage applied to the source terminal.

A general bit line sensing process will be described with reference to FIGS. 1 to 3 as follows.

1 is a circuit diagram of a general bit line sense amplifier driver, FIG. 2 is a circuit diagram of a general memory cell and a bit line sense amplifier, and FIG. 3 is a timing diagram for explaining a general bit line sensing operation.

The bit line sense amplifier driver shown in FIG. 1 serves to generate a control signal for driving the bit line sense amplifier (20 in FIG. 2), and the bit line equalization signal bleq1 is high. In this case, the N-type transistors 102, 104, and 106 are turned on so that the voltages of the sense amplifier power line rto1 and the sense amplifier ground line sb1 become the first voltage VBLP, for example, 0.7V.

Thereafter, the bleq1 signal goes low at the first time T1 shown in FIG. 3, for example, 9 nsec, and the word line selection signal wl <1> at the second time T2, eg 10 nsec. When the power is turned high and the active operation is started, charge sharing is started to the bit line pairs bit1 and bit1b shown in FIG. 2.

Bit line sensing senses the amount of charge shared by the memory cell 10 on the bit line pair. For this purpose, the voltage applied to the bit line pairs bit1 and bit1b must be amplified. For example, the bit line sense amplifier driver enable signals sap1 and san1 are active at 16 nsec. The first bit line sense amplifier driver enable signal sap1 is applied low and the second bit line sense amplifier driver enable is enabled. The signal san1 is applied high.

Accordingly, the P-type transistor 108 and the N-type transistor 110 are each turned on so that the voltage level of the sense amplifier power line rto1 is changed from the first voltage to the second voltage by VCORE, for example, 1.4V. Transition In addition, the voltage applied to the sense amplifier ground line sb1 transitions from the first voltage to the ground voltage VSS.

The pair of potentials applied to the sense amplifier power line rto1 and the sense amplifier ground line sb1 is a power source of the sense amplifier 20 shown in FIG. 2, and the bit line pairs that start charge sharing at the second time T2 are performed. The sensing is performed by amplifying the voltage levels of (bit1, bit1b). As shown in FIG. 3, the actual sensing operation is a specified time from the third time T3 when the bit line sense amplifier driver enable signal is activated. For example, it can be seen that it is performed at 20.7 nsec, which is the fourth time T4 after 4.7 nsec has elapsed. This is because accurate sensing is achieved only when the difference between the voltage levels applied to the bit line pairs bit1 and bit1b is greater than or equal to a predetermined value, for example, 200 mV.

Therefore, after 4.7 nsec has elapsed since the bit line sense amplifier driver enable signals sap1 and san1 are active, the difference between the voltage levels applied to the bit line pairs bit1 and bit1b becomes 200 mV or more, so that Node 1 The voltage level of the sense amplifier power line rto1 (ie, VCORE) is applied to N1, and the voltage level of the sense amplifier ground line sb1 (ie, VSS) is applied to the node 2 N2.

As described above, the actual sensing operation is not performed immediately after the bit line sense amplifier driver enable signals sap1 and san1 are active, but requires time for applying charge to the bit line in the memory cell. As the number of memory devices increases, the number of unit memory cells connected to the bit line increases, so that the load on the bit line becomes high, and the sensing speed is delayed because it occurs after approximately 4.7 nsec has elapsed. There is a problem in reducing the overall operating speed in the device.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and senses by shifting the voltage applied to the ground line of the bit line sense amplifier below the ground voltage at high speed, thereby increasing the potential difference applied to the bit line pair at high speed. There is a technical problem to provide a bit line sense amplifier driver and a bit line sensing method using the same so that the operation can be performed at a high speed.

The present invention for achieving the above-described technical problem is controlled by the first and second enable signal and the bit line equalization signal, the sense amplifier power line signal and the sense amplifier ground line signal for driving the bit line sense amplifier A bit line sense amplifier driver, which is connected between the sense amplifier ground line signal output terminal and a substrate bias voltage terminal, wherein the sense amplifier ground line signal output terminal is connected to the substrate bias voltage in response to an input of the second enable signal. Auxiliary driver for connecting to the voltage terminal is provided.

In addition, the present invention is controlled by the first and second enable signal and the bit line equalization signal, the bit line sense amplifier for generating a sense amplifier power line signal and a sense amplifier ground line signal for driving the bit line sense amplifier A method for sensing a bit line of a semiconductor memory device by driving a bit line sense amplifier by a driver, wherein the bit line equalization signal is disabled, a word line is selected, and charge sharing is started on a pair of bit lines. Activating the first and second enable signals; Connecting the sense amplifier ground line signal output terminal and a ground terminal to each other by the second enable signal; Generating a pulse signal by the second enable signal to connect the sense amplifier ground line signal output terminal and a substrate bias voltage terminal while the pulse signal is held high; And allowing the sense amplifier ground line signal output terminal to maintain a ground voltage as the pulse signal transitions low.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a block diagram illustrating a bit line sense amplifier driver according to an embodiment of the present invention.

The bit line sense amplifier driver according to the present invention is controlled by the first and second bit line sense amplifier driver enable signals sap2 and san2 and the bit line equalization signal bleq2, and thus the bit line equalization signal bleq2. Is disabled and the first and second bit line sense amplifier driver enable signals sap2 and san2 are applied low and high, respectively, to sense amplifier power lines rto2 and sense amplifier ground lines sb2. A voltage for operating the power is applied, but the voltage applied to the sense amplifier ground line sb2 is changed to be equal to or less than the ground voltage at high speed, and then the ground voltage VSS is maintained.

More specifically, the bit line sense amplifier driver according to the present invention is controlled by the second bit line sense amplifier driver enable signal san2, so that the voltage applied to the sense amplifier ground line sb2 is grounded at high speed. It is controlled by the auxiliary driver 30 and the first bit line sense amplifier driver enable signal sap2 and the bit line equalization signal bleq2 for transitioning to the following and connected to the auxiliary driver 30 to sense amplifier power. The main driver 40 outputs a line signal rto2 and a sense amplifier ground line signal sb2.

In addition, the auxiliary driver 30 receives the second bit line sense amplifier driver enable signal san2 as an input, and generates a pulse generator 32 and a pulse generator 32 that generate a pulse signal san_pul that is maintained for a specified time. The voltage level fast transition section 34 for controlling the voltage applied to the sense amplifier ground line sb2 of the main driver 40 to be shifted below the ground voltage at high speed is controlled by the pulse signal generated by Equipped.

5 is a detailed circuit diagram of an example of the voltage level fast transition unit 34 and the main driver 40 shown in FIG. 4, and FIG. 7 is a bit line sensing operation using a bit line sense amplifier driver according to the present invention. It is a timing chart for explaining this.

As shown in FIG. 5, the main driver 40 according to the present invention is driven by the bit line equalization signal bleq2 and is connected between the first voltage signal input terminal VBLP and the first node N11. A second N-type transistor 404 driven by a 1 N-type transistor 402, a bit line equalization signal bleq2, and connected between a first voltage signal input terminal VBLP and a second node N12, The third N-type transistor 406, the power supply terminal VCORE and the first node N11 that are driven by the bit line equalization signal bleq2 and are connected between the first node N11 and the second node N12. A P-type transistor 408 connected between the third nodes N13 extending from the P-type transistor 408 and driven by the first bit line sense amplifier driver enable signal sap2 to output the sense amplifier power line signal rto2; A second node N14 extending from the second node N12 and a ground terminal VSS; Trad is driven by the sense amplifier driver enable signal (san2) comprise a first 4 N- type transistor 410 for outputting a sense amplifier signal ground line (sb2).

In addition, the voltage level fast transition unit 34 according to the present invention is driven by the output signal san_pul of the pulse generator 32, and the fourth node N14 of the main driver 40 and the substrate bias voltage terminal ( And a fifth N-type transistor 302 connected between the VBBs.

In the present invention, by connecting the source terminal of the fifth N-type transistor 302 of the voltage level fast transition unit 34 to the substrate bias voltage terminal VBB, the output signal (san_pul) of the pulse generator 32 When the fifth N-type transistor 302 is turned on, the voltage applied to the fourth node N14 drops rapidly below the ground voltage. Since the substrate bias voltage is lower than the ground voltage, for example, about −0.9 V, the fourth N-type transistor 410 is turned on by making the second bit line sense amplifier driver enable signal san2 active. When turned on together with the fifth N-type transistor 302, the current applied to the fourth node N14 by the voltage difference between the ground voltage and the substrate bias voltage is less than the ground terminal VSS, rather than the substrate bias voltage terminal VBB. This is because it is faster to side.

In this way, the voltage applied to the fourth node N14, that is, the voltage applied to the sense amplifier ground line sb2 activates the second bit line sense amplifier driver enable signal san2 and rapidly falls below the ground voltage. As the voltage drops, the difference with the voltage applied to the sense amplifier power line rto2 increases to a predetermined value (for example, 200 mV) or more. As a result, the voltage difference between the bit line bit1 and the bit line bar bit1b rapidly increases by more than a predetermined value, so that the sensing operation can be performed quickly.

More specifically described as follows.

In the bit line sense amplifier driver illustrated in FIG. 5, when the bit line equalization signal bleq2 is in a high state, the first to third N-type transistors 402, 404, and 406 are turned on to sense amplifier power lines rto2. And a first voltage VBLP (for example, 0.7V) are applied to the sense amplifier ground line sb2.

Thereafter, the bit line equalization signal bleq2 goes low at the first time T1 (eg, 9 nsec), and the word line selection signal wl <2 at the second time (T2; eg, 10 nsec). When &quot;) becomes high and the active operation starts, charge sharing is started on the bit line pairs bit1 and bit1b shown in FIG.

In addition, since the voltage applied to the bit line pairs bit1 and bit1b (refer to FIG. 2) must be amplified for bit line sensing, the bit line sense amplifier driver enable signal (3) (for example, 16 nsec) is used. The sap2 and san2 are activated, and the first bit line sense amplifier driver enable signal sap2 is applied low and the second bit line sense amplifier driver enable signal san2 is applied high.

Accordingly, since the P-type transistor 408 is turned on to apply the second voltage VCORE to the sense amplifier power line rto2, the voltage level of the sense amplifier power line rto2 is increased after the third time T3. It gradually rises from the first voltage to the second voltage by VCORE, for example 1.4V.

Meanwhile, as the second bit line sense amplifier driver enable signal san2 is enabled high, the fourth N-type transistor 410 is turned on, and the second bit line sense amplifier driver enable signal san2 is turned on. Of the voltage level fast transition section 34 by a pulse san_pul that occurs during a specified time (e.g., from the third time T3 to the fifth time T5; 3 nsec) when enabled high; The fifth N-type transistor 302 is turned on. In this case, since the substrate bias voltage VBB (for example, −0.9 V) is applied to the source terminal of the fifth N-type transistor 302, the current applied to the fourth node N14 is applied to the ground terminal VSS. Is induced to the substrate bias voltage terminal VBB at a higher rate than is induced to Accordingly, the voltage applied to the sense amplifier ground line sb2 drops rapidly to a voltage lower than the ground voltage VSS, and then transitions back to the ground voltage VSS level after the pulse signal san_pul is removed.

The potential applied to the sense amplifier power line rto2 and the sense amplifier ground line sb2 is used as a power source of the bit line sense amplifier 20 of FIG. 2, and is sensed by the voltage level fast transition unit 34 by the sense amplifier ground line. As the potential of sb2 drops rapidly below the ground voltage, the voltage applied to the bit line bar bit1b also drops rapidly, so that the potential difference between the bit line pairs bit1 and bit1b increases rapidly. In other words, when the potential of the sense amplifier ground line sb2 suddenly drops below the ground voltage (for example, −0.2 V), the voltage applied to the bit line bar bit1b also drops rapidly, thereby causing the bit line bit1 to fall. The potential difference between the bit line bar and bit1b extends beyond the potential difference required for sensing (eg, 200 mV), so that bit line sensing is started at the sixth time T6 (for example, 17.7 nsec).

Comparing FIG. 7 with FIG. 3, unlike the case in which sensing is started after 4.7 nsec has elapsed since the bit line sense amplifier driver enable signal has been activated, the case where the bit line sense amplifier driver according to the present invention is applied is 1.7. Sensing is started after nsec has elapsed, and it can be seen that the operation speed is significantly improved.

FIG. 6 is a detailed circuit diagram of an example of the pulse generator illustrated in FIG. 4.

As shown, the pulse generator 32 according to the present invention includes an inversion delay circuit 310 and a second bit line sense for inverting and delaying the second bit line sense amplifier driver enable signal san2 for a predetermined time. The driver driver enable signal san2 and the output signal of the inversion delay circuit 310 are input, and the logic circuit 320 outputs a high signal only when both input signals are high.

Here, the inversion delay circuit 310 can be configured by connecting an odd number of inverting elements in series. In addition, the logic circuit 320 inputs an output signal of the second bit line sense amplifier driver enable signal san2 and the inversion delay circuit 310 and outputs a low signal only when both input signals are high. A logic element (eg, a NAND gate) 322 and a second logic element 324 for inverting the output signal of the first logic element 322 may be configured.

The configuration of the pulse generator 32 is not limited to the configuration shown in FIG. 6, and any configuration can be adopted as long as it can generate a pulse for a specified time.

In addition, by controlling the delay time of the inversion delay circuit 310 of the pulse generator 32, it is possible to easily adjust the pulse signal generation time, that is, the time when the voltage below the ground voltage is applied to the sense amplifier ground line sb2. .

8 is a flowchart illustrating a bit line sensing method according to the present invention.

As shown, after the bit line equalization signal is disabled, the word line selection signal is enabled to start charge sharing on the bit line pair (S101).

Thereafter, the first and second bit line sense amplifier driver enable signals sap2 and san2 for driving the bit line sense amplifier driver for driving the sense amplifier are activated (S103). In this case, the first bit line sense amplifier driver enable signal sap2 is applied low and the second bit line sense amplifier driver enable signal san2 is applied high.

Next, the pulse generator 32 generates a pulse for maintaining a high state for a predetermined time (for example, 3 nsec) by inputting the second bit line sense amplifier driver enable signal san2 (S105). By inputting this to the voltage level fast transition unit 34, the voltage applied to the sense amplifier ground line sb2 drops rapidly below the ground voltage, and after the pulse is removed, the sense amplifier ground line sb2. Maintain this ground voltage. As a result, the voltage applied to the bit line bar bit1b also drops rapidly, so that the potential difference with the bit line bit1 rapidly increases (S107).

Here, the voltage level fast transition unit 34 is connected between the sense amplifier ground line sb2 and the substrate bias voltage terminal VBB, and the sense amplifier ground line when the voltage level fast transition unit 34 is driven by a pulse. The current induced at (sb2) is rapidly induced to the substrate bias voltage terminal (VBB) so that the voltage applied to the sense amplifier ground line (sb2) rapidly transitions below the ground voltage, and after the pulse is removed, the ground voltage is removed. Control to maintain.

In this way, the difference between the voltage applied to the sense amplifier ground line sb2 and the voltage applied to the sense amplifier power line rto2 is increased to a predetermined value (eg, 200 mV) or more. This consequently causes the voltage difference between the bit line bit1 and the bit line bar bit1b to rapidly increase beyond a certain value, thereby enabling the sensing operation to be started quickly.

In this way, the voltage by the sense amplifier power line is applied to the bit line bit1, and the voltage by the sense amplifier ground line is applied to the bit line bar bit1b to perform sensing (S109).

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

According to the present invention, the bit line sensing operation can be performed at high speed by rapidly increasing the voltage difference applied to the pair of bit lines. In addition, when the bit line sense amplifier driver is applied to a device requiring high speed operation, the overall performance of the device may be improved.

Claims (10)

A bit line sense amplifier driver controlled by first and second enable signals and a bit line equalization signal to generate a sense amplifier power line signal and a sense amplifier ground line signal for driving a bit line sense amplifier, An auxiliary driver connected between the sense amplifier ground line signal output terminal and a substrate bias voltage terminal and configured to connect the sense amplifier ground line signal output terminal to the substrate bias voltage terminal in response to an input of the second enable signal; And a bit line sense amplifier driver. The method of claim 1, The auxiliary driver may include a pulse generator configured to generate a pulse signal held for a predetermined time by receiving the second enable signal as an input; And A voltage level fast transition unit driven by a pulse signal generated by the pulse generator, for inducing a current of the sense amplifier ground line signal output terminal to the substrate bias voltage terminal; And a bit line sense amplifier driver. The method of claim 2, The voltage level high speed transition unit is driven by an output signal of the pulse generator, and includes a bit line sense amplifier connected between the sense amplifier ground line signal output terminal and the substrate bias voltage terminal. driver. The method of claim 2, The pulse generator may include an inversion delay circuit for inverting and delaying the second enable signal for a predetermined time; And A logic circuit for inputting the second enable signal and the output signal of the inversion delay circuit, and outputting a high signal only when both input signals are high; Bit line sense amplifier driver comprising a. The method of claim 4, wherein The inversion delay circuit is a bit line sense amplifier driver, characterized in that configured to connect an odd number of inverting elements in series. The method of claim 4, wherein The logic circuit may include a first logic device configured to output a low signal only when the input signal is high by inputting the second enable signal and the output signal of the inversion delay circuit; And A second logic element for inverting the output signal of the first logic element; Bit line sense amplifier driver comprising a. The method of claim 6, And the first logic element is a NAND gate. The method of claim 1, The auxiliary driver is connected to the main driver at the sense amplifier ground line signal output terminal, and the main driver is driven by the bit line equalization signal and is connected between the voltage signal input terminal and the first node. ; A second N-type transistor driven by the bit line equalization signal and connected between the voltage signal input terminal and a second node; A third N-type transistor driven by the bit line equalization signal and connected between the first node and the second node; A P-type transistor connected between a power supply terminal and a third node extending from the first node, the P-type transistor being driven by the first enable signal to output a sense amplifier power line signal; And A fourth N-type transistor connected between a fourth node extending from the second node and a ground terminal (VSS) and driven by the second enable signal to output a sense amplifier ground line signal; Bit line sense amplifier driver, characterized in that comprises a. The bit line is controlled by the first and second enable signals and the bit line equalization signal to generate a sense amplifier power line signal and a sense amplifier ground line signal for driving the bit line sense amplifier. A method for sensing a bit line of a semiconductor memory device by driving a sense amplifier, Activating the first and second enable signals after the bit line equalization signal is disabled and a word line is selected to initiate charge sharing on a pair of bit lines; Connecting the sense amplifier ground line signal output terminal and a ground terminal to each other by the second enable signal; Generating a pulse signal by the second enable signal to connect the sense amplifier ground line signal output terminal and a substrate bias voltage terminal while the pulse signal is held high; And Allowing the sense amplifier ground line signal output terminal to maintain a ground voltage as the pulse signal transitions low; Bit line sensing method comprising a. The method of claim 9, The step of connecting the sense amplifier ground line signal output terminal and the substrate bias voltage terminal is performed by using a transistor driven by the pulse signal and connected between the sense amplifier ground line signal output terminal and the substrate bias voltage terminal. Characterized in that the bit line sensing method.

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