KR20090131414A - Metal-oxide semiconductor field effect transistor and method of manufacturing the same - Google Patents

Abstract

PURPOSE: An MOSFET(Metal Oxide Semiconductor Field Effect Transistor) and a manufacturing method thereof are provided to improve reduction of a drain current by reducing source resistance through a source routing part of a stack structure. CONSTITUTION: Gate poly lines(G1~G4) are formed on a semiconductor substrate(100). Source regions(S1~S3) and drain regions(D1,D2) are formed to an active region of the semiconductor substrate. An interlayer insulation film is formed on the semiconductor substrate. A plurality of first via contacts is formed inside the interlayer insulation film corresponding to the source regions. A metal source routing part(140) has a stack structure, and includes a plurality of metal layers and an insulation film. The metal layers are formed on the interlayer insulation film. A plurality of second via contacts is formed to the insulation film.

Description

MOS transistor and method of manufacturing the same {Metal-oxide semiconductor field effect transistor and method of manufacturing the same}

The present invention relates to an apparatus for manufacturing a semiconductor device, and more particularly, to a radio frequency metal-oxide semiconductor field effect transistor (RF MOSFET).

RF-based metal-oxide semiconductor field effect transistors (MOSFETs) use multiple fingers rather than single gates to increase the maximum oscillation frequency (Fmax) or reduce noise caused by gate resistance. A multi-finger gate structure is used.

In general, a layout d of a RE MOS transistor having a multi-finger structure is formed on a semiconductor substrate, a gate polyline of a multi-finger structure formed on an active region of the semiconductor substrate, and a semiconductor substrate on one side of the gate polylines. Source regions, a drain region formed on the semiconductor substrate on the other side of the gate poly lines, a drain routing portion at which one end of each of the drain regions are interconnected, a gate routing portion at which one end of each of the gate poly lines are interconnected; And a source routing unit to which one end of each of the source regions is interconnected.

The drain current flowing with respect to the width of the unit gate polyline (ie, the unit finger) of the multi-finger structure is reduced. As the drain current decreases, errors in DC data and AC parameters may occur when using a core model of generic logic for modeling an RF MOS transistor, and performance degradation may occur due to a decrease in gain. The exact cause of the decrease in the drain current is not clear, but as the number of unit gate polylines in the multi-finger structure increases, the drain current may decrease, and the width of the metal source routing connecting all the source regions decreases. In this case, the resistance of the source regions is increased, which may reduce the drain current.

1 is a graph illustrating a reduction rate of drain current according to the number of general multi-fingers and the width of a unit finger. 2 represents the reduction rate (%), and the abscissa represents the number of unit fingers. Herein, the width of the unit finger may be a positive real number W1 to W4 and W1 <W2 <W3 <W4.

As the width of the metal source routing increases, the reduction of the drain current can be improved, but the parasitic capacitance between the source and the drain increases, which reduces the maximum oscillation frequency. It is limited to increasing the width of the metal source routing. There is.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a MOS transistor and a method of manufacturing the same, which can improve a reduction of drain current due to source routing.

According to an exemplary embodiment of the present invention, a MOS transistor includes gate polylines formed on a semiconductor substrate, source and drain regions formed on semiconductor substrates on both sides of the gate polylines, and the gate. An interlayer insulating layer formed on the semiconductor substrate on which the poly lines, the drain regions, and the source regions are formed, first via contacts formed in the interlayer insulating layer corresponding to the source regions, and an interlayer on which the first via contacts are formed And a metal source routing part having a stack structure including a plurality of stacked metal layers formed on the insulating layer and an insulating layer having a plurality of second via contacts formed between each of the plurality of metal layers.

The metal source routing part of the stack structure may include a first metal layer formed on the interlayer insulating layer, a source routing insulating layer formed on the first metal layer, and a source routing insulating layer formed on the source routing insulating layer to be electrically connected to the first via contacts. And a second metal layer and the plurality of second via contacts formed inside the source routing insulating layer to connect the first metal layer and the second metal layer. In this case, the second metal layer may be formed on the source routing insulating layer corresponding to the first metal layer to have the same cross-sectional area as the first metal layer.

According to another aspect of the present invention, there is provided a method of manufacturing a MOS transistor, the method including: forming gate polylines having a multi-finger structure on a semiconductor substrate; Forming a region, forming an interlayer insulating layer on the semiconductor substrate on which the gate poly lines, the drain regions, and the source regions are formed, and forming first via contacts in the interlayer insulating layer corresponding to the source regions. Forming a plurality of stacked metal layers on the interlayer insulating layer on which the first via contacts are formed, and forming an insulating layer including a plurality of second via contacts between each of the plurality of metal layers. Source routing forming step.

The source routing forming of the stack structure may include forming a first metal layer on the interlayer insulating layer to be electrically connected to the first via contacts, forming a source routing insulating layer on the first metal layer, and forming the source routing insulating layer on the first metal layer. Forming a plurality of second via contacts connected to the first metal layer in a routing insulating layer, and forming a second metal layer on a source routing insulating layer in which the plurality of second via contacts are formed. In this case, the forming of the second metal layer may be formed on the source routing insulating layer corresponding to the first metal layer so as to have the same cross-sectional area as the first metal layer.

The MOS transistor and the method of manufacturing the same according to the embodiment of the present invention have an effect of reducing the drain current by reducing the source resistance by routing by applying the source rounding part of the stack structure.

Hereinafter, the technical objects and features of the present invention will be apparent from the description of the accompanying drawings and the embodiments. Looking at the present invention in detail.

2A illustrates a layout of an RF MOS transistor according to an embodiment of the present invention. Referring to FIG. 2A, the layout of the RF MOS transistor includes a semiconductor substrate 100, gate polylines G1, G2, G3, and G4 of a multi-finger structure, and source regions S1, S2, and S3. , Drain regions D1 and D2, dummy patterns 110, 112, 114, and 116, drain routing part 120, gate routing part 130, and source routing part 140.

In general, the RF MOS transistor may be formed on the semiconductor substrate 100 of the dual ring structures 102 and 105.

The gate poly lines G1, G2, G3, and G4 have a multi-finger structure and are formed in an active region of the semiconductor substrate 110. For example, the first gate polyline G1 to the fourth gate polyline G4 may have a rod shape, and each gate polyline may be formed on the active area at regular intervals.

The source regions S1 to S3 and the drain regions D1 to D2 are formed in an active region of the semiconductor substrate 100, and the source region (eg, S1) is formed on the gate poly line (eg, G1). It may be formed in the active region on one side. The drain region (eg, D1) may be formed in the active region on the other side of the gate poly line (eg, G1).

That is, a source region is formed at one side and a drain region is formed at the other side based on each of the gate poly lines G1 to G4, and the source region or the drain region may be alternately formed. For example, a first source region S1 is formed in an adjacent semiconductor substrate on the left side based on the first gate polyline G1, a first drain region D1 is formed in an adjacent semiconductor substrate on the right side, and a second gate is formed. The first drain region D1 may be formed in the left semiconductor substrate based on the polyline G2, and the second source region S2 may be formed in the right semiconductor substrate.

Thus, the source region (eg, S1), the gate polyline G1, and the drain region D1 may form a layout of a series of RF MOS transistors. Dummy patterns 110, 112, 114, and 116 are formed in the active regions on both sides of the layout of the series of RF MOS transistors.

The drain routing unit 120 interconnects one end of each of the drain regions S1 to S3. The gate writing unit 130 interconnects one end of each of the gate poly lines G1 to G4.

The source routing unit 140 is positioned above the source regions S1, S2, and S3, and interconnects each of the source regions S1, S2, and S3.

The configuration of the source routing unit will be described in detail with reference to the cross-sectional view shown in FIG. 2B. FIG. 2B is a cross-sectional view of the layout of the RF MOS transistor illustrated in FIG. 2A taken along the AB direction.

Referring to FIG. 2B, as described above, the gate polylines G1 to G4, the drain regions D1 and D2, and the source regions S1, S2, and S3 of the multi-finger structure on the semiconductor substrate 110 are described above. Is formed.

For example, after the polysilicon is deposited on the semiconductor substrate 100, the polysilicon may be patterned through photolithography and etching to form gate polylines G1 to G4 having a multi-finger structure.

The drain regions D1 to D2 and the source regions S1, S2, and S3 may be formed by selectively implanting impurity ions into the semiconductor substrate 100 on both sides of each of the gate polylines. .

An interlayer insulating layer 310 is formed on the entire surface of the semiconductor substrate 100 on which the gate polylines G1 to G4, the drain regions D1 and D2, and the source regions S1, S2, and S3 of the multi-finger structure are formed. do.

Via contacts 311, 314, and 318 corresponding to each of the source regions S1, S2, and S3 are formed in the interlayer insulating layer 310. The interlayer insulating layer 310 may be a multilayer insulating layer (not shown), and may include at least one via contact (eg, 311, 314, 318) corresponding to each of the source regions S1, S2, and S3, and at least One metal wire 312 and 316 may be included.

The interlayer insulating layer 310 may be formed using a general deposition method, and the via contact may be formed by a general contact hole and a contact plug forming method.

A first metal layer 320 (referred to as a “first source routing part”) that is electrically connected to the via contacts 311, 314, and 318 is formed on the interlayer insulating layer 310. The source regions may be connected to each other by the first source routing unit 320.

An insulating layer 330 (eg, an oxide layer or a nitride layer) is formed on the first source routing part 320. A plurality of via contacts 335 are formed in the insulating layer 330.

A second metal layer 340 (referred to as a “second source routing unit”) is formed on the insulating layer 330 on which the plurality of via contacts 335 are formed. The second source routing unit 340 is connected to the first source routing unit 320 through the via contacts 335.

In general, the saturation drain current of a MOSFET is greatly affected by the source and drain resistances, especially the source resistance. In other words, when the source resistance is reduced, the saturation drain current reduction rate may be improved. For example, the drain current degradation rate of the RF MOS transistor may be improved by reducing the resistance of the source routing portion where the source regions are interconnected in the layout of the RF MOS transistor.

The embodiment of the present invention proposes a source routing portion of a stack structure to reduce the resistance of the source routing portion of the layout of the RF MOS transistor.

As shown in FIG. 2B, first, gate poly lines (eg, G1 to G4) having a multi-finger structure are formed on the semiconductor substrate 100. Source regions (eg, S1 to S3) and drain regions (eg, D1 and D2) are formed in the semiconductor substrate 100 at both sides of the gate poly lines (eg, G1 to G4). Next, an interlayer insulating layer 310 is formed on the semiconductor substrate on which the gate poly lines (eg, G1 to G4), the drain regions (eg, D1 and D2), and the source regions (eg, S1 to S3) are formed. Form.

Next, first via contacts 311, 314, and 318 are formed in the interlayer insulating layer 310 to correspond to the source regions (eg, S1 to S3). In this case, the first via contacts 311, 314, and 318 may be connected to the metal wires 312 and 316 formed in the interlayer insulating layer 310.

A plurality of stacked metal layers (eg, 320 and 340) are formed on the interlayer insulating layer 310 on which the first via contacts 311, 314, and 318 are formed, and between each of the plurality of metal layers 320 and 340. A source routing insulating layer 330 including a plurality of second via contacts 335 is formed therein.

For example, a first metal layer 320 is formed on the interlayer insulating layer 310 to be electrically connected to the first via contacts 311, 314, and 318, and source routing insulation is formed on the first metal layer 320. Form layer 330.

The plurality of second via contacts 335 may be metal plugs formed in the via holes. However, the plurality of second via contacts 335 may be trench-type contacts (not shown) in which metal is embedded in trenches (not shown) formed in the source routing insulating layer.

When the source routing part is formed in the stack structure as described above, the source resistance can be reduced. For example, the first source routing unit 320, the insulating layer 330, and the plurality of via contacts 335 may be compared to the case of implementing the source routing unit of the RF MOS transistor using only the first source routing unit 320. And a source routing unit having a stack structure including the second source routing unit 340 reduce the overall resistance of the source regions.

Therefore, when the source routing portion of the stack structure illustrated in FIG. 2B is applied to the layout of the RF MOS transistor, the resistance of the source region due to the routing is reduced, so that the drain current may be reduced. In addition, since the stack structure does not change the cross-sectional area of the source routing portion, the parasitic capacitance between the source region and the drain region is not affected. Therefore, the use of stacked source routing does not affect the maximum oscillation frequency of the RF MOSFET.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a graph illustrating a reduction rate of drain current according to the number of general multi-fingers and the width of a unit finger.

2A illustrates a layout of an RF MOS transistor according to an embodiment of the present invention.

FIG. 2B is a cross-sectional view of the layout of the RF MOS transistor illustrated in FIG. 2A taken along the AB direction.

<Explanation of symbols for the main parts of the drawings>

100: semiconductor substrate, 110, 112, 114, 116: dummy patterns,

120: drain routing section, 130: gate routing section,

310: interlayer insulating film, 320: first metal layer,

311, 314, 318: first via contacts, 330: source routing insulation layer,

335: second via contacts, 340: second metal layer.

Claims (6)

Gate poly lines formed on the semiconductor substrate; Source and drain regions formed on the semiconductor substrate on both sides of the gate poly lines; An interlayer insulating layer formed on the semiconductor substrate on which the gate poly lines, the drain regions, and the source regions are formed; First via contacts formed in the interlayer insulating layer corresponding to the source regions; And And a metal source routing part having a stack structure including a plurality of stacked metal layers formed on the interlayer insulating layer on which the first via contacts are formed, and an insulating layer on which a plurality of second via contacts are formed between each of the plurality of metal layers. MOS transistor. The method of claim 1, wherein the metal source routing portion of the stack structure, A first metal layer formed on the interlayer insulating layer to be electrically connected to the first via contacts; A source routing insulation layer formed on the first metal layer; A second metal layer formed on the source routing insulating layer; And And the plurality of second via contacts formed inside the source routing insulating layer to connect the first metal layer and the second metal layer. The method of claim 2, wherein the second metal layer, And the source routing insulating layer corresponding to the first metal layer to have the same cross-sectional area as the first metal layer. Forming gate polylines of a multi-pinker structure on the semiconductor substrate; Forming a source region and a drain region in the semiconductor substrate on both sides of the gate poly lines; Forming an interlayer insulating layer on the semiconductor substrate on which the gate poly lines, the drain regions, and the source regions are formed; Forming first via contacts in the interlayer insulating layer corresponding to the source regions; And Forming a plurality of stacked metal layers on the interlayer insulating layer on which the first via contacts are formed, and forming a source routing of a stack structure to form an insulating layer including a plurality of second via contacts between each of the plurality of metal layers; MOS transistor manufacturing method comprising. The method of claim 4, wherein the source routing forming step of the stack structure comprises: Forming a first metal layer on the interlayer insulating layer to be electrically connected to the first via contacts; Forming a source routing insulating layer on the first metal layer; Forming a plurality of second via contacts connected to the first metal layer in the source routing insulating layer; And Forming a second metal layer on the source routing insulating layer having the plurality of second via contacts formed thereon. The method of claim 5, wherein the forming of the second metal layer comprises: And the source routing insulating layer corresponding to the first metal layer to have the same cross-sectional area as the first metal layer.

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