KR20090128912A - Method for forming recess gate of semiconductor device - Google Patents

Method for forming recess gate of semiconductor device Download PDF

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KR20090128912A
KR20090128912A KR1020080054892A KR20080054892A KR20090128912A KR 20090128912 A KR20090128912 A KR 20090128912A KR 1020080054892 A KR1020080054892 A KR 1020080054892A KR 20080054892 A KR20080054892 A KR 20080054892A KR 20090128912 A KR20090128912 A KR 20090128912A
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forming
film
gate
substrate
etching
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KR1020080054892A
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Korean (ko)
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KR101016351B1 (en
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차한섭
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매그나칩 반도체 유한회사
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Priority to KR1020080054892A priority Critical patent/KR101016351B1/en
Priority to CN2009101407781A priority patent/CN101604628B/en
Priority to CN201110308347.9A priority patent/CN102361011B/en
Priority to US12/468,325 priority patent/US8557694B2/en
Priority to JP2009131810A priority patent/JP5506248B2/en
Publication of KR20090128912A publication Critical patent/KR20090128912A/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66613Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356Disposition, e.g. buried gate electrode
    • H01L29/4236Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE: A method for forming recess a gate of a semiconductor device is provided to weaken the intensity of electric field focused on the top corner by forming a trench through a vapor etching using hydrogen chloride gas. CONSTITUTION: In a device, an element isolation film(102) is formed in a substrate(100A). A buffer layer(104A) is formed on the substrate. A photosensitive pattern is formed on the buffer layer. The buffer layer is etched through an etching process, and the photosensitive pattern is removed. A trench(108) is formed through the etching process, and the buffer layer is removed through etching process. A gate insulating layer is formed along the inner surface of a trench on the substrate. A conductive film is formed on the gate insulating layer. The gate electrode is formed by etching the conductive film and gate insulating layer. The source and drain region are formed within the substrate exposed to the both sides of the gate electrode.

Description

반도체 소자의 리세스 게이트 형성방법{METHOD FOR FORMING RECESS GATE OF SEMICONDUCTOR DEVICE}Recess gate formation method of a semiconductor device {METHOD FOR FORMING RECESS GATE OF SEMICONDUCTOR DEVICE}

본 발명은 반도체 제조 기술에 관한 것으로, 특히 다면 채널을 갖는 트랜지스터의 게이트 형성방법, 더욱 상세하게는 리세스(recess) 게이트 형성방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing techniques, and more particularly, to a method of forming a gate of a transistor having a multi-sided channel, and more particularly, a method of forming a recess gate.

최근에는 반도체 소자의 고집적화가 높아짐에 따라 트랜지스터의 채널 길이는 감소하고 소오스 및 드레인의 농도는 점차 증가하고 있다. 이로 인해 소오스와 드레인 간에 간섭이 심해져 문턱전압이 감소하고, 누설전류가 증가하는 단채널 효과가 발생하게 된다. 이러한 단채널 효과를 억제하기 위해 다면 채널을 갖는 트랜지스터 중 하나인 리세스 게이트형 트랜지스터에 대한 연구가 활발히 진행되고 있다. In recent years, as the integration of semiconductor devices increases, the channel length of transistors decreases and the source and drain concentrations gradually increase. As a result, the interference between the source and the drain is severe, resulting in a short channel effect in which the threshold voltage is reduced and the leakage current is increased. In order to suppress such short channel effects, researches on recessed gate transistors, which are one of transistors having multiple channels, are being actively conducted.

리세스 게이트형 트랜지스터 형성방법을 살펴보면, 먼저 채널영역의 기판을 일정 깊이 식각하여 트렌치(trench)를 형성한 후 그 내부면을 따라 게이트 절연막 을 형성한다. 그런 다음, 트렌치가 매립되도록 게이트 절연막 상에 게이트를 형성한다. 이러한 구조에서는 소오스 및 드레인 간의 간섭이 억제되어 전기적 특성이 크게 개선된다. Referring to a method of forming a recessed gate transistor, first, a trench is formed by etching a substrate of a channel region to a predetermined depth, and then a gate insulating layer is formed along an inner surface thereof. Then, a gate is formed on the gate insulating film to fill the trench. In such a structure, interference between the source and the drain is suppressed, thereby greatly improving the electrical characteristics.

그러나, 리세스 게이트형 트랜지스터 형성방법에서는 기판을 플라즈마 식각(plasma etch)공정을 이용하여 식각하기 때문에 채널이 형성될 영역에 플라즈마에 기인한 손상이 발생되어 적층결함(stacking fault)과 같은 결정결함(crystal defect)이 발생하게 된다. 이로 인해, 계면 포획 밀도(interface trap density)가 높아지게 된다. 또한, 플라즈마 식각공정의 특성상 표면 거칠기가 열화되게 된다. 뿐만 아니라 기판을 식각하여 트렌치를 형성하고 나면 상부 모서리 부분이 날카롭게 형성되고, 이 부분에 전기장(electric field)이 집중되어 소자 특성 및 신뢰성이 열화된다. However, in the recess gate type transistor forming method, since the substrate is etched by using a plasma etch process, damage due to plasma is generated in the region where the channel is to be formed, and thus crystal defects such as stacking faults ( crystal defects occur. As a result, the interface trap density becomes high. In addition, the surface roughness is deteriorated due to the characteristics of the plasma etching process. In addition, after the substrate is etched to form a trench, an upper edge portion is sharply formed, and an electric field is concentrated in this portion, thereby degrading device characteristics and reliability.

따라서, 본 발명은 종래기술에 따른 문제점을 해결하기 위해 제안된 것으로서, 다음과 같은 목적들이 있다. Therefore, the present invention has been proposed to solve the problems according to the prior art, and has the following objects.

첫째, 본 발명은 플라즈마 식각공정에 의해 발생되는 소자 특성 및 신뢰성 열화를 방지할 수 있는 반도체 소자의 리세스 게이트 형성방법을 제공하는데 그 목적이 있다. First, an object of the present invention is to provide a method of forming a recess gate of a semiconductor device capable of preventing deterioration of device characteristics and reliability caused by a plasma etching process.

둘째, 본 발명은 플라즈마 식각공정에 의해 발생되는 상부 모서리 부위에서의 전계 집중 현상을 방지할 수 있는 반도체 소자의 리세스 게이트 형성방법을 제공하는데 다른 목적이 있다.Second, another object of the present invention is to provide a method of forming a recess gate of a semiconductor device capable of preventing an electric field concentration phenomenon at an upper edge portion generated by a plasma etching process.

상기한 목적을 달성하기 위한 일 측면에 따른 본 발명은, 증기식각공정으로 기판을 일부 식각하여 트렌치를 형성하는 단계와, 상기 트렌치 내부면을 따라 상기 기판 상에 게이트 절연막을 형성하는 단계와, 상기 게이트 절연막 상에 도전막을 형성하는 단계와, 상기 도전막과 상기 게이트 절연막을 식각하여 게이트 전극을 형성하는 단계를 포함하는 반도체 소자의 리세스 게이트 형성방법을 제공한다.According to an aspect of the present invention, there is provided a method of forming a trench by partially etching a substrate by a vapor etching process, forming a gate insulating layer on the substrate along an inner surface of the trench, and A method of forming a recess gate in a semiconductor device includes forming a conductive layer on a gate insulating layer, and forming a gate electrode by etching the conductive layer and the gate insulating layer.

또한, 상기한 목적을 달성하기 위한 다른 측면에 따른 본 발명은, 기판 상에 완충막이 형성된 기판을 준비하는 단계와, 상기 완충막을 일부 식각하여 상기 기판을 노출시키는 단계와, 상기 완충막을 식각 장벽층으로 이용한 증기식각공정으로 상기 기판을 일부 식각하여 트렌치를 형성하는 단계와, 상기 완충막을 제거하는 단계와, 상기 트렌치 내부면을 따라 상기 기판 상에 게이트 절연막을 형성하는 단계와, 상기 게이트 절연막 상에 도전막을 형성하는 단계와, 상기 도전막과 상기 게이트 절연막을 식각하여 게이트 전극을 형성하는 단계를 포함하는 반도체 소자의 리세스 게이트 형성방법을 제공한다.According to another aspect of the present invention, there is provided a method of preparing a substrate including a buffer layer on a substrate, partially etching the buffer layer to expose the substrate, and etching the buffer layer as an etch barrier layer. Forming a trench by partially etching the substrate using a vapor etching process, removing the buffer layer, forming a gate insulating layer on the substrate along an inner surface of the trench, and forming a trench on the gate insulating layer A method of forming a recess gate in a semiconductor device includes forming a conductive layer and forming a gate electrode by etching the conductive layer and the gate insulating layer.

바람직하게, 상기 증기식각공정은 염화수소(HCl) 또는 염소(Cl2)를 사용하여 실시한다. Preferably, the steam etching process is performed using hydrogen chloride (HCl) or chlorine (Cl 2 ).

바람직하게, 상기 증기식각공정은 600~1100℃의 온도에서 실시한다.Preferably, the steam etching process is carried out at a temperature of 600 ~ 1100 ℃.

바람직하게, 상기 증기식각공정은 0.01~760Torr의 압력에서 실시한다.Preferably, the steam etching process is carried out at a pressure of 0.01 ~ 760 Torr.

바람직하게, 상기 완충막은 산화공정 또는 증착공정으로 형성한다.Preferably, the buffer film is formed by an oxidation process or a deposition process.

바람직하게, 상기 완충막은 열 산화막 또는 TEOS(Tetra Ethyle Ortho Silicate)막으로 형성한다. Preferably, the buffer film is formed of a thermal oxide film or a TEOS (Tetra Ethyle Ortho Silicate) film.

상기한 구성을 포함하는 본 발명에 의하면, 다음과 같은 효과들을 얻을 수 있다. According to the present invention including the above-described configuration, the following effects can be obtained.

첫째, 본 발명에 의하면, 리세스 게이트 형성방법에 있어서, 증기식각공정으로 트렌치를 형성함으로써 플라즈마에 의한 손상이 없어 소자의 특성 및 신뢰성을 개선시킬 수 있다.First, according to the present invention, in the recess gate forming method, since the trench is formed by the vapor etching process, there is no damage caused by plasma, thereby improving the characteristics and reliability of the device.

둘째, 본 발명에 의하면, 리세스 게이트 형성방법에 있어서, 염화수소(HCl) 가스를 이용한 증기식각공정으로 트렌치를 형성함으로써, 염화수소(HCl) 증기식각공정 특성상 트렌치의 '111'면과 '110'면이 노출되어, 단면 구조상 45°에 가까운 경사면이 형성되고, 이로 인해 상부 모서리부위에 집중되는 전기장의 세기를 약화시킬 수 있다. Second, according to the present invention, in the recess gate forming method, the trench is formed by a vapor etching process using hydrogen chloride (HCl) gas, and thus the '111' and '110' planes of the trench are in view of the hydrogen chloride (HCl) vapor etching process. This exposure results in the formation of an inclined surface close to 45 ° in cross-sectional structure, thereby weakening the strength of the electric field concentrated at the upper edge portion.

이하에서는, 본 발명의 가장 바람직한 실시예를 첨부한 도면을 참조하여 설명한다. 또한, 도면들에 있어서, 층 및 영역들의 두께와 간격은 설명의 편의와 명확성을 기하기 위하여 과장되어진 것이며, 층이 다른 층, 영역 또는 기판 '상' 또는 '상부'에 있다고 언급되어지는 경우에 그것은 다른 층, 영역 또는 기판 상에 직접 형성될 수 있거나, 또는 그들 사이에 제3의 층이 개재될 수도 있다. 또한, 명세서 전체에 걸쳐서 동일한 도면번호로 표시된 부분은 동일한 층을 나타내며, 각 도면번호에 영문을 포함하는 경우 동일층이 식각 또는 연마공정 등을 통해 일부가 변형된 것을 의미한다. Hereinafter, with reference to the accompanying drawings, the most preferred embodiment of the present invention will be described. In addition, in the drawings, the thicknesses and spacings of layers and regions are exaggerated for ease of explanation and clarity, and where layers are referred to as being on or above other layers, regions or substrates. It may be formed directly on another layer, region or substrate, or a third layer may be interposed therebetween. In addition, the parts denoted by the same reference numerals throughout the specification represent the same layer, and when the reference numerals include the English, it means that the same layer is partially modified through an etching or polishing process.

실시예Example

도 1a 내지 도 1f는 본 발명의 실시예에 따른 반도체 소자의 리세스 게이트 형성방법을 도시한 공정 단면도이다. 1A to 1F are cross-sectional views illustrating a method of forming a recess gate of a semiconductor device in accordance with an embodiment of the present invention.

먼저, 도 1a에 도시된 바와 같이, STI(Shallow Trench Isolation) 공정을 실시하여 기판(100) 내에 소자 분리막(102)을 형성한 후 기판(100) 상에 완충막(104) 을 형성한다. 이때, 완충막(104)은 산화막으로 형성한다. 바람직하게는 실리콘산화막(SiO2)으로 형성한다. 더욱 바람직하게는 열 산화막 또는 TEOS(Tetra Ethyle Ortho Silicate)막으로 형성한다. 완충막(104)은 산화공정 또는 증착공정으로 형성한다. 산화공정의 경우 건식산화 또는 습식산화공정을 포함한다. 증착공정의 경우 CVD(Chemical Vapor Deposition) 공정 또는 PVD(Physical Vapor Deposition) 공정을 포함한다. First, as shown in FIG. 1A, a device isolation layer 102 is formed in the substrate 100 by performing a shallow trench isolation (STI) process, and then a buffer layer 104 is formed on the substrate 100. At this time, the buffer film 104 is formed of an oxide film. Preferably it is formed of a silicon oxide film (SiO 2 ). More preferably, it is formed of a thermal oxide film or a TEOS (Tetra Ethyle Ortho Silicate) film. The buffer film 104 is formed by an oxidation process or a deposition process. Oxidation processes include dry or wet oxidation processes. The deposition process includes a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) process.

이어서, 도 1b에 도시된 바와 같이, 완충막(104) 상에 감광막 패턴(106)을 형성한다. Subsequently, as illustrated in FIG. 1B, a photosensitive film pattern 106 is formed on the buffer film 104.

이어서, 감광막 패턴(106)을 식각 마스크로 이용한 식각공정을 실시하여 완충막(104A)을 식각한다. 이로써, 리세스 게이트가 일부 매립될 트렌치 영역이 정의된다. Subsequently, an etching process using the photosensitive film pattern 106 as an etching mask is performed to etch the buffer film 104A. As a result, a trench region in which the recess gate is partially embedded is defined.

이어서, 도 1c에 도시된 바와 같이, 감광막 패턴(106, 도 1b참조)을 제거한다.Subsequently, as shown in FIG. 1C, the photoresist pattern 106 (see FIG. 1B) is removed.

이어서, 도 1d에 도시된 바와 같이, 완충막(104A)을 식각 장벽층으로 이용한 식각공정을 실시하여 트렌치(108)를 형성한다. 이때, 식각공정은 증기식각(vapor etching)공정으로 실시한다. 즉, 플라즈마를 사용하지 않고 기체 상태의 화학물질을 이용하여 식각한다. 증기식각공정은 화학반응에 의한 식각이므로 선택성이 매우 우수하고 플라즈마에 의한 손상이 없으며, 등방성 식각이 가능하다. 또한, 습식식각과 같은 특성을 갖지만 용액을 사용하지 않으므로 쉽게 한 장비 내에서 RIE(Reactive Ion beam Etching) 반응관과 증기식각 반응관을 조합할 수 있는 이점도 있다. 예컨대, 증기식각공정은 식각가스로 염화수소(HCl) 또는 염소(Cl2) 가스를 사용하며, 600~1100℃의 온도에서 0.01~760Torr의 압력에서 실시한다. 이때, 온도 열원은 할로겐 램프(halogen ramp)를 이용한 RTP(Rapid Temperature Process) 방식을 사용하거나 히터(heater)를 사용할 수도 있다.Subsequently, as shown in FIG. 1D, the trench 108 is formed by performing an etching process using the buffer film 104A as an etching barrier layer. In this case, the etching process is performed by a vapor etching process. That is, etching is performed using chemical substances in the gas state without using plasma. Since the steam etching process is etching by chemical reaction, the selectivity is very excellent, there is no damage by plasma, and isotropic etching is possible. In addition, since it has the same properties as wet etching, but does not use a solution, there is an advantage in that it is possible to easily combine a reactive ion beam etching (RIE) reaction tube and a steam etching reaction tube in one equipment. For example, the steam etching process uses hydrogen chloride (HCl) or chlorine (Cl 2 ) gas as an etching gas, and is performed at a pressure of 0.01 to 760 Torr at a temperature of 600 to 1100 ° C. In this case, the temperature heat source may use a rapid temperature process (RTP) method using a halogen lamp or use a heater.

이어서, 도 1e에 도시된 바와 같이, 완충막(104A, 도 1d참조)을 식각하여 제거한다. 이때, 식각공정은 BOE 용액(Buffered Oxide Etchant, HF와 NH4F가 혼합된 용액) 또는 DHF 용액(Diluted HF, H20로 희석된 HF용액)을 사용하여 실시할 수 있다. Subsequently, as shown in FIG. 1E, the buffer film 104A (see FIG. 1D) is etched and removed. In this case, the etching process may be performed using a BOE solution (Buffered Oxide Etchant, a solution of HF and NH 4 F mixed) or a DHF solution (Diluted HF, HF solution diluted with H 2 O).

이어서, 트렌치(108, 도 1d참조)의 내부면을 따라 기판(100A) 상에 게이트 절연막(110)을 형성한다. 이때, 게이트 절연막(110)은 실리콘산화막(SiO2)으로 형성한다. 이러한 게이트 절연막(110)은 산화공정, 예컨대 건식산화, 습식산화 또는 라디컬 이온(radical ion)을 이용한 산화공정으로 형성한다. 또한, 게이트 절연막(110)은 실리콘산화막과 기판(100A) 간의 계면에 질화층이 형성된 구조로 형성할 수도 있다. Next, a gate insulating layer 110 is formed on the substrate 100A along the inner surface of the trench 108 (see FIG. 1D). In this case, the gate insulating layer 110 is formed of a silicon oxide film (SiO 2 ). The gate insulating layer 110 is formed by an oxidation process, for example, an oxidation process using dry oxidation, wet oxidation, or radical ions. In addition, the gate insulating layer 110 may be formed in a structure in which a nitride layer is formed at an interface between the silicon oxide film and the substrate 100A.

이어서, 게이트 절연막(110) 상에 도전막(112)을 형성한다. 이때, 도전막(112)은 다결정실리콘막으로 형성하거나, 전이금속들 중 어느 하나로 형성할 수 있다. Subsequently, a conductive film 112 is formed on the gate insulating film 110. In this case, the conductive film 112 may be formed of a polysilicon film or any one of transition metals.

이어서, 도 1f에 도시된 바와 같이, 도전막(112A)과 게이트 절연막(110A)을 식각하여 게이트 전극을 형성한다.Subsequently, as illustrated in FIG. 1F, the conductive film 112A and the gate insulating film 110A are etched to form a gate electrode.

이어서, 이온주입공정을 실시하여 상기 게이트 전극의 양측으로 노출되는 기판(100A) 내에 소오스 및 드레인 영역(114, 116)을 형성한다.Subsequently, an ion implantation process is performed to form source and drain regions 114 and 116 in the substrate 100A exposed to both sides of the gate electrode.

이어서, 상기 게이트 전극의 양측벽에 스페이서(118)를 형성한다. 이때, 스페이서(118)은 산화막, 질화막 또는 산화막과 질화막이 적층된 적층막으로 형성한다. Subsequently, spacers 118 are formed on both sidewalls of the gate electrode. In this case, the spacer 118 is formed of an oxide film, a nitride film, or a laminated film in which an oxide film and a nitride film are stacked.

이상에서 설명한 바와 같이, 본 발명의 기술적 사상은 바람직한 실시예에서 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며, 그 제한을 위한 것이 아님을 주의하여야 한다. 이렇듯, 이 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예들이 가능함을 이해할 수 있을 것이다.As described above, although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not for the purpose of limitation. As such, those skilled in the art may understand that various embodiments are possible within the scope of the technical idea of the present invention.

도 1a 내지 도 1f는 본 발명의 실시예에 따른 반도체 소자의 리세스 게이트 형성방법을 도시한 공정 단면도.1A to 1F are cross-sectional views illustrating a method of forming a recess gate of a semiconductor device in accordance with an embodiment of the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

100 : 기판100: substrate

102 : 소자 분리막102: device isolation film

104 : 완충막104: buffer membrane

106 : 감광막 패턴106: photosensitive film pattern

108 : 트렌치108: trench

110 : 게이트 절연막110: gate insulating film

112 : 도전막112: conductive film

114 ; 소오스 영역114; Source area

116 : 드레인 영역116: drain region

118 : 스페이서118: spacer

Claims (7)

증기식각공정으로 기판을 일부 식각하여 트렌치를 형성하는 단계;Forming a trench by partially etching the substrate by a vapor etching process; 상기 트렌치 내부면을 따라 상기 기판 상에 게이트 절연막을 형성하는 단계;Forming a gate insulating film on the substrate along the inner surface of the trench; 상기 게이트 절연막 상에 도전막을 형성하는 단계; 및Forming a conductive film on the gate insulating film; And 상기 도전막과 상기 게이트 절연막을 식각하여 게이트 전극을 형성하는 단계Etching the conductive layer and the gate insulating layer to form a gate electrode 를 포함하는 반도체 소자의 리세스 게이트 형성방법.Recess gate forming method of a semiconductor device comprising a. 기판 상에 완충막이 형성된 기판을 준비하는 단계;Preparing a substrate on which a buffer film is formed; 상기 완충막을 일부 식각하여 상기 기판을 노출시키는 단계;Partially etching the buffer film to expose the substrate; 상기 완충막을 식각 장벽층으로 이용한 증기식각공정으로 상기 기판을 일부 식각하여 트렌치를 형성하는 단계;Forming a trench by partially etching the substrate by a vapor etching process using the buffer layer as an etching barrier layer; 상기 완충막을 제거하는 단계;Removing the buffer film; 상기 트렌치 내부면을 따라 상기 기판 상에 게이트 절연막을 형성하는 단계;Forming a gate insulating film on the substrate along the inner surface of the trench; 상기 게이트 절연막 상에 도전막을 형성하는 단계; 및Forming a conductive film on the gate insulating film; And 상기 도전막과 상기 게이트 절연막을 식각하여 게이트 전극을 형성하는 단계Etching the conductive layer and the gate insulating layer to form a gate electrode 를 포함하는 반도체 소자의 리세스 게이트 형성방법.Recess gate forming method of a semiconductor device comprising a. 제 1 항 또는 제 2 항에 있어서, The method according to claim 1 or 2, 상기 증기식각공정은 염화수소(HCl) 또는 염소(Cl2)를 사용하여 실시하는 반도체 소자의 리세스 게이트 형성방법.The vapor etching process is a method of forming a recess gate of a semiconductor device using hydrogen chloride (HCl) or chlorine (Cl 2 ). 제 3 항에 있어서, The method of claim 3, wherein 상기 증기식각공정은 600~1100℃의 온도에서 실시하는 반도체 소자의 리세스 게이트 형성방법.The vapor etching process is a recess gate forming method of a semiconductor device performed at a temperature of 600 ~ 1100 ℃. 제 4 항에 있어서, The method of claim 4, wherein 상기 증기식각공정은 0.01~760Torr의 압력에서 실시하는 반도체 소자의 리세스 게이트 형성방법.The vapor etching process is a recess gate forming method of a semiconductor device performed at a pressure of 0.01 ~ 760 Torr. 제 2 항에 있어서, The method of claim 2, 상기 완충막은 산화공정 또는 증착공정으로 형성하는 반도체 소자의 리세스 게이트 형성방법.The buffer film is a method of forming a recess gate of a semiconductor device formed by an oxidation process or a deposition process. 제 6 항에 있어서, The method of claim 6, 상기 완충막은 열 산화막 또는 TEOS(Tetra Ethyle Ortho Silicate)막으로 형성하는 반도체 소자의 리세스 게이트 형성방법.The buffer film is a method of forming a recess gate of a semiconductor device formed of a thermal oxide film or a TEOS (Tetra Ethyle Ortho Silicate) film.
KR1020080054892A 2008-06-11 2008-06-11 Method for forming recess gate of semiconductor device KR101016351B1 (en)

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CN201110308347.9A CN102361011B (en) 2008-06-11 2009-05-15 The method forming the grid of semiconductor device
US12/468,325 US8557694B2 (en) 2008-06-11 2009-05-19 Method for forming gate of semiconductor device
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