KR20090125677A - Supporting substrates for semiconductor light emitting device and high-performance vertical structured semiconductor light emitting devices using supporting substrates - Google Patents

Abstract

PURPOSE: A supporting substrate for a semiconductor light emitting device and a semiconductor light emitting device with high performance vertical structure are provided to improve chip yield and productivity, by using a wet etching process in a single chip process. CONSTITUTION: A selected supporting substrate formed with a predetermined material is prepared. A sacrificial layer is stacked on the top of the supporting substrate. A heat sink layer is stacked on the top of the sacrificial layer. A bonding layer is stacked on the top of the heat sink layer. The difference of a thermal expansion coefficient between the selected supporting substrate and an initial growth substrate is below 2ppm. The thickness of the heat sink layer is below 0.1 micron meter or 500 micron meter.

Description

Supporting substrates for semiconductor light emitting device and high-performance vertical structured semiconductor light emitting devices using supporting substrates}

The present invention is a "prepared supporting substrate (hereinafter referred to as" PSS ") used in the manufacture of a high-performance vertical light emitting device using a multi-layer light emitting structure thin film composed of a group 3-5 nitride-based semiconductor, The present invention relates to a light emitting device having a high performance vertical structure manufactured using the PSS and a method of manufacturing the same.

More specifically, in a group 3-5 nitride-based semiconductor light emitting device having an vertical ohmic contact electrode structure in up / down direction, the first growth substrate used for growing the group 3-5 nitride-based semiconductor (ie Thin film of multi-layered light emitting structure from Al2O3, SiC, Si, GaAs, GaP) using laser lift-off, chemo-mechanical polishing, or wet-etching process Prior to lift-off, a thin film of a semiconductor single crystal multi-layered light emitting structure separated from sapphire, a growth substrate by using a support substrate (PSS) prepared by bonding to a resultant substrate and a wafer bonding process with the PSS. The present invention relates to a semiconductor light emitting device having a high performance vertical structure that minimizes damage and consequently improves overall performance.

In general, semiconductor light emitting devices include a light-emitting diode (LED) and a laser diode (LD) that generate light when a forward current flows. In particular, the LED and the LD have a p-n junction in common, and when a current is applied to the light emitting elements, the current is converted into a photon so that light is emitted from the device. Light emitted from LEDs and LDs varies from long-wavelength light to short-wavelength light range depending on the type of semiconductor material. Above all, visible light using LEDs made of semiconductors with wide band-gap semiconductors. It is possible to realize red, green, and blue areas, which are widely applied to display parts of various electronic devices, traffic signals, and various display light source devices. Recently, due to the development of white light sources, it is widely used in next-generation general lighting light source devices. It is sure to be possible.

In general, Group 3-5 nitride-based semiconductors are the first growth substrates, sapphire and silicon carbide (SiC), which have significantly different lattice constants and thermal expansion coefficients in order to obtain high quality semiconductor thin films. It is growing hetero-epitaxially on top of silicon (Si). However, Sapphire's first growth substrate has the disadvantage of not being able to apply a large current to the LED due to poor thermal conductivity, and since Sapphire's first growth substrate is an electrical insulator, it is difficult to cope with static electricity flowing from the outside. There is a big problem that is likely to cause failure. These problems not only lower the reliability of the device but also cause a lot of process constraints in the packaging process.

In addition, the first growth substrate of sapphire, which is an electrical insulator, has a multi-layered n-type ohmic contact electrode (hereinafter referred to as 'first ohmic contact electrode') and a p-type ohmic contact electrode (hereinafter referred to as 'second ohmic contact electrode'). In addition to having a mesa structure formed in the same direction as the growth direction of the light emitting structure, the LED chip area must also be larger than a certain size, so there is a limit to reducing the LED chip area. It is an obstacle to the improvement of LED chip production quantity per light emitting device.

As described above, in addition to the shortcomings of the mesa structure LED fabricated on the sapphire, which is the first growth substrate, it is difficult to dissipate a large amount of heat inevitably generated when driving the light emitting device to the outside due to the poor thermal conductivity of the sapphire growth substrate. have. For this reason, there is a limit to the application of a mesa structure in which sapphire is attached to a light emitting device used in a large area and a large capacity (that is, a large current), such as a large display and a general light source. That is, when a large current is injected into the light emitting device for a long time, the internal temperature of the light emitting active layer is gradually increased due to a large amount of heat generated, thereby causing a problem that the LED luminous efficiency gradually decreases.

Unlike sapphire, silicon carbide (SiC) growth substrates have excellent thermal and electrical conductivity, and at the same time, lattice constant and thermal expansion coefficient (TEC), which are important variables in growing high-quality semiconductor single crystal thin films, Similar to the Group 3-5 nitride-based semiconductor, a good multilayer light emitting structure thin film has been successfully laminated and grown, and various types of vertical light emitting devices have been manufactured. However, since it is not easy to manufacture a good quality SiC growth substrate, it is considerably higher cost than other single crystal growth substrates, and as a result, there are many limitations in applying to mass production.

Therefore, in view of the current technology, economy, and performance, it is most preferable to manufacture a high-performance light emitting device using a multilayer light emitting structure laminated on a sapphire growth substrate. As described above, in order to solve the LED problems of the mesa structure fabricated using a thin film, which is a group III-nitride-based semiconductor multilayer light emitting structure stacked / grown on the sapphire, which is the first growth substrate, the first growth of sapphire recently. After growing a high quality multilayer light emitting structure thin film on the substrate, the group 3-5 nitride-based semiconductor multilayer light emitting structure thin film is lifted off safely from sapphire, and a high performance vertical light emitting diode using the same Many efforts have been made to fabricate vertical structured LEDs.

1 is a cross-sectional view illustrating a process of separating the first growth substrate sapphire using a laser lift off (LLO) technique according to the prior art. As shown in FIG. 1, when the laser beam, which is a strong energy source, is irradiated to the backside of the first growth substrate 100 formed of transparent sapphire using LLO technology, the laser at the interface is exposed. The beam absorption is strongly generated, resulting in instantaneous temperature of 900 ° C. or higher, resulting in thermal chemical decomposition of gallium nitride (GaN) at the interface, and the first growth substrate 100 made of sapphire and the nitride semiconductor thin film 120 Laser lift-off (LLO). However, as mentioned in many prior documents, the group III-nitride-based semiconductor multilayer light emitting structure thin film is a group III-nitride-based semiconductor thin film due to different lattice constants and coefficients of thermal expansion when subjected to a laser lift off (LLO) process. It is not able to withstand the mechanical stress generated between sapphire, which is a thick initial growth substrate, and a large amount of damage and breaking occurs in the semiconductor single crystal thin film after separation from sapphire. As described above, when the group 3-5 nitride-based semiconductor multilayer light emitting structure thin film is damaged and broken, not only does a large leakage current occur, but also the chip yield of many light emitting devices, including LEDs, is greatly reduced. This will cause the overall performance degradation of the LED chip as a device. Therefore, a high-performance vertical LED manufacturing process has been steadily studied using a sapphire growth substrate separation process and a semiconductor single crystal thin film which can minimize damage of the group 3-5 nitride-based semiconductor multilayer light emitting structure thin film.

As a result, various methods have been proposed for minimizing damage and breakage of the Group 3-5 nitride-based semiconductor multilayer light emitting structure thin film when the sapphire, which is the first growth substrate, is separated using the LLO process. Figure 2 is a growth direction by introducing wafer bonding and electroplating (electroplating or electroless plating) process before performing the LLO process, according to a conventional technique for preventing damage and cracking of the semiconductor multilayer light emitting structure thin film ([0001]) is a cross-sectional view showing a process of forming a stiffening supporting substrate (stiffening supporting substrate) is in close contact. Referring to FIG. 2A, a semiconductor single crystal multilayer light emitting structure is formed from the first growth substrate 200 by irradiating a laser beam through a back-side of the first growth substrate 200 formed of transparent sapphire. Prior to separating the thin films 210 and 220, the support substrate 240 is structurally stable and strongly adhered to the bonding layer 230 by using wafer bonding and electroplating processes. In addition, referring to FIG. 2B, prior to separating the semiconductor single crystal multilayer light emitting structure thin films 210 and 220 from the first growth substrate 200 formed of sapphire, wafer bonding and an upper portion of the seed layer 232 may be performed. By using the electroplating process to form a structurally stable and strongly adhered support substrate 242.

FIG. 3 is a cross-sectional view of a group 3-5 nitride-based semiconductor light emitting device having a vertical structure manufactured by grafting a support substrate that is structurally stable and strongly adhered to the LLO process according to the conventional technique using the method of FIG. 2. admit.

FIG. 3A is a cross-sectional view illustrating a semiconductor light emitting device manufactured by using the method of forming the supporting substrate of FIG. 2A. Referring to (a) of FIG. 3, which shows a cross-section of the LED bonded to the wafer bonding, the multi-layer metal layer 250 including the support substrate 240, the bonding layer 230, and the second ohmic contact electrode, which are thermal and electrical conductors, is formed. The two semiconductor cladding layer 280, the light emitting active layer 270, the first semiconductor cladding layer 260, and the first ohmic contact electrode 290 are sequentially formed. The support substrate 240, which is an electrical conductor, is preferably a semiconductor wafer such as silicon (Si), low manganese (Ge), silicon low manganese (SiGe), gallium arsenide (GaAs) having excellent thermal and electrical conductivity. Doing.

However, the support substrate 240 used in the vertical light emitting device (LED) as shown in (a) of FIG. 3 has a large thermal expansion coefficient (TEC) and a sapphire growth substrate on which a semiconductor single crystal thin film is stacked / grown. When the Si or other conductive support substrate wafers are bonded by wafer bonding, wafer warpage and a large amount of fine micro-cracks are generated inside the semiconductor multilayer light emitting structure, which leads to process difficulties and fabricated LEDs. Low product yields are an issue due to poor performance.

3B is a cross-sectional view illustrating a semiconductor light emitting device manufactured by using the method of forming the supporting substrate of FIG. 2B. Referring to Figure 3 (b) showing a cross-sectional view of the LED grafted with electroplating, a vertical light emitting device (LED) produced by the LLO and electroplating process graft is a support substrate 242, which is an electrical conductor The seed layer 232, the multilayer metal layer 252 including the second ohmic contact electrode, the second semiconductor clad layer 280, the light emitting active layer 270, the first semiconductor clad layer 260, and the first ohmic contact electrode 290. ) Are sequentially configured. The support substrate 242, which is the electrical conductor, is a metallic thick film formed by electroplating, and in particular, is composed of a single metal such as Cu, Ni, W, Au, Mo, or the like having excellent thermal and electrical conductivity. Alloy is used first.

The LED support substrate 242 as shown in FIG. 3 (b) having the above-described structure is considerably larger than the growth substrate sapphire due to the metal or alloy thick film fabricated by electroplating. Coefficients of thermal expansion and ductility cause many problems such as curling, warpage, and braking in a single chip process such as mechanical sawing or laser scribing.

Therefore, when fabricating a group III-nitride semiconductor light emitting device having a vertical structure using the LLO process, many subsequent processes including wafer bending and cracking, micro crack generation, annealing and single chip processes ( Considering post-processing constraints and low product yield, an efficient support substrate and a high-performance vertical light emitting device manufacturing process using the same must be developed.

An object of the present invention for solving the above problems is a wafer warpage when wafer bonding a sapphire and a support substrate, which is the first growth substrate on which a thin film, which is a group 3-5 nitride-based semiconductor multilayer light emitting structure, are stacked and bonded with a bonding material. Is not prepared at all, and after the LLO process, a "prepared ready substrate" is obtained to obtain a nitride-based semiconductor single crystal multilayer thin film having no cracking and no micro-crack in the semiconductor multilayer light emitting structure. supporting substrate "(PSS)".

Another object of the present invention is to use a PSS as described above, after stacking / growing a multi-layered light emitting structure thin film composed of group 3-5 nitride-based semiconductor single crystals on top of sapphire, which is the first growth substrate, an efficient support substrate manufacturing and LLO process The present invention provides a group 3-5 nitride-based semiconductor light emitting device having a high-performance vertical structure capable of minimizing damage and breaking of a semiconductor single crystal thin film.

Still another object of the present invention is to provide a method of manufacturing a group 3-5 nitride-based semiconductor light emitting device having the high performance vertical structure described above.

A feature of the present invention for achieving the above object relates to a prepared supporting substrate (hereinafter referred to as 'PSS') for a semiconductor light emitting device used as a support substrate of a vertical semiconductor light emitting device,

A selected supporting substrate (hereinafter referred to as 'SSS') formed of a predetermined material;

A sacrificial layer is formed by stacking on top of the SSS,

A heat-sink layer having excellent thermal and electrical conductivity formed by being stacked on top of the sacrificial layer,

And a bonding layer formed by being stacked on the heat sink layer.

The SSS of the PSS having the aforementioned characteristics is preferably an electrically insulating material having a difference in thermal expansion coefficient of 2 ppm or less from the original growth substrate. For example, sapphire (Al 2 O 3), aluminum nitride (AlN), It consists of a wafer of single crystal, polycrystalline, or amorphous substrate, such as MgO, AlSiC, BN, BeO, TiO 2, SiO 2, and glass.

The sacrificial layer is a single crystal, polycrystalline or amorphous compound combined with nitrogen or oxygen. For example, GaN, InGaN, ZnO, InN, In2O3, ITO, SnO2, In2O3, Si3N4, SiO2, BeMgO, MgZnO Etc.,

The heat sink layer is made of a metal having high thermal and electrical conductivity, or at least one of Cu, Ni, Ag, Mo, Al, Au, Nb, W, Ti, Cr, Ta, Al, Pd, Pt, and Si. It is made of a material containing at least one or more of an alloy or a solid solution, or a nitride or oxide consisting of the above, wherein the heat sink layer is characterized in that the thickness of 0.1 micrometer to 100 micrometers or less ,

The bonding layer may be a soldering or brazing alloy material including at least one of Ga, Bi, In, Sn, Pb, Au, Al, Ag, Cu, Ni, Pd, Si, and Ge. It is preferable to make.

At least one or more layers of the sacrificial layer, heat sink layer and bonding layer of the PSS for semiconductor light emitting device having the above-mentioned characteristics is selectively patterned into a shape of a predetermined shape,

Preferably, the sacrificial layer, heat sink layer, and bonding layer of the PSS for semiconductor light emitting device are all patterned into a predetermined shape, and the SSS is etched to a predetermined depth.

Method for manufacturing a semiconductor light emitting device using a PSS according to another feature of the present invention,

(a) preparing a first wafer in which a semiconductor multilayer light emitting structure is stacked and grown on top of an initial growth substrate;

(b) preparing a second wafer which is a prepared support substrate (PSS),

(c) bonding the second wafer on top of the first wafer,

(d) separating the first growth substrate of the first wafer from the bonded result,

(e) forming and passivating the first ohmic contact electrode to complete the chip, and

(f) cutting to produce a single chip,

The PSS may be formed by sequentially stacking a sacrificial layer, a heat sink layer, and a bonding layer on the selected support substrate SSS.

In the method of manufacturing a semiconductor light emitting device having the features described above, the semiconductor multilayer light emitting structure in the step (a) comprises an n-type semiconductor cladding layer, a light emitting active layer, a p-type semiconductor cladding layer, the semiconductor multilayer light emitting structure Each layer constituting the thin film is preferably made of a single crystal having a composition of Inx (GayAl1-y) N (1 = x = 0, 1 = y = 0, x + y> 0).

In the method of manufacturing a semiconductor light emitting device having the above characteristics, the step of manufacturing the final single chip of the step (f)

(f1) attaching a temporary supporting substrate formed of an organic or inorganic bonding material in the opposite direction of the PSS,

(f2) separating and removing the SSS by thermally chemically reacting the sacrificial layer by selecting a laser beam having an appropriate absorption wavelength band according to the material used as the sacrificial layer;

(f3) if the thickness of the heat sink layer is 80 micrometers or less than 500 micrometers or less, cutting the resultant in a vertical direction without a separate supporting substrate bonding process, thereby completing a semiconductor chip of a single chip. do.

In the method of manufacturing a semiconductor light emitting device having the above characteristics, the step of manufacturing the final single chip of the step (f)

(f1) attaching a temporary supporting substrate formed of an organic or inorganic bonding material in the opposite direction of the PSS,

(f2) separating and removing the SSS by thermo-chemical decomposition reaction of the sacrificial layer by selecting a laser beam having an appropriate absorption wavelength band according to the material used as the sacrificial layer;

(f3) If the thickness of the heat sink layer is thinner than a predetermined value (80 microns), an additional bonding layer made of an electrically conductive metal or alloy is formed, and the third supporting substrate is formed using the additional bonding layer. Bonding to the heat sink layer;

(f4) cutting the resultant in a vertical direction to complete a semiconductor light emitting device of a single chip, wherein the third support substrate is thermally and electrically conductive Si, Ge, SiGe, ZnO, GaN, AlGaN, It is preferably formed from a single crystal or polycrystalline wafer such as GaAs or metal foil such as Mo, Cu, Ni, Nb, Ta, Ti, Au, Ag, Cr, NiCr, CuW, CuMo, NiW.

As described above, according to the present invention, the first and second ohmic contact electrodes are positioned on the upper and lower surfaces of the group 3-5 nitride semiconductor single crystal multilayer light emitting structure, respectively, to improve the yield of LED chips, which are light emitting devices per wafer, and the first growth substrate. Separation of the sapphire has the advantage that it is easy to manufacture a LED, a light emitting device of a vertical structure in which heat dissipation and antistatic effectively. In addition, according to the present invention, before the separation of the sapphire growth substrate using the laser lift-off process, the sapphire growth substrate is grouped using the laser lift-off process by performing wafer bonding of the prepared support substrate with no wafer warpage. Micro cracks or cracks in group III-nitride semiconductors, which reduce the stress that group III-nitride semiconductor layers will receive when separated from the group 5 nitride semiconductor multilayer light emitting structure, and group III-nitride semiconductors The loss of separation of the thin film into the wafer bonding material was minimized.

In addition, when fabricating a light emitting device using a group 3-5 nitride-based semiconductor multilayer light emitting structure on the prepared support substrate, subsequent processes such as heat treatment and passivation can be freed, resulting in high thermal and mechanical damage. A reliable light emitting element can be obtained. In addition, when a highly reliable light emitting device fabricated on the prepared support substrate is subjected to a unified chip process, a wet etching process may be used rather than a conventional machine and laser process, and thus it may be achieved in a wafer bonding process using a conventional support substrate. It has the advantage of greatly improving chip yield and productivity which were not available.

The " prepared support substrate " can not only obtain a high quality nitride based semiconductor single crystal multilayer thin film through good wafer bonding, but also free all post-processing after sapphire separation, a growth substrate. As a result, it is essential to manufacture LEDs of group III-nitride-based light emitting devices having a high performance vertical structure.

In addition, in the present invention, many unified light emitting devices (LEDs) fabricated on top of a "prepared support substrate (PSS)" wafer, which are invented, are not mechanically polished without some mechanical processing such as sawing or laser scribing. In addition, a light emitting device having a high performance vertical structure having a single chip shape may be manufactured by using a sacrificial layer formed on the prepared support substrate PSS.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a prepared support substrate (PSS) according to a preferred embodiment of the present invention, a group group 3-5 nitride-based semiconductor light emitting device having a vertical structure, and a method of manufacturing the same will be described in detail.

Prepared support substrate ( PSS )

Hereinafter, the structure and manufacturing process of the PSS according to the preferred embodiment of the present invention will be described with reference to FIG. 4.

Figure 4 (a) is a cross-sectional view showing a PSS according to a preferred embodiment of the present invention.

Referring to FIG. 4A, the PSS 40 is referred to as a selected supporting substrate (hereinafter referred to as an 'SSS') 400, a sacrificial layer 410, and a heat-sink layer. 420 and a bonding layer 430.

The manufacturing process of the PSS 400 having the above-described structure is a. Preparing a selected supporting substrate (SSS); b. Sacrificial layer formation; c. Forming a heat-sink; d. Process steps of forming a bonding layer. As shown in (a) of FIG. 4, the PSS 40 according to the preferred embodiment of the present invention basically consists of a tri-layer on top of the SSS 400. That is, the sacrificial layer 410, the heat sink layer 420, and the bonding layer 430 are sequentially stacked on the SSS 400, which is an electrical conductor. Hereinafter, the structure and manufacturing process of the above-described PSS will be described in detail.

The selected support substrate (SSS) 400 is preferably an electrically insulating material having a thermal expansion coefficient difference of 2 ppm or less from an initial growth substrate. For example, sapphire (Al 2 O 3), aluminum nitride (AlN), It consists of a wafer of single crystal, polycrystalline, or amorphous substrate, such as MgO, AlSiC, BN, BeO, TiO 2, SiO 2, and glass.

The selected support substrate 400 is separated from the first growth substrate sapphire by using a laser beam, which is a strong energy source, to separate the group 3-5 nitride-based semiconductor single crystal multilayer light-emitting structure thin film by a few microns thick. It acts as a support of the mechanical impact absorbing (relief of mechanical impact) of the laser beam required to minimize the damage of the thin film having a single crystal multilayer light emitting structure.

In particular, when selecting the support substrate (SSS) should be appropriately selected according to the LED manufacturing process, which is a light emitting device of a single vertical structure to be finally manufactured. In other words, wafer bonding is performed to bond the PSS to the first wafer prior to performing the LLO process, in which the wafer bonded after wafer bonding is subjected to wafer warpage due to thermal properties (ie, coefficient of thermal expansion). ) Occurs mainly. Therefore, in order to minimize the wafer warpage phenomenon, SSS is the first growth substrate sapphire and sapphire (Al2O3), aluminum nitride (AlN), MgO, AlSiC, BN, BeO, TiO2, SiO2, Preferred are wafers of single crystal, polycrystalline or amorphous substrate such as glass.

The sacrificial layer 410 is a material layer necessary to separate and remove the SSS 400 from the LED chip, which is a final light emitting device, by using a laser beam as a strong energy source. The sacrificial layer 410 is GaN, InGaN, ZnO, InN, In2O3. Preferred are monocrystalline, polycrystalline, or amorphous phase materials in combination with nitrogen or oxygen, including ITO, SnO2, In2O3, Si3N4, SiO2, BeMgO, MgZnO, etc., and Si single crystal, polycrystalline, or amorphous phase materials. It is also possible.

The sacrificial layer 410 has to be selected from the composition material according to the characteristics of the selected support substrate (SSS) and the LED structure, which is a light emitting device having a single vertical structure to be finally manufactured.

The heat-sink layer 420 smoothly dissipates a large amount of heat generated when driving the LED, which is the finally manufactured vertically structured light emitting device, to the outside and at the same time, a strong bonding of upper and lower layers, It serves as a support. Accordingly, the heat sink layer 420 is preferably composed of a metal, an alloy, or a solid solution having excellent thermal and electrical conductivity, and may be formed by various physico-chemical deposition (CVD or PVD) methods. More preferably, it is carried out by an electroplating or electroless plating method.

The bonding layer 430 is a material formed to bond the first wafer, which is a sapphire growth substrate on which a group 3-5 nitride-based semiconductor single crystal multilayer thin film is laminated / grown, and the prepared support substrate PSS. The layer is made of a soldering or brazing alloy material containing at least one of Ga, Bi, In, Sn, Pb, Au, Al, Ag, Cu, Ni, Pd, Si, Ge It is preferable.

4B to 4F are stacked cross-sectional views illustrating various embodiments of the PSS according to the preferred embodiment of the present invention. 4A and 4D are cross-sectional views illustrating embodiments of the unpatterned PSS, and FIGS. 4B, 4C, and 4F are patterned PSSs. Are cross-sectional views illustrating exemplary embodiments of the present invention. FIG. 4B is a PSS patterning the bonding layer and the heat sink layer, and FIG. 4C is a PSS patterning the bonding layer, the heat sink layer, and the sacrificial layer. 4D illustrates a PSS in which the heat sink layer 422 is formed to have a predetermined thickness or more, and FIGS. 4E and 4F illustrate embodiments in which a PSS having a thick heat sink layer is patterned. have.

As shown in (b), (c), (e), and (f) of FIG. 4, a PSS according to a preferred embodiment of the present invention includes a bonding layer and a heat sink layer or a bonding layer, a heat sink layer, and a sacrificial layer. By patterning this, it is possible to facilitate the removal process of the SSS 400 in the future.

PSS The first of the high performance vertical semiconductor light emitting device using Example

Hereinafter, a structure of a first embodiment of a high performance vertical semiconductor light emitting device using PSS and a method of manufacturing the same will be described.

5 is a cross-sectional view illustrating a semiconductor light emitting device having a high performance vertical structure using PSS according to a first embodiment of the present invention. The semiconductor light emitting device 50 shown in FIG. 5 is a light emitting device fabricated using a PSS having a heat sink layer 680 having a relatively thin thickness (less than 80 microns).

As illustrated in FIG. 5, the high performance vertical semiconductor light emitting device 50 may include a first ohmic contact electrode 580, a buffer layer 510, and an n-type semiconductor cladding layer 520. A light-emitting active layer 530, a p-type semiconductor cladding layer 540, a second ohmic contact electrode 550, and a first bonding layer 560 are stacked. The second bonding layer 688, the heat sink layer 686, the third bonding layer 620, and the third support substrate 630 are stacked on the first bonding layer 560. The third support substrate 630 may be a single crystal or polycrystalline wafer such as Si, Ge, SiGe, ZnO, GaN, AlGaN, GaAs or the like, which has excellent thermal and electrical conductivity or Mo, Cu, Ni, Nb, Ta, Ti, Au Metal foils, such as Ag, Cr, NiCr, CuW, CuMo, and NiW, are preferable. In addition, the third bonding layer 620 existing between the third support substrate 630 and the heat sink layer 686 is preferably formed of a thermally stable metal, alloy, or solid solution.

More preferably, the first ohmic contact electrode 580 may be formed on the n-type semiconductor clad layer 520 after removing the buffer layer 510.

Hereinafter, referring to FIGS. 6A to 6H, a process of manufacturing a semiconductor light emitting device having a high performance vertical structure having the above-described structure according to the present embodiment will be described sequentially.

Referring to Figure 6, the manufacturing process of the semiconductor light emitting device of the high performance vertical structure using the PSS according to the present embodiment, a. Preparing a first wafer having a group III-nitride-based semiconductor multilayer light emitting structure stacked / grown on top of sapphire, which is the first growth substrate (see FIG. 6A); b. Preparing a second wafer which is a prepared support substrate (PSS) (see FIG. 6 (b)); c. Wafer bonding (see FIG. 6C); d. Sapphire lift-off, the first growth substrate (see FIG. 6 (d)); e. Post-processing (see (e) to (h) of FIG. 6); f. Process steps of manufacturing a single chip. Hereinafter, each process step described above will be described in detail.

Referring to (a) of FIG. 6, in the first wafer preparation step, the multi-layered light emitting structure thin film formed of the group 3-5 nitride-based semiconductor is separated from the growth substrate by applying an LLO process. In order to improve the quality, the semiconductor single crystal multilayer thin film of the high quality is necessarily grown on a transparent sapphire growth substrate 600. Low and high temperature buffering, which is the basic multilayer light emitting structure thin film of the light emitting device on the first growth substrate sapphire 600, using MOCVD and MBE systems, the most common group III-nitride semiconductor thin film growth equipment. a layer; 510, an n-type semiconductor cladding layer 520, a light-emitting active layer 530, and a p-type semiconductor cladding layer 540. Lamination / growth. Next, a high reflective second ohmic contact electrode 550 is formed on the p-type semiconductor clad layer, which is the uppermost layer of the multilayer light emitting structure thin film, and includes a first bonding layer including a diffusion barrier layer 562; 560 is continuously stacked / formed. Also prior to wafer bonding with the second wafer, trenches to deeper sapphire growth substrates or deeper to make a single chip using a patterning and dry etching process in which a plurality of rectangular or square arrays are regularly arranged. It is desirable to form a trench 670. The highly reflective second ohmic contact electrode 550 may include Ag, Al, Rh, Pt, Au, Cu, Ni, Pd, metallic silicide, Ag-based alloy, Al-based alloy, Rh-based alloy, CNTNs (carbon nanotube networks), a transparent conductive oxide, and a transparent conductive nitride, wherein the diffusion barrier layer 562 is formed of Ti, W, Cr, Ni, Pt, NiCr, TiW, CuW, Ta, Is formed of a material layer including at least one of TiN, CrN, TiWN, the first bonding layer 560 is Ga, Bi, In, Sn, Pb, Au, Al, Ag, Cu, Ni, Pd, Si It is preferably made of an alloying material of soldering or brazing comprising at least one of Ge.

In the a-stage process, the first organic substrate, the transparent organic sapphire 600, metal organic chemical vapor deposition (MOCVD), liquid phase epitaxy (hydride vapor phase epitaxy), The group III-nitride-based semiconductor thin films deposited / grown using a molecular beam epitaxy and metal organic vapor phase epitaxy (MOVPE) equipment are Inx (GayAl1-y) N (1 = x = 0). , 1 = y = 0, x + y> 0), and the multi-layer light emitting structure of the light emitting device is a low temperature buffer layer (low-growth layer directly grown on the sapphire growth substrate 600 at a temperature of 600 ° C. or less). high-temperature buffering layer 510, including a -temperature buffering layer, an n-type semiconductor cladding layer 520 doped with silicon (Si), a semiconductor light-emitting layer active layer; 530, doped with magnesium (Mg) The p-type semiconductor cladding layer 540 is sequentially stacked / grown in a multilayer structure, and the high temperature buffer layer 510 is a group 3-5 nitride-based semiconductor doped with silicon (Si). desirable. The light emitting active layer 530 has a single quantum well (SQW) structure consisting of a barrier layer of Inx (GayAl1-y) N and a well layer of Inx (GayAl1-y) N, or a multi quantum well. ; MQW) structure, and a short wavelength light emitting device having an AlN (~ 6.2eV) bandgap from a long wavelength having an InN (~ 0.7eV) bandgap by controlling the composition ratio of In, Ga, Al of the light emitting active layer 530 Can be produced freely. The well layer has a lower band gap than the barrier layer so that electrons and holes, which are carriers, are collected in the wells for the improvement of the internal quantum effect, and particularly, in order to improve light emission characteristics and lower the forward driving voltage. At least one of the layer and the barrier layer may be doped with Si or Mg.

Also prior to wafer bonding the first wafer to the second wafer, the PSS 680, trenches to or deeper into the sapphire growth substrate to make a single chip using patterning and dry etching processes in which a plurality of rectangular or square arrays are regularly arranged. It is desirable to form a trench 670. In some cases, a trench-free first wafer substrate is also applicable.

Next, referring to FIG. 6B, the step b process prepares a prepared support substrate (PSS) 680 which is a second wafer. The PSS 680 may include a sacrificial layer 684, a heat-sink layer 686, and a second bonding layer 688 on top of a selected support substrate (SSS) 682 to be used. Three layers of are sequentially stacked.

In more detail, the SSS 682 is an electrically insulating material of sapphire (Al 2 O 3), aluminum nitride (AlN), MgO, which is an electrically insulating material having a difference in thermal expansion coefficient of 2 ppm or less from the original growth substrate. AlSiC, BN, BeO, TiO 2, SiO 2, glass or the like is formed of one of the wafers of a single crystal, polycrystalline, or amorphous substrate.

The sacrificial layer 684, which is the first layer formed on the SSS 682, is a GaN, InGaN, ZnO, InN, in order to smoothly perform the unification process by using a laser beam as a strong energy source when finally manufacturing a single chip. Compounds of monocrystalline, polycrystalline, or amorphous phase in combination with nitrogen or oxygen, including In2O3, ITO, SnO2, In2O3, Si3N4, SiO2, BeMgO, MgZnO, etc., are preferred, but Si monocrystalline, polycrystalline, or amorphous phase compounds are preferred. Material is also possible.

The heat sink layer 686 made of a material having thermally and electrically good conductivity, which is a second layer formed on the SSS 682, is a light emitting device that dissipates heat generated when the light emitting device is driven to the outside. Metals, alloys, solid solutions, and semiconductor materials that serve as a support for the multilayer light emitting structure are preferred. In addition, the heat sink layer is preferably made of a relatively thin thickness (80 microns or less).

The second bonding layer 688 for wafer bonding with the first wafer, which is the third layer formed on the SSS 682, is made of the same material as the first bonding layer 560 positioned on the uppermost layer of the first wafer. It is most preferable to make it, but it may be composed of other materials. In addition, the three layers formed on the SSS of the PSS is preferably carried out by a physical or chemical vapor deposition method, in particular, the heat sink layer 686 is more preferably carried out by the electroplating (electroplating or electroless plating) method.

The SSS 682 constituting the PSS 680 selects one of wafers such as sapphire (Al 2 O 3), AlN, MgO, AlSiC, BN, BeO, TiO 2, and SiO 2 substrate, which are electrical insulators, and the sacrificial layer 684. ) Is a monocrystalline, polycrystalline, or amorphous material layer combined with nitrogen or oxygen, including GaN, InGaN, ZnO, InN, In2O3, ITO, SnO2, In2O3, Si3N4, SiO2, BeMgO, MgZnO, Alternatively, a single layer of Si, polycrystalline, or amorphous phase material may be used, and the relatively thin heat sink layer 686 may be a thermally or electrically conductive metal, Cu, Ni, Ag, Mo, Al, Au, Nb, W , Ti, Cr, Ta, Al, Pd, Pt, Si, consisting of an alloy or a solid solution containing at least one, or a material comprising at least one or more of the nitrides and oxides thereof The second bonding layer 688 is less than Ga, Bi, In, Sn, Pb, Au, Al, Ag, Cu, Ni, Pd, Si, Ge It is made of an alloy material of soldering (soldering) or brazing (brazing) containing one or more are preferred. Moreover, it can form also in things other than these material system.

Next, referring to FIG. 6C, wafer bonding, which is the next step c, bonds the first wafer and the second wafer by a thermocompressive method. Heat-compression bonding in the step c process is preferably carried out at a pressure of 1Mpa to 200Mpa at a temperature of 100 ℃ or more.

Next, referring to Figure 6 (d), the step d process is a step of separating the sapphire substrate which is the first growth substrate using the LLO technology. In order to separate the first growth substrate, the laser beam, a strong energy source, is irradiated through the transparent sapphire back-side, resulting in a strong laser absorption at the interface between the semiconductor single crystal multilayer light emitting structure and the sapphire. The first growth substrate sapphire is lifted off by thermo-chemical dissolution reaction of gallium nitride (GaN) at the interface.

In the d-step process, transparent sapphire liftoff, which is the first growth substrate 600, is preferably performed through a thermochemical decomposition reaction by irradiating a transparent sapphire back-side with a laser beam, which is a strong energy source. It is preferable to include the step of treating the surface of the group 3-5 nitride-based semiconductor thin film exposed to at least one of H2SO4, HCl, KOH, BOE at a temperature of 30 ℃ to 200 ℃. It is also desirable to completely remove the original growth substrate 600 further through mechanical-chemical polishing and subsequent wet etching. The wet etching of the sapphire growth substrate 600 is any one of sulfuric acid (H 2 SO 4), chromic acid (CrO 3), phosphoric acid (H 3 PO 4), gallium (Ga), magnesium (Mg), indium (In), aluminum (Al) or these It is preferable to carry out the mixed solution by the combination of the etching solution. More preferably, the wet etching solution has a temperature of 200 ° C or higher.

Next, referring to FIG. 6E, post-annealing by the step e process includes passivation, dry etching, and the like of the light emitting device, including wafer cleaning. Subsequent processes, such as vapor deposition and heat treatment of the first ohmic contact electrode material, are performed.

In the step e, the thermally stable first ohmic contact electrode 580 is formed on the buffer layer 510 or the n-type semiconductor clad layer 520 through the first ohmic contact electrode material deposition and heat treatment process, and Si3N4, SiO2. Or passivating the surface or side of the group III-nitride semiconductor device using at least one of various electrical insulator materials. In addition, the first ohmic contact electrode 580 may include Al, Ti, Cr, Ta, Ag, Al, Rh, Pt, Au, Cu, Ni, Pd, In, La, Sn, Si, Ge, Zn, Mg, NiCr , PdCr, CrPt, NiTi, TiN, CrN, SiC, SiCN, InN, AlGaN, InGaN, rare earth metals and alloys, metallic silicides, semiconducting silicides, carbon nanotube networks (CNTNs), transparent conductive oxides It is preferable to form a material including at least one of transparent conducting oxide (TCO) and transparent conducting nitride (TCN).

Next, the final f step process, a single chip fabrication, is performed by wafer bonding (c) according to the thickness of the heat sink layer 686 of the PSS 680 (ie, less than or greater than 80 microns) in the b step process. After the step process), the final single-chip type light emitting device structure is manufactured as shown in FIG. 5 after undergoing different post-processing.

Referring to FIG. 6F, when the thickness of the heat sink layer 686 of the PSS 680 is less than 80 microns, the temporary support substrate is formed of an organic or inorganic bonding material in the opposite direction of the PSS 680. supporting substrate; hereafter referred to as 'TSS': 610). Next, as shown in FIG. 6G, the sacrificial layer 686 is thermally chemically reacted by selecting a laser beam having an appropriate absorption wavelength band according to the material used as the sacrificial layer 686, thereby forming an electrical insulator. SSS 682 is separated and removed. Next, as shown in (h) of FIG. 6, the third support substrate 630 and the heat sink layer made of an electric conductor using the third bonding layer 620 made of an electrically conductive soldering or brazing metal or an alloy is formed. 686 is bonded and cut in the vertical direction (in the direction of the AA ′ arrow in FIG. 6H) to finally produce an LED chip, which is the light emitting device shown in FIG. 5.

PSS Second of the high performance vertical semiconductor light emitting device using Example

7 and 8, a semiconductor light emitting device having a high performance vertical structure using a PSS according to a second embodiment of the present invention and a method of manufacturing the same will be described.

7 is a cross-sectional view showing a semiconductor light emitting device having a high performance vertical structure using the PSS according to the present embodiment. PSS 880 according to the present embodiment is the same as the PSS 880 according to the first preferred embodiment described above and its laminated structure and manufacturing process, except that the heat sink layer 886 has a thickness of 80 microns to 500 microns It is formed below the meter, thickening.

The semiconductor light emitting device 70 shown in FIG. 7 is a light emitting device manufactured using a PSS 880 having a thick heat sink layer, and is stacked on top of a selected support substrate (SSS) 882 of the PSS 880. Since the heat sink layer 884 is made of 80 to 500 microns or less, it is characterized in that the thickness of the heat sink layer 884 is relatively thick.

As illustrated in FIG. 7, the high performance vertical semiconductor light emitting device 70 may include a first ohmic contact electrode 780, a buffer layer 710, and an n-type semiconductor cladding layer 720. A light-emitting active layer 730, a p-type semiconductor cladding layer 740, a second ohmic contact electrode 750, and a first bonding layer 760 are stacked. The second bonding layer 888 and the heat sink layer 886 are stacked on the first bonding layer 760. Therefore, in the semiconductor light emitting device 70 fabricated using the PSS according to the present embodiment, after the SSS 882, which is an electrical insulator, is removed through the sacrificial layer 884 by using the LLO process, a separate third light emitting device 70 may be used. Even without a support such as a support substrate, the thick heat sink layer 886 can support the multilayer light emitting structure of the semiconductor light emitting device.

More preferably, the first ohmic contact electrode 780 may be formed on an upper surface of the n-type semiconductor clad layer 720 after removing the buffer layer 710.

8A to 8H are cross-sectional views sequentially illustrating a method of manufacturing a light emitting device having a high performance vertical structure using the PSS according to the present embodiment. 8 (a) to (g) are the same as FIG. 6 (a) to (g) except for the difference in thickness of the heat sink layer 886 of the PSS, a description overlapping with FIG. 6 will be omitted. .

As shown in (a) to (g) of FIG. 8, after fabricating a semiconductor light emitting device using the PSS according to the present embodiment through the same manufacturing process as in the first embodiment described above, the SSS 882 of the PSS ). Next, as shown in FIG. 8 (h), the LED chip, which is the light emitting device 70 shown in FIG. . The PSS 880 used to fabricate the semiconductor light emitting device 70 according to the present exemplary embodiment includes a thick heat sink layer 886, so that the thick heat sink layer may have a multi-layer structure even if the third support substrate is not bonded. The semiconductor light emitting device can be supported.

Although the present invention has been described with reference to the embodiments illustrated in the accompanying drawings, it is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Could be. In particular, a homogeneous group III-nitride-based semiconductor growth substrate and a group III-nitride-based semiconductor multilayer thin film fabricated by growing a group III-nitride-based semiconductor on the sapphire growth substrate, and a vertical laser diode It will be appreciated that various optoelectronic devices, including laser diodes and transistors, can also be applied. Therefore, the true scope of protection of the present invention should be defined only by the appended claims.

1 is a cross-sectional view illustrating a laser lift-off (LLO) process that is generally performed in manufacturing a semiconductor light emitting device having a vertical structure according to the related art.

FIG. 2 illustrates a structure in which a support substrate is structurally stable and tightly adhered to a group 3-5 nitride-based semiconductor single crystal thin film growth direction before performing a laser lift off (LLO) process according to the related art. Cross-sectional views.

3 is a cross-sectional view of a group 3-5 nitride-based semiconductor light emitting device having a vertical structure manufactured by incorporating a support substrate that is structurally stable and strongly adhered to the LLO process according to the related art.

4A to 4F are stacked cross-sectional views illustrating exemplary prepared supporting substrates (hereinafter, referred to as 'PSS') according to a preferred embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a first embodiment of an LED which is a semiconductor light emitting device having a vertical single chip shape manufactured using PSS according to the present invention.

6 is a cross-sectional view sequentially illustrating a manufacturing process of a semiconductor light emitting device having a vertical structure according to a first embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a second embodiment of an LED which is a semiconductor light emitting device having a vertical single chip shape manufactured using PSS according to the present invention.

8 is a cross-sectional view sequentially illustrating a manufacturing process of a semiconductor light emitting device having a vertical structure according to a second embodiment of the present invention.

Claims (19)

A selected supporting substrate formed of a predetermined material (hereinafter referred to as 'SSS'); A sacrificial layer formed by being stacked on top of the SSS; A heat sink layer formed on the sacrificial layer and formed of a material having high thermal and electrical conductivity; A bonding layer formed on the heat sink layer and formed on top of the heat sink layer, and prepared as a supporting substrate for a semiconductor light emitting device having a vertical structure. The method of claim 1, The SSS is preferably an electrically insulating material having a difference in thermal expansion coefficient of 2 ppm or less from an initial growth substrate. For example, SSS (Al 2 O 3), aluminum nitride (AlN), MgO, AlSiC, BN, BeO , TiO2, SiO2, glass PSS for semiconductor light emitting device, characterized in that composed of one of a wafer of a single crystal, polycrystalline, or amorphous substrate. The method of claim 1, The sacrificial layer may be a single crystal, polycrystalline or combined with nitrogen or oxygen containing at least one of GaN, InGaN, ZnO, InN, In2O3, ITO, SnO2, In2O3, Si3N4, SiO2, BeMgO, MgZnO. A PSS for semiconductor light emitting device, comprising an amorphous material or a Si single crystal, polycrystalline, or amorphous material. The method of claim 1, The heat sink layer is thermally and electrically conductive, characterized in that made of a metal, alloy, or solid solution, the thickness of the heat sink layer is PSS for semiconductor light emitting device, characterized in that less than 0.1 micron to 500 micrometers. The method of claim 1, The metal, alloy, or solid solution constituting the heat sink layer includes at least one of Cu, Ni, Ag, Mo, Al, Au, Nb, W, Ti, Cr, Ta, Al, Pd, Pt, and Si. PSS for semiconductor light emitting device, characterized in that. The method of claim 1, The bonding layer may be a soldering or brazing alloy material including at least one of Ga, Bi, In, Sn, Pb, Au, Al, Ag, Cu, Ni, Pd, Si, and Ge. PSS for semiconductor light emitting device, characterized in that made. The method of claim 1, The sacrificial layer, heat sink layer, and bonding layer deposited / formed on top of the SSS are formed by one of physical and chemical vapor deposition and electrochemical vapor deposition, and the sacrificial layer is formed by an E-beam or a thermal vapor deposition method (E-beam). or thermal evaporator, MOCVD, Sputtering, and PLD methods, wherein the heat sink layer is formed by electroplating or electroless plating. The method of claim 1, At least one of the sacrificial layer, the heat sink layer and the bonding layer of the PSS for semiconductor light emitting device is selectively patterned into a predetermined shape, or the sacrificial layer, the heat sink layer and the bonding layer of the PSS for semiconductor light emitting device are predetermined PSS for semiconductor light emitting device, characterized in that all patterned in the shape of the shape and the SSS is etched to a predetermined depth. (a) preparing a first wafer on which a semiconductor multilayer light emitting structure is stacked / grown on an initial growth substrate; and (b) preparing a second wafer which is a prepared support substrate (PSS); and (c) bonding the second wafer on top of the first wafer; and (d) separating the first growth substrate of the first wafer from the bonded result; and (e) forming and passivating a first ohmic contact electrode; and (f) cutting the resultant into a single chip, wherein the PSS has a high performance vertical structure formed by sequentially stacking a sacrificial layer, a heat sink layer, and a bonding layer on a selected support substrate. The manufacturing method of the semiconductor light emitting element. The method of claim 9, In the step (a), the semiconductor multilayer light emitting structure includes an n-type semiconductor cladding layer, a light emitting active layer, and a p-type semiconductor cladding layer, and each layer constituting the semiconductor multilayer light emitting structure is Inx (GayAl1-y) N (1). = x = 0, 1 = y = 0, x + y> 0) A method for manufacturing a high-performance vertical semiconductor light emitting device, characterized in that it consists of a single crystal. The method of claim 9, The wafer bonding in step (c) uses a heat-compression bonding method, and the heat-compression bonding method is performed at a pressure of 1 MPa to 200 MPa at a temperature of 100 ° C. or higher, and the semiconductor light emitting device having a high performance vertical structure Method of manufacturing the device. The method of claim 9, The method of lifting off a semiconductor single crystal multi-light emitting structure from the initial growth substrate of step (d) comprises a laser irradiating a surface of the initial growth substrate with a laser beam. A method of manufacturing a high performance vertical semiconductor light emitting device, characterized in that it is one of a lift-off method, a mechanical-mechanical polishing method and a wet etching method using a wet etching solution. The method of claim 9, Fabricating the final single chip of step (f) (f1) attaching a temporary supporting substrate formed of an organic or inorganic bonding material in the opposite direction of the PSS; and (f2) separating and removing the SSS by thermal-chemical decomposition reaction of the sacrificial layer by selecting an electromagnetic light including a laser beam having an appropriate absorption wavelength band according to the material used as the sacrificial layer; and (f3) if the thickness of the heat sink layer is thicker than a predetermined value, cutting the resultant in the vertical direction without a separate bonding process for supporting substrate; and completing the semiconductor light emitting device of a single chip. A method of manufacturing a semiconductor light emitting device having a high performance vertical structure, characterized in that. The method of claim 13, And a thickness of the heat sink layer of the PSS of the semiconductor light emitting device is at least 80 microns to 500 microns or less. The method of claim 9, Fabricating the final single chip of step (f) (f1) attaching a temporary supporting substrate formed of an organic or inorganic bonding material in the opposite direction of the PSS; and (f2) separating and removing the SSS by thermally chemically decomposing the sacrificial layer by selecting an electromagnetic light including a laser beam having an appropriate absorption wavelength band according to the material used as the sacrificial layer; and (f3) if the thickness of the heat sink layer is thinner than a predetermined value (80 micron meter), an additional bonding layer of electrically conductive metal, solid solution or alloy is formed, and the third bonding layer is used to support the third layer. Bonding a substrate to the heat sink layer; and (f4) cutting the resultant in the vertical direction; comprising: completing a semiconductor light emitting device of a single chip. The method of claim 15, The third support substrate may be a single crystal or polycrystalline wafer such as Si, Ge, SiGe, ZnO, GaN, AlGaN, GaAs, or the like that has thermal and electrical conductivity or Mo, Cu, Ni, Nb, Ta, Ti, Au, Ag, Cr And NiCr, CuW, CuMo, NiW, or a metal, an alloy, or a solid solution foil. The method of claim 9, The material forming the first ohmic contact electrode of step (e) may be Al, Ti, Cr, Ta, Ag, Al, Rh, Pt, Au, Cu, Ni, Pd, In, La, Sn, Si, Ge, Zn, Mg, NiCr, PdCr, CrPt, NiTi, TiN, CrN, SiC, SiCN, InN, AlGaN, InGaN, rare earth metals and alloys, metallic silicides, semiconducting silicides, CNTNs (carbonnanotube networks) ), A method of manufacturing a high-performance vertical semiconductor light emitting device, characterized in that formed of a material containing at least one of transparent conducting oxide (TCO), transparent conducting nitride (TCN). The method of claim 9, The preparing of the first wafer includes an optical reflective layer, an electrical insulating layer, and a diffusion barrier layer on the semiconductor multilayer light emitting structure stacked and grown on the growth substrate in step (a). ), A heat sink layer or a bonding layer is formed, the method for manufacturing a high-performance vertical semiconductor light emitting device. The method of claim 18, The optical reflective layer, the electrical insulating layer, the diffusion barrier layer, the heat sink layer, or the bonding layer formed on the semiconductor multilayer light emitting structure is a physical vapor deposition method. ), A chemical vapor deposition method, or electroplating (electro plating or electroless plating) formed by the method of manufacturing a high-performance vertical semiconductor light emitting device.

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