KR20090123505A - Method of forming an isolation layer in semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming a device isolation layer of a semiconductor device is provided to suppress the lowering of a coupling ratio due to the decrease of the area of a floating gate by forming a linear insulation layer with a dual structure stacking a HTO(High Temperature Oxide) layer and a nitride layer in the sidewall of a conductive layer. CONSTITUTION: A trench is formed in a device isolation region of a semiconductor substrate(100) by an etching process using a device isolation mask. A trench is filled by forming a sidewall oxide layer(114), a first liner insulation layer(116), a second liner insulation layer(118), and a first insulation layer successively. A part of the first insulation layer remains in the lower part of the trench by etching the first insulation layer. The trench is filled by forming a second insulation layer and a third insulation layer on the remaining first insulation layer and second liner insulation layer. The third insulation layer is removed. The trench is filled by forming a fourth insulation layer(128) on the remaining second insulation layer.

Description

Method of forming an isolation layer in semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a device isolation layer of a semiconductor device, and more particularly, to a sidewall loss of a conductive film for a floating gate during a trench gap fill process using a spin on dielectric (SOD) method. It relates to a device isolation film forming method.

As the semiconductor devices are highly integrated, the process of forming a device isolation layer is becoming more difficult. Accordingly, an isolation layer is formed by using a shallow trench isolation (STI) method in which a trench is formed in a semiconductor substrate and then embedded. On the other hand, there are a number of methods for the STI method, among which a tunnel insulating film, a polysilicon film and a hard mask film stacked on a semiconductor substrate are sequentially etched to form a trench, and an oxide film is formed on the entire structure to fill the trench. This is applied to, for example, a NAND flash memory device. However, in the case of highly integrated devices, since the trench depth is deeper than the inlet width of the trench, the trench is formed without a void using a high density plasma (HDP) oxide film that has been used due to the large aspect ratio. It is becoming more difficult to form a device isolation film by fully gap filling. In order to solve this problem, research is being actively conducted on materials used to gap fill trenches without voids.

Among the methods for solving the above problem, there is a method of completely gap filling the trench by a spin on dielectric (SOD) method using polysilazane (PSZ). The PSZ material has a low viscosity and flows like water, so the trench can be completely gap filled. As such, when the device isolation layer is formed of the PSZ material, it is advantageous for the gap fill but is weak in reliability. For this reason, recently, PSZ-based materials are coated, cured, and then planarized by chemical mechanical polishing (CMP), followed by wet etchback process. By lowering the subsequent gap fill margin to secure a subsequent gap to form an appropriate thickness of the HDP oxide film is repeated to form a device isolation film.

However, the PSZ material contains a lot of impurities and moisture therein so that the tunnel insulation film is deteriorated when the PSZ material is formed adjacent to the tunnel insulation film. Accordingly, the HDP oxide film is formed under the PSZ film in the form of a liner to prevent the tunnel insulating film from being contaminated by impurities contained in the PSZ film. However, when forming the HDP oxide layer to secure the reliability, a problem occurs in that the sidewall of the floating silicon polysilicon layer is lost due to plasma damage. This results in a decrease in coupling ratio due to the reduction of the floating gate area, thereby lowering the operation characteristics of the device.

In the trench gap fill process using a spin on dielectric (SOD) method, the present invention provides a double layer liner insulating film in which a high temperature oxide (HTO) film and a nitride film are stacked on the sidewalls of a conductive film for a floating gate. A method of forming a device isolation layer of a semiconductor device capable of preventing sidewall loss of a conductive film for a floating gate during wet etching and HDP oxide deposition in order to secure a gap fill.

In an embodiment, a method of forming a device isolation layer of a semiconductor device may include forming a trench in an isolation region of a semiconductor substrate by an etching process using a device isolation mask, a sidewall oxide layer, first and second liner insulating layers, Forming a first insulating film sequentially to fill the trench; etching the first insulating film to leave a portion of the first insulating film under the trench; and forming a second insulating film on the remaining first insulating film and the second liner insulating film. Forming an insulating film to fill the trench; removing the third insulating film; and forming a fourth insulating film on the remaining second insulating film to fill the trench.

In the above, after the trench is formed, a laminated film of a tunnel insulating film, a conductive film and an element isolation mask is formed in the active region of the semiconductor substrate.

The first liner insulating layer is formed of a high temperature oxide (HTO) film.

The HTO film is formed by a Low Pressure Chemical Vapor Deposition (LPCVD) method using dichlorosilane (SiH ₂ Cl ₂ , dichlorosilane; DCS) gas as a silicon source.

The second liner insulating film is formed of a nitride film.

The second liner insulating layer is formed to a thickness such that the second liner insulating layer formed on sidewalls of the tunnel insulating layer may be removed during the etching process of the first insulating layer and the deposition process of the second insulating layer.

The second liner insulating film is formed to a thickness of 30 to 60 kPa.

The first and third insulating films are formed of a spin on dielectric (SOD) insulating film. The SOD insulating film is formed of a PSZ (Polysilazane) film. The PSZ film is formed by coating the PSZ material, followed by first and second curing and annealing.

Coating is carried out by spin coating at a temperature of 350 to 400 ℃. The first curing is performed at a temperature of 300 to 500 ° C. using a catalytic water vapor generator (c-WVG) method. The second curing is carried out at a temperature of 550-700 ° C. using catalytic steam generation. Annealing is carried out at a temperature of 850 to 1000 ° C. in an N ₂ gas atmosphere.

The first and third insulating layers are etched or removed by a wet etching process.

The wet etch process is performed by a wet etch back process using a buffered oxide etchant (BOE) or HF solution.

A portion of the sidewalls of the second liner insulating layer is etched together in the process of etching the first insulating layer.

In the process of removing the third insulating layer, sidewalls of the second insulating layer are etched together to increase the aspect ratio of the device isolation region.

The second and fourth insulating films are formed of HDP (High Density Plasma) oxide films.

During deposition of the second insulating layer, the second liner insulating layer remaining on the sidewall of the first liner insulating layer is oxidized.

The sidewalls of the conductive film are protected by the liner insulating film during the etching of the first insulating film and the deposition of the second insulating film.

In the trench gap fill process using a spin on dielectric (SOD) method, the present invention provides a double layer liner insulating film in which a high temperature oxide (HTO) film and a nitride film are stacked on the sidewalls of a conductive film for a floating gate. Prevents sidewall loss of the conductive film for the floating gate during wet etching and HDP oxide deposition to secure the gap fill, thereby reducing the coupling ratio due to the reduction of the floating gate area, thereby degrading the operation characteristics of the device. Can be prevented.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below, but should be understood by those of ordinary skill in the art. It is preferred that the present invention be interpreted as being provided to more fully explain the invention.

1A to 1F are cross-sectional views illustrating a method of forming a device isolation layer of a flash memory device according to an embodiment of the present invention.

Referring to FIG. 1A, a tunnel insulating film 102, a floating gate conductive film 104, and a device isolation mask 106 are sequentially formed on a semiconductor substrate 100. The tunnel insulating layer 102 may be formed of a silicon oxide layer (SiO ₂ ), and in this case, may be formed by an oxidation process. Preferably, the tunnel insulating film 102 is formed to a thickness of 70 to 80 kW using a wet oxidation process, and nitrogen in the tunnel insulating film 102 through an annealing process performed in a subsequent N ₂ O gas atmosphere. (Nitrogen; N) is included to reduce trap density and improve reliability. The floating gate conductive film 104 is intended to be used as a floating gate of a flash memory device. The floating gate conductive film 104 may be formed of a polysilicon film, a metal layer, or a stacked film thereof, and preferably a doped polysilicon. Can be formed into a film. The conductive film 104 for the floating gate is formed of undoped polysilicon to reduce the concentration of impurities (eg, phosphorus (P)) at the interface between the tunnel insulating film 102 and a floating gate (not shown) to be formed later. It is more preferable to form a laminated structure of an undoped polysilicon film and a doped polysilicon film, and may be formed to a thickness of about 300 to 1500Å at a temperature of 500 to 550 ° C. After the floating gate conductive film 104 is formed, impurities are diffused from the doped polysilicon film to the undoped polysilicon film. The heat treatment process may be performed by a rapid thermal process (RTP) process.

The device isolation mask 106 is used as an etch mask in the subsequent trench formation and is used to prevent the upper loss of the conductive film 104 for the floating gate, and may include a buffer insulating film (not shown) and a nitride film for a hard mask ( 108 and a hard mask oxide film 110 can be formed. The buffer insulating film and the hard mask oxide film 110 may be omitted, and when it is formed, an oxide film using a low pressure chemical vapor deposition (LPCVD) method, each having a thickness of about 30 to 100 GPa and a thickness of 100 to 400 GPa, respectively. It can be formed in thickness. The nitride film 108 for a hard mask is formed of a nitride film-based material for use as a polishing stop film in a subsequent chemical mechanical polishing (CMP) process for forming a device isolation film, and is 300 to 1000 kW using an LPCVD method. It can be formed in the thickness of.

Next, the trench 112 is formed by etching the device isolation mask 106, the floating gate conductive film 104, the tunnel insulating film 102, and the semiconductor substrate 100 in the device isolation region. More specifically described as follows. A photoresist (not shown) is applied on the device isolation mask 106 and an exposure and development process is performed to form a photoresist pattern (not shown) that exposes the device isolation mask 106 in the device isolation region. Subsequently, the device isolation region of the device isolation mask 106 is etched by an etching process using a photoresist pattern. Thereafter, the photoresist pattern is removed. Subsequently, the floating gate conductive film 104 and the tunnel insulating film 102 are etched by an etching process using the device isolation mask 106. As a result, the semiconductor substrate 100 in the device isolation region is exposed. In the process of etching the device isolation mask 106, the floating gate conductive film 104, and the tunnel insulating film 102, the hard mask oxide film 110 of the device isolation mask 106 is also etched by a predetermined thickness. Subsequently, the semiconductor substrate 100 of the exposed device isolation region is etched to a predetermined depth. As a result, the trench 112 is formed in the device isolation region. As such, the trench 112 may be formed by performing an ASA-STI (Advanced Self Align-Shallow Trench Isolation) process on the semiconductor substrate 100.

Referring to FIG. 1B, a wall oxidization process is performed to compensate for damage generated by an etching process for forming the trench 112. In this case, the sidewall oxidation process is preferably performed by a radical oxidation process to help oxidize the device isolation mask 106 and to minimize a smiling phenomenon occurring at both ends of the tunnel insulating layer 102.

Accordingly, the surface of the exposed tunnel insulating film 102, the floating gate conductive film 104, and the device isolation mask 106, as well as the sidewalls and the bottom surface of the trench 112, are oxidized to a predetermined thickness through a radical oxidation process. A damage layer (not shown) is formed of the sidewall oxide film 114. The sidewall oxide film 114 may be formed to have a thickness of 20 to 100 kHz to suppress damage to the trench 112 while suppressing the smiling of the tunnel insulating film 102.

Next, the liner insulating layer 120 having a double structure is formed on the sidewall oxide layer 114 including the trench 112 so that a portion of the trench 112 is filled. The liner insulating layer 120 is formed of a laminated film of the first and second liner insulating layers 116 and 118. In this case, the first insulating layer 116 may be caused by intrusion of H ₂ or SiH _{2 that} is outgased during the curing process of a polysilazane (PSZ) film to be formed later, and by doze ion moving. In order to prevent the tunnel insulating layer 102 from deteriorating, it should be formed using a material whose reliability has been verified. In addition, in order to prevent the loss of sidewalls of the conductive film 104 for the floating gate during the wet etching process, which is performed for the purpose of securing a subsequent gap-fill margin and securing an etching selectivity. It is formed in the form of a liner using a material having an etching rate ratio lower than that of the PSZ film. To this end, the first liner insulating layer 116 is formed of a high temperature oxide (HTO) film having a lower etching rate ratio and a relatively superior step coverage characteristic than the PSZ film. HTO membrane PSZ film and tunnel formed by Low Pressure Chemical Vapor Deposition (LPCVD) method using dichlorosilane (SiH ₂ Cl ₂ , dichlorosilane; DCS) gas as a silicon source. It may be formed to a thickness of 50 to 300 kPa so that the contact with the insulating film 102 can be suppressed to the maximum. This HTO film is characterized by a slight decrease in the etching ratio by the subsequent thermal budget.

The second liner insulating layer 118 suppresses the loss of the first liner insulating layer 116 during the wet etching process for the purpose of securing the subsequent gap fill margin and the etching selectivity, and finally, the conductive film 104 for the floating gate. In order to prevent the sidewalls of the ()) from being lost, it is formed in a liner shape using a material having an etching rate ratio lower than that of the PSZ film. Preferably, the second liner insulating film 118 is formed of a nitride film using a nitride-based material, and the nitride film on the sidewall of the tunnel insulating film 102 is formed by a subsequent wet etching process and an HDP oxide film deposition process at a temperature of 600 to 750 ° C. It is formed to a thickness of 30 to 60Å so that all can be removed.

Conventionally, since the HDP oxide film is formed on the sidewall of the conductive film for the floating gate to secure the reliability during the trench gap fill process using the PSZ film, the sidewall of the floating gate polysilicon film is lost by the plasma damage when the HDP oxide film is deposited. Occurred. In addition, when a single film of a nitride film is used as the liner insulating film, it is difficult to obtain a target to completely oxidize the nitride film in the subsequent HDP oxide film deposition process, and even if obtained, the thickness of the nitride film oxidized by the HDP oxide film deposition is small. The nitride film remained on the sidewall of this important tunnel insulating film, and had a structure vulnerable to reliability.

However, in the present invention, the liner insulating film 120 is formed by the dual structure of the HTO film and the nitride film using LPCVD. Accordingly, the sidewall of the floating gate conductive film 104 is prevented from being lost in the process of depositing the HTO film on the sidewall of the floating gate conductive film 104. In addition, the conductive film 104 for the floating gate is secured by securing a process margin of a wet etching process and an HDP oxide deposition process to secure a subsequent gap fill margin while preventing the nitride film from directly contacting or remaining on the sidewall of the tunnel insulation layer 102. Can be prevented from being lost. This is because the nitride film deposited before the HDP oxide deposition is oxidized by the plasma during the deposition of the HDP oxide, and serves as a buffer to prevent attack of the sidewall of the conductive film 104 for the floating gate. This is because the HTO film that is deposited before the nitride film deposition serves as a secondary buffer to protect the sidewall of the conductive film 104 for the floating gate even when the amount of the nitride film lost by the HDP oxide deposition is over.

Referring to FIG. 1C, the first insulating layer 122 is formed on the liner insulating layer 120 including the trench 112 to fill the trench 112. The first insulating layer 122 is formed of a spin on dielectric (SOD) insulating layer having the best fluidity and the best buried property of the trench 112. PSZ (polysilazane) -based chemical (chemical) can be used to form the SOD insulating film. Therefore, the SOD insulating film may be formed of a PSZ film.

When the first insulating layer 122 is formed of a PSZ film, the PSZ material is coated and then cured and then annealed. The coating process may be performed using a spin coating method such that the PSZ material has a thickness of about 3000 to 6000 kPa at a temperature of 350 to 400 ° C. When the coating process of the PSZ material is performed, since the viscosity of the material itself is low, the trench 112 may be filled without voids.

Since the PSZ film contains a lot of impurities and moisture therein, the PSZ film may be formed by continuously performing the first and second curing processes and then performing an annealing process in order to remove them and increase the etching ratio. The first curing process may be performed at a temperature of 300 to 500 ° C. using a catalytic water vapor generator (c-WVG) method. At this time, after completion of the first curing process, N is desorbed from the PSZ material composed of Si, H, and N, and H is substituted with O to form a solidified PSZ film formed of a SiO ₂ film. The second curing process may be performed at a temperature of 550 to 700 ° C using the c-WVG method. The annealing step can be carried out at a temperature of 850 to 1000 ° C. in an N ₂ gas atmosphere. After the second curing and annealing processes, the PSZ film may be further densified to lower the etching ratio of the PSZ film to a controllable level.

PSZ film has better landfill characteristics than HDP oxide film, but its etching rate is faster than that of wet etchant, and it is rapidly lost when exposed to wet etchant used in subsequent processes. There is this. Therefore, it is necessary to reduce the thickness of the PSZ film so that the PSZ film is not exposed in a subsequent step. This will be described later.

Next, the planarization process is performed on the sidewall oxide film 114, the liner insulating film 120, and the first insulating film 122 until the hard mask nitride film 108 is exposed to the sidewall only in the device isolation region where the trench 112 is formed. The oxide film 114, the liner insulating film 120, and the first insulating film 122 are left. The planarization process is preferably carried out using a chemical mechanical polishing (CMP) process, and is performed by using the hard mask nitride film 108 as a polishing stop film.

Referring to FIG. 1D, a portion of the first insulating layer 122 is etched to bottom up the bottom of the trench 112 to increase the aspect ratio of the device isolation region. The etching process may be performed by a wet etching process, and preferably may be performed by a wet etch back process. In the wet etch back process, a buffered oxide etchant (BOE) or HF solution may be used as an etchant. In this case, the wet etchback process is performed so that the first insulating film 122 is lower than the surface of the semiconductor substrate 100 in the active region by appropriately adjusting the process time in order to secure a subsequent gap fill margin and to secure an etching selectivity. do.

Accordingly, the first insulating film 122 having a higher etching ratio than the second liner insulating film 118 is rapidly etched by the etching process so that the first insulating film 122 remains only in the lower portion of the trench 112 so that the bottom surface of the trench 112 is bottomed up. This increases the aspect ratio of the device isolation region, thereby ensuring a gap fill margin for subsequent deposition processes. Meanwhile, the sidewalls of the second liner insulating layer 118 may be etched together by some thickness in the first insulating layer 122 etching process. However, since the first and second liner insulating films 116 and 118 having lower etching ratios than the first insulating film 122 are formed on the sidewalls of the conductive film 104 for floating gate, the floating gate conductive material is etched when the first insulating film 122 is etched. The film 104 is not exposed and is protected by the first liner insulating film 116 and the remaining second liner insulating film 118.

Subsequently, the first insulating film 122 remaining so that a portion of the trench 112 is filled, A second insulating film 124 having a liner shape is formed on the second liner insulating film 118, the first liner insulating film 116, and the nitride film 108 for a hard mask. Preferably, the second insulating layer 124 may be formed to a thickness of 150 to 1000 kW using a high density plasma (HDP) oxide film. The second insulating film 124 made of the HDP oxide film is thicker on the upper portion of the first insulating film 122 and the upper portion of the conductive film 104 for the floating gate than the sidewall of the conductive film 104 for the floating gate due to the deposition characteristics of the HDP method. Is formed.

In particular, when the second insulating film 124 made of the HDP oxide film is deposited, all of the second liner insulating film 118 remaining in the portion in contact with the HDP oxide film is oxidized, so that the second liner insulating film 118 is formed on the sidewall of the tunnel insulating film 102. It will not remain.

Referring to FIG. 1E, the third insulating layer 126 is formed on the second insulating layer 124 including the trench 112 to fill the trench 112. The third insulating layer 126 is fluid and forms the SOD insulating layer having the best embedding characteristics of the trench 112. In this case, PSZ-based chemicals may be used to form the SOD insulating film. Therefore, the SOD insulating film may be formed of a PSZ film.

When the third insulating layer 126 is formed of a PSZ film, the PSZ material may be coated and then cured and then annealed. The coating process may be carried out using a spin coating method such that the PSZ material has a thickness of about 3000 to 6000 kPa at a temperature of 350 to 400 ° C. When the coating process of the PSZ material is performed, since the viscosity of the material itself is low and flows, the trench 112 may be filled without voids.

Since the PSZ film contains a lot of impurities and moisture therein, the first and second curing processes are successively performed to remove the impurities and increase the etching ratio, and then the annealing process is finally performed. The first curing process may be performed at a temperature of 300 to 500 ° C. using a catalytic steam generation (c-WVG) method. At this time, after completion of the first curing process, N is desorbed from the PSZ material composed of Si, H, and N, and H is substituted with O to form a solidified PSZ film formed of a SiO ₂ film. The second curing process may be performed at a temperature of 550 to 700 ° C using the c-WVG method. The annealing step can be carried out at a temperature of 850 to 1000 ° C. in an N ₂ gas atmosphere. After the second curing and annealing processes, the PSZ film may be further densified to lower the etching ratio of the PSZ film to a controllable level.

Subsequently, the third insulating film 126 is planarized until the hard mask nitride film 108 is exposed, and the third insulating film 126 is left only in the region where the trench 112 is formed. It is preferable to perform a planarization process using a CMP process, and the nitride film 108 for hard masks is used as a polishing stop film.

Referring to FIG. 1F, the third insulating layer 126 of FIG. 1E is removed by etching to increase the aspect ratio of the device isolation region. The etching process may be performed by a wet etching process, preferably, by a wet etch back process. BET or HF solution can be used as an etchant in the wet etchback process. The wet etch back process of the third insulating film 126 is performed under the condition that all of the third insulating film 126 is removed by appropriately adjusting the process time in order to secure a subsequent gap fill margin. In this case, the third insulating film 126 of FIG. 1E having a higher etching ratio than that of the second insulating film 124 is etched by the etching process, and the sidewalls of the second insulating film 124 are etched together to form sidewalls of the first liner insulating film 116. Some are exposed. As a result, some of the second insulating layer 124 on the sidewall is removed, and the second insulating layer 124 remains only on the first insulating layer 124 on the bottom of the trench 112, thereby increasing the aspect ratio of the device isolation region.

Next, a fourth insulating film 128 is formed on the remaining second insulating film 124 including the trench 112 so that the trench 112 is filled. The fourth insulating film 128 is formed of an HDP oxide film. Even when the fourth insulating layer 128 is formed of the HDP oxide layer, the trench 112 may be gap-filled without voiding as the bottom surface of the trench 112 is bottomed up to reduce the aspect ratio of the device isolation region.

As described above, according to the present invention, during the gap fill process of the trench 112 using the SOD method, the double layer liner insulating film 120 having the HTO film and the nitride film laminated on the sidewall of the conductive film 104 for floating gate is formed. An etching margin may be secured during the wet etching process and the HDP oxide deposition process to secure the gap fill, thereby preventing sidewall loss of the conductive film 104 for the floating gate. Accordingly, the area of the floating gate to be formed later is prevented from being reduced, thereby preventing the coupling ratio of the cell from being lowered, thereby preventing the operation characteristics of the device from being lowered.

The present invention is not limited to the above-described embodiments, but may be implemented in various forms, and the above embodiments are intended to complete the disclosure of the present invention and to completely convey the scope of the invention to those skilled in the art. It is provided to inform you. Therefore, the scope of the present invention should be understood by the claims of the present application.

1A to 1F are cross-sectional views illustrating a method of forming a device isolation layer of a flash memory device according to an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

100 semiconductor substrate 102 tunnel insulating film

104: conductive film for floating gate 106: device isolation mask

108: nitride film for hard mask 110: oxide film for hard mask

112 trench 114 sidewall oxide film

116: first liner insulating film 118: second liner insulating film

120 liner insulating film 122 first insulating film

124: second insulating film 126: third insulating film

128: fourth insulating film

Claims (21)

Forming a trench in an isolation region of the semiconductor substrate by an etching process using an isolation mask; Sequentially forming sidewall oxide layers, first and second liner insulating layers, and first insulating layers to fill the trenches; Etching the first insulating film to leave a portion of the first insulating film below the trench; Filling the trench by forming second and third insulating films on the remaining first insulating film and the second liner insulating film; Removing the third insulating film; And And forming a fourth insulating film on the remaining second insulating film to fill the trench. The method of claim 1, wherein after the trench is formed, And a stacked layer of a tunnel insulating film, a conductive film and the device isolation mask in the active region of the semiconductor substrate. The method of claim 1, And the first liner insulating layer is formed of an HTO film. The method of claim 3, wherein The HTO film is a device isolation film forming method of a semiconductor device formed by a low pressure chemical vapor deposition method using a dichlorosilane (SiH ₂ Cl ₂ ) gas as a silicon source. The method of claim 1, And the second liner insulating layer is formed of a nitride film. The method of claim 2, The second liner insulating layer may be formed to have a thickness such that the second liner insulating layer formed on sidewalls of the tunnel insulating layer may be removed during the etching of the first insulating layer and the deposition of the second insulating layer. . The method of claim 6, The second liner insulating film is a device isolation film forming method of a semiconductor device formed to a thickness of 30 to 60Å. The method of claim 1, And the first and third insulating layers are formed of SOD insulating layers. The method of claim 8, And the SOD insulating film is formed of a PSZ film. The method of claim 9, Wherein the PSZ film is formed by coating a PSZ material, followed by first and second curing and annealing. The method of claim 10, The coating method is a device isolation film forming method of a semiconductor device is carried out by a spin coating method at a temperature of 350 to 400 ℃. The method of claim 10, The first curing is a method of forming a device separator of a semiconductor device is carried out at a temperature of 300 to 500 ℃ using a catalytic water vapor generator (c-WVG) method. The method of claim 10, The second curing is a method of forming a device isolation layer of a semiconductor device is carried out at a temperature of 550 to 700 ℃ using a catalytic steam generation method. The method of claim 10, The annealing is a device isolation film forming method of a semiconductor device is carried out at a temperature of 850 to 1000 ℃ in an N ₂ gas atmosphere. The method of claim 1, And the first and third insulating layers are etched or removed by a wet etching process. The method of claim 15, The wet etching process is a method of forming a device isolation layer of a semiconductor device performed by a wet etch back process using a BOE or HF solution. The method of claim 1, A method of forming a device isolation layer of a semiconductor device in which a portion of the sidewall of the second liner insulating layer is etched together during the etching of the first insulating layer. The method of claim 1, And removing sidewalls of the second insulating layer from the third insulating layer to increase the aspect ratio of the device isolation region. The method of claim 1, And the second and fourth insulating layers are formed of an HDP oxide film. The method of claim 19, And depositing the second liner insulating layer remaining on the sidewalls of the first liner insulating layer when the second insulating layer is deposited. The method of claim 2, And forming sidewalls of the conductive layer during the etching of the first insulating layer and the deposition of the second insulating layer by the liner insulating layer.

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