KR20090120913A - Liquid crystal display device and manufacturing method thereof - Google Patents

Abstract

PURPOSE: A liquid crystal display and a manufacturing method thereof for improving aperture ratio are provided to implement a common electrode function and a repair function by a connection pattern with a repair function. CONSTITUTION: A pixel electrode(23) is connected to a TFT(Thin Film Transistor). A common electrode is arranged to the pixel electrode. Common lines are connected to the common electrode. The common line is arranged to be contiguous to the gate line and the data line. A connection pattern(29) is arranged around a cross area of the data line and the gate line. The connection pattern is connected to the common electrode.

Description

Liquid crystal display device and manufacturing method thereof

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a manufacturing method thereof.

Due to the development of the information society, display devices capable of displaying information have been actively developed. The display device includes a liquid crystal display device, an organic electro-luminescence display device, a plasma display panel, and a field emission display device.

Among these, the liquid crystal display device has advantages such as light weight, small size, low power consumption, and full color video, and is widely applied to mobile phones, navigation, monitors, and televisions.

The LCD displays an image corresponding to a video signal by adjusting the light transmittance of the liquid crystal cells on the liquid crystal panel.

In the liquid crystal display device, an in-plane switching mode (IPS) mode is used in which a pixel electrode and a common electrode are formed on an array substrate to display an image by displacing liquid crystal molecules by a transverse electric field, thereby improving a viewing angle.

On the other hand, in order to improve the resolution, the thickness and pitch of metal lines or electrodes formed in the liquid crystal display device are narrowed. In such a case, a defect is likely to occur due to a short between the metal lines or disconnection of the metal lines during the process.

Repair technology is used to solve this problem.

1 is a diagram illustrating a repair structure of a conventional liquid crystal display.

As shown in FIG. 1, a repair pattern is formed to overlap the data line at least more than the intersection area in the intersection area of the gate line and the data line. In addition, a gate hole is formed in the gate line of the crossing region so as to at least exceed the crossing region. The gate hole may be divided into two regions from the crossing region to the gate line.

The repair pattern may be formed of the same material as the pixel electrode disposed on the pixel.

Due to the thickness of the gate line, the data line may be disconnected at the crossing area. In this case, the laser is irradiated to two points of the repair pattern to melt the gate insulating film formed under the data line so that the repair pattern is connected to the two points of the data line, respectively. Accordingly, even when the data line is disconnected, a signal supplied to the data line may flow through the repair pattern, thereby preventing a disconnection failure.

Due to the thickness of the gate insulating layer, the gate line and the data line may be shorted at the intersection area. In this case, the area of the gate line on both sides of the data line is disconnected with respect to the area of the data line and the shorted gate line (for example, the first region). Accordingly, as both sides of the first region are disconnected from the gate line, the short of the data line and the gate line is released, and the signal supplied to the gate line flows through the second region.

In the conventional liquid crystal display, as the repair pattern is formed to overlap the data line, the pixel electrode made of the same material as the repair pattern should be spaced apart within the design margin to prevent short circuit with the repair pattern.

In the conventional liquid crystal display, a common electrode formed of the same material as a pixel electrode is disposed on a pixel, and the common electrode of each pixel may be connected by a connection pattern.

Accordingly, the liquid crystal display of the related art should be spaced apart from the connection pattern and the pixel electrode or the common electrode in a designed margin range in order to prevent the pixel electrode or the common electrode from being electrically shorted to each other. Accordingly, there is a problem that the size of the pixel electrode or the common electrode is reduced, and thus the size of the pixel is reduced, thereby reducing the aperture ratio.

In addition, in the conventional liquid crystal display, as the size of the pixel is reduced, the size of the pixel electrode is also reduced, thereby reducing the capacity of the storage capacitance formed by the pixel electrode.

In addition, the conventional liquid crystal display has a problem in that a signal is delayed due to an increase in resistance of the gate line in the cross region due to the gate hole of the gate line formed in the cross region.

Accordingly, an object of the present invention is to provide a liquid crystal display device and a method of manufacturing the same, which can improve the aperture ratio and increase the capacitance of the storage capacitance by serving as a repair electrode as a common electrode.

Another object of the present invention is to provide a liquid crystal display device and a method of manufacturing the same, which can prevent a signal delay by not forming a gate hole in a gate line of an intersection region.

According to a first embodiment of the present invention, a liquid crystal display device includes a plurality of pixels arranged in a matrix, each pixel comprising: a gate line; A data line crossing the gate line; A thin film transistor connected to the gate line and the data line; A pixel electrode connected to the thin film transistor; A common electrode disposed adjacent to the pixel electrode; And a common line connected to the common electrode and disposed adjacent to the gate line and the data line, wherein the common line is disposed to overlap the data line around an intersection area of the gate line and the data line. A connection pattern connected to the electrode is disposed.

According to a second embodiment of the present invention, a method of manufacturing a liquid crystal display includes: forming a gate line, a common line, and a contact pad on a substrate; Forming a gate insulating film on the substrate including the gate line, the common line, and the contact pad; Forming a semiconductor layer on the gate insulating layer corresponding to the gate line; Forming a data line and a source / drain electrode on the substrate including the semiconductor layer; Forming a passivation layer having first and second contact holes on a substrate including the data line and the source / drain electrodes; And forming a pixel electrode, a common electrode, and a connection pattern on the passivation layer, wherein the connection pattern is disposed to overlap the data line around an intersection area of the gate line and the data line and is common to adjacent pixels. Connected to the electrode.

Accordingly, in the present invention, by connecting the connection pattern having the repair function to the common electrode of each pixel integrally, both the function and the repair function of the common electrode can be realized by the connection pattern.

In addition, the present invention does not need to connect the common electrode of each pixel separately, so that the size of the pixel electrode or the common electrode can be increased, and the aperture ratio can be improved.

In addition, since the common electrode of each pixel does not need to be separately connected, the size of the pixel electrode can be increased, thereby increasing the capacity of the storage capacitance formed by the pixel electrode.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.

FIG. 2 is a plan view illustrating a liquid crystal display according to the present invention, and FIG. 3 is a cross-sectional view taken along lines II ′ and II-II ′ of FIG. 2.

2 and 3, in the liquid crystal display, a plurality of pixels P1 to P4 for displaying an image are arranged in a matrix.

Each pixel P1 to P4 includes at least first and second domains D1 and D2. Transverse electric fields of different directions may be formed in the first and second domains D1 and D2. For example, transverse electric fields in symmetrical directions may be formed in the first and second domains D1 and D2. Accordingly, the liquid crystals disposed in the first and second domains D1 and D2 may be aligned in different directions by the transverse electric field, thereby further expanding the viewing angle.

Each pixel P1 to P4 may be defined by the gate line 3 and the data lines 17 and 19 crossing each other on the substrate 1. That is, the gate line 3 may be disposed along the first direction, and the data lines 17 and 19 may be disposed along the second direction perpendicular to the first direction.

In the present invention, the gate line 3 and the data lines 17 and 19 are limited to vertically cross each other, but the gate line 3 and the data lines 17 and 19 may not necessarily cross vertically.

The gate line 3 and the data lines 17 and 19 are insulated from each other by the gate insulating film 9 interposed therebetween.

Common lines 5 and 5 'are disposed adjacent to the gate line 3 and the data lines 17 and 19. The common lines 5 and 5 ′ disposed in each of the pixels P1 to P4 may be electrically connected to each other by the common link line 5a in a first direction parallel to the gate line 3. At least one common link line may be disposed between the common lines 5 and 5 ′ disposed in each pixel P1 to P4.

For example, as shown in FIG. 4, the common lines 5 and 5 ′ have a '-' shape adjacent to the gate line 3 and the data line 17 for defining the first pixel P1. And the gate line 3 and the data line 19 for defining the third pixel P3 may be disposed in a '-' shape.

The contact pad 7 may be disposed to extend from the common line disposed in the third pixel P3 to the first pixel P1. Similarly, the contact pad 7 ′ may be disposed to extend from the common line disposed in the fourth pixel P4 to the second pixel P2.

The contact pads 7 and 7 ′ may be electrically connected to the common electrodes 25 and 27 described later. The contact pads 7 and 7 ′ may be disposed in the boundary region between the first and second domains D1 and D2 to prevent the decrease in the aperture ratio. Therefore, the common voltage supplied to the common lines 5 and 5 'may be applied to the common electrodes 25 and 27.

The common lines 5 and 5 ′ may be formed on the same layer as the same material as the gate line 3.

The common electrodes 25 and 27 may overlap the pixel electrode 23 with an insulating layer, that is, the gate insulating layer 9 and the passivation layer, to form a storage capacitance.

In the boundary regions of the first and second domains D1 and D2, a disclination region in which the alignment of the liquid crystal molecules is disturbed is formed, and thus the liquid crystal is not driven. Accordingly, the boundary regions of the first and second domains D1 and D2 exist as non-transmissive regions, that is, dead regions where light is not transmitted. As a result, as the contact pads 7 and 7 ′ are disposed in the dead regions of the pixels P1 to P4, the aperture ratio may be prevented from being lowered.

In addition, since the common line 5 is not disposed in the first pixel P1 adjacent to the data line 19 for defining the third pixel P3, the aperture ratio of the first pixel P1 may be increased. All. As such, by arranging each of the pixels P1 to P4, the total aperture ratio of the liquid crystal display device can be significantly improved.

The common lines 5 and 5 ', the contact pads 7 and 7' and the common link line may be integrally formed.

The thin film transistor 15 is disposed in each pixel P1 to P4. The thin film transistor 15 includes a gate electrode, a semiconductor layer 11, and source / drain electrodes 13a and 13b.

The gate electrode may be integrally formed with the gate line 3. The semiconductor layer 11 may be disposed on the gate insulating film 9 corresponding to the gate electrode. The source electrode 13a and the drain electrode 13b may be spaced apart from each other. The source electrode 13a may be integrally formed with the data line 17.

Therefore, when the thin film transistor 15 is turned on by the gate electrode supplied to the gate line 3, the data voltage supplied to the data line 17 may be applied via the thin film transistor 15.

In FIG. 2, to improve the electrical characteristics of the thin film transistor 15, the edge region of the source electrode 13a is formed in a U shape to increase the channel width of the thin film transistor 15. It is not.

A protective film is formed on the substrate 1 including the thin film transistor 15. The passivation layer has a first contact hole 31 formed to expose the drain electrode 13b of the thin film transistor 15 and second contact holes 33a and 33b formed to expose the contact pads 7 and 7 '.

On the passivation layer 21 of each pixel P1 to P4, the pixel electrode 23 and the common electrodes 25 and 27 face each other. Each of the pixel electrode 23 and the common electrodes 25 and 27 may be disposed parallel to the data lines 17 and 19.

Pixel electrode bars 23a are formed in the first domain in the diagonal directions of the right and the upper sides of the pixel electrodes 23, and pixel electrode bars 23a are formed in the second domain in the diagonals of the right and lower sides of the pixel electrodes 23. It may be formed extending in the direction. Therefore, the pixel electrode bars 23a of each of the first and second domains may be symmetrically formed with respect to the first and second domains.

Common electrode bars 25a and 27a extend in the left and lower diagonal directions from the common electrodes 25 and 27 in the first domain, and common electrode bars 25a and 27a in the second domain. 27, it may be formed extending in the diagonal direction of the left and the upper side. Accordingly, the common electrode bars 25a and 27a of each of the first and second domains may be symmetrically formed with respect to the first and second domains.

In addition, the common electrode bars 25a and 27a may be formed in the boundary regions of the first and second domains in a direction perpendicular to the common electrodes 25 and 27.

The pixel electrode 23 may be electrically connected to the drain electrode 13b of the thin film transistor 15, and the common electrodes 25 and 27 may be electrically connected to the contact pads 7 and 7 ′.

The common electrodes 25 and 27 disposed in each of the pixels P1 to P4 may be connected to each other by the connection pattern 29 in a second direction parallel to the data lines 17 and 19.

As shown in FIG. 5, the connection pattern 29 overlaps the data line 19 disposed in an area between the pixels P1 and P2 or between P3 and P4 adjacent to the gate line 3. On the other hand, both sides are electrically connected to the common electrodes 25 and 27 disposed in each of the adjacent pixels P1 and P2 or between P3 and P4.

The connection pattern 29 is formed on the data line 19 that intersects the gate line 3 and overlaps the data line 19 with a length of 5 to 10 times the width of the gate line 3. Can be formed.

Therefore, the common electrodes 25 and 27 and the connection pattern 29 of each pixel P1 to P4 may be integrally formed. In addition, the common electrodes 25 and 27 disposed in the pixels P1 and P2 or P3 and P4 arranged along the second direction parallel to the data lines 17 and 19 may be electrically connected to each other by the connection pattern 29. Can be connected.

The connection pattern 29 normally connects the common electrodes 25 and 27 disposed in each of the adjacent pixels P1 to P4 to maintain the common voltage of the equipotential between the pixels P1 to P4. If a repair is necessary due to a bad line, it can be used as a repair pattern. For example, a line failure may be a short of the gate line 3 and the data lines 17 and 19 or a disconnection of the data lines 17 and 19 at the intersection of the gate line 3 and the data lines 17 and 19. Can be.

For example, when the gate line 3 and the data line 19 are shorted, the data line 19 on both sides of the gate line 3 is removed at the intersection of the gate line 3 and the data line 19. Each laser is cut using a laser, and a laser is cut between the common electrodes 25 and 27 and the connection pattern 29 disposed in adjacent pixels P1 and P2 or P3 and P4, respectively. The protective layers under the connection patterns 29 on both sides of the gate pattern are melted to form the connection patterns 29 to be electrically connected to the data lines 19. In this case, the data voltage supplied to the data line 19 may be applied to the data line 19 again via the connection pattern 29 where the gate line 3 is located.

When disconnection of the data line 19 occurs, a laser is cut between the common electrodes 25 and 27 and the connection pattern 29 disposed in the adjacent pixels P1 and P2 or P3 and P4, respectively. Next, each of the passivation layers under the connection pattern 29 on both sides of the gate pattern is melted using a laser so that the connection pattern 29 is electrically connected to the data line 19. In this case, the data voltage supplied to the data line 19 may be applied to the data line 19 again via the connection pattern 29 where the gate line 3 is located.

The pixel electrode 23, the pixel electrode bars 23a, the common electrodes 25 and 27, the common electrode bars 25a and 27a, and the connection pattern 29 may be made of ITO or IZO that may transmit light.

According to the present invention, the common lines 5 and 5 'are disposed in the pixels P1 and P3 or P2 and P4 arranged along the first direction parallel to the gate line 3, and each pixel P1 and P3 or P2 is disposed. And common lines 5 and 5 'of P4 are connected by common link lines, and are connected to the pixels P1 and P2 or P3 and P4 arranged along a second direction parallel to the data lines 17 and 19. The common electrodes 25 and 27 are disposed, and the common electrodes 25 and 27 of the pixels P1 and P2 or P3 and P4 are connected by the connection pattern 29 to thereby common the pixels P1 to P4. The voltage can be maintained at equipotential.

In addition, the present invention also provides data lines 17 and 19 between the common electrodes 25 and 27 of the pixels P1 and P2 or P3 and P4 arranged in a second direction parallel to the data lines 17 and 19. By forming the connection pattern 29 thereon, the repair may be performed when a line break occurs.

Therefore, in the present invention, a mesh structure is formed by the common lines 5 and 5 'and the common electrodes 25 and 27, and a repair function may be performed using the connection pattern 29.

In addition, the present invention compares the repair pattern and the connection pattern with the common electrodes 25 and 27 of each pixel P1 and P2 or P3 and P4, compared to conventionally disposing a connection pattern connecting the repair pattern and the common electrode. By locally connecting the connected connection patterns 29 on the data lines 17 and 19, the conventional connection patterns are not required, so that the size of the pixel is increased and the aperture ratio is increased, thereby increasing the common electrode 25 and 27. The overlap area of the pixel electrode 23 and the pixel electrode 23 may be increased to increase the capacitance of the storage capacitance.

6A through 6D are process diagrams illustrating a manufacturing process of a liquid crystal display according to the present invention.

As shown in FIG. 6A, a gate line 3, a common line 5, a contact pad 7, and a common link line are formed on the substrate 1.

The gate line 3, the common line 5, the contact pad 7 and the common link line may be formed of the same material by the same process.

The common line 5, the contact pad 7 and the common link line may be integrally formed.

The common line 5 may be formed in a '-' shape in each of the pixels P1 to P4. The common link line electrically connects the common line 5 of each pixel P1 and P3 or P2 and P4.

As shown in FIG. 6B, a gate insulating film 9 is formed on the substrate 1 including the gate line 3, the common line 5, the contact pads 7, and the common link line.

Next, the semiconductor layer 11 is formed on the gate insulating film 9 corresponding to the gate line 3.

The data lines 17 and 19 and the source / drain electrodes 13a and 13b are formed on the substrate 1 including the semiconductor layer 11.

The data lines 17 and 19 and the source / drain electrodes 13a and 13b may be formed of the same material by the same process. The data lines 17 and 19 and the source electrode 13a may be integrally formed. The drain electrode 13b is formed spaced apart from the source electrode 13a. The source / drain electrodes 13a and 13b may be formed to locally overlap the semiconductor layer 11.

Accordingly, the thin film transistor 15 may be formed by the gate line 3, the semiconductor layer 11, and the source / drain electrodes 13a and 13b.

As shown in FIG. 6C, a protective film is formed on the substrate 1 including the data lines 17 and 19 and the source / drain electrodes 13a and 13b. The passivation layer may include a first contact hole 31 formed to expose the drain electrode 13b and second contact holes 33a and 33b formed to expose the contact pad 7.

As shown in FIG. 6D, the pixel electrode 23, the pixel electrode bars 23a, the common electrodes 25 and 27, the common electrode bars 25a and 27a and the connection pattern 29 are disposed on the passivation layer 21. Form.

The pixel electrode 23, the pixel electrode bars 23a, the common electrodes 25 and 27, the common electrode bars 25a and 27a, and the connection pattern 29 may be formed of the same material by the same process.

The pixel electrode 23 and the common electrodes 25 and 27 may be formed to face each other. The pixel electrode bars 23a may extend from the pixel electrode 23, and the common electrode bars 25a and 27a may extend from the common electrodes 25 and 27.

The pixel electrode 23 and the common electrodes 25 and 27 may be formed to be parallel to the data lines 17 and 19.

The pixels P1 to P4 include first and second domains.

The pixel electrode bars 23a of the first domain may be formed to extend in the diagonal directions of the right and upper sides, and the pixel electrode bars 23a of the second domain may be formed to extend in the diagonal directions of the right and lower sides.

The common electrode bars 25a and 27a of the first domain are formed to extend in the left and lower diagonal directions, and the common electrode bars 25a and 27a of the second domain are formed to extend in the diagonal directions of the left and upper sides. Can be.

The pixel electrode bars 23a and the common electrode bars 25a and 27a may be alternately formed.

Accordingly, the pixel electrode bars 23a of the first domain and the pixel electrode bars 23a of the second domain may be symmetrically formed in the boundary regions of the first and second domains. In addition, the common electrode bars 25a and 27a of the first domain and the common electrode bars 25a and 27a of the second domain may be symmetrically formed in the boundary regions of the first and second domains.

As such, the pixel electrode bars 23a and the common electrode bars 25a and 27a formed in the first domain, and the pixel electrode bars 23a and the common electrode bars 25a and 27a formed in the second domain are formed of the first and second electrodes. By being symmetrical with each other in the boundary region of the domain, the viewing angle can be further widened.

The pixel electrode 23 is electrically connected to the drain electrode 13b through the first contact hole 31, and the common electrodes 25 and 27 are connected to the contact pad 7 through the second contact holes 33a and 33b. Can be electrically connected to the

The common electrodes 25 and 27, the common electrode bars 25a and 27a, and the connection pattern 29 may be integrally formed.

The connection pattern 29 may be formed to overlap the data line 19 at the intersection of the gate line 3 and the data line 19. More specifically, the connection pattern 29 may be disposed to overlap the data line 19 of the crossing area and the data line 19 adjacent to the crossing area. Accordingly, the length of the connection pattern 29 may range from 5 times to 10 times the width of the gate line 3.

As such, the first and second pixels P1 and P2 are formed such that the connection pattern 29 overlaps the intersecting area and the data line 19 adjacent to the intersecting area, while the two sides are separated by the gate line 3. As it is electrically connected to the common electrodes 25 and 27 disposed in the structure, not only a function as a common electrode but also a repair function may be implemented.

Therefore, the connection patterns 29 connecting to the common electrodes 25 and 27 of the first and second pixels P1 and P2 and the repair patterns disposed in the intersecting regions for the repair are separately formed. The reduction of the aperture ratio and the capacity reduction of the storage capacitance can be prevented.

1 is a diagram illustrating a repair structure of a conventional liquid crystal display.

2 is a plan view illustrating a liquid crystal display according to the present invention.

3 is a cross-sectional view taken along lines II ′ and II-II ′ of FIG. 2.

FIG. 4 is a diagram illustrating a structure of a common line in FIG. 2.

FIG. 5 is a diagram illustrating the structure of a pixel electrode, a common electrode, and a connection pattern in FIG. 2.

6A through 6D are process diagrams illustrating a manufacturing process of a liquid crystal display according to the present invention.

<Explanation of symbols for the main parts of the drawings>

1: substrate 3: gate line

5, 5 ': common line 7, 7': contact pad

9: gate insulating film 11: semiconductor layer

13a: source electrode 13b: drain electrode

15: thin film transistor 17, 19: data line

21: protective film 23: pixel electrode

23a: pixel electrode bars 25 and 27: common electrode

25a and 27a: common electrode bars 29: connection pattern

31: first contact hole 33a, 33b: second contact hole

Claims (10)

Including a plurality of pixels arranged in a matrix, Each pixel, Gate line; A data line crossing the gate line; A thin film transistor connected to the gate line and the data line; A pixel electrode connected to the thin film transistor; A common electrode disposed adjacent to the pixel electrode; And A common line connected to the common electrode and disposed adjacent to the gate line and the data line, And a connection pattern arranged around the intersection of the gate line and the data line and overlapping the data line and connected to a common electrode of adjacent pixels. The liquid crystal display of claim 1, wherein the common lines of adjacent pixels are connected by a common link line. The liquid crystal display device of claim 1, wherein a length of the connection pattern is in a range of 5 to 10 times the width of the gate line. The method of claim 1, further comprising: a contact pad extending from a common line of the first pixel among adjacent pixels and disposed in the second pixel; And the common electrode is connected to the contact pad. The liquid crystal display of claim 1, wherein the common line is disposed in a '-' shape adjacent to the gate line and the data line. The display device of claim 1, further comprising: pixel electrode bars extending from the pixel electrode; And And a common electrode bar alternately disposed with the pixel electrode bars and extending from the common electrode. The method of claim 6, wherein each of the pixels includes first and second domains, The pixel electrode bars and the common electrode bars of the first domain, and the pixel electrode bars and the common electrode bars of the second domain are symmetrically disposed in a boundary area between the first and second domains. . Forming a gate line, a common line and a contact pad on the substrate; Forming a gate insulating film on the substrate including the gate line, the common line, and the contact pad; Forming a semiconductor layer on the gate insulating layer corresponding to the gate line; Forming a data line and a source / drain electrode on the substrate including the semiconductor layer; Forming a passivation layer having first and second contact holes on a substrate including the data line and the source / drain electrodes; And Forming a pixel electrode, a common electrode, and a connection pattern on the passivation layer; And wherein the connection pattern is arranged to overlap the data line around an intersection area of the gate line and the data line, and is connected to a common electrode of adjacent pixels. The method of claim 8, wherein the connection pattern has a length ranging from 5 times to 10 times the width of the gate line. The method of claim 8, A contact pad extending from a common line of the first pixel among adjacent pixels and disposed in the second pixel, The common electrode is connected to the contact pad, The common line of the adjacent pixels are connected by a common link line.

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