KR20090120772A - Liguid crystal display device and method for fabricating the same - Google Patents

Abstract

PURPOSE: A liquid crystal display and a manufacturing method thereof for securing a storage capacitor without the deterioration of the deterioration of the aperture ratio are provided to reduce the CD(Critical Dimension) of a pixel electrode by a process deviation. CONSTITUTION: A common voltage partial line(105) is branched at each pixel of a substrate(101). The common voltage line is crossed with a data line(103). The common voltage line is parallel formed with a gate line. A common electrode is numerously branched from the common voltage line. The common electrode is parallel formed with data line. A pixel electrode is branched in order to cross with the common electrode. The pixel electrode forms the horizontal electric field with the common electrode.

Description

Liquid crystal display and its manufacturing method {LIGUID CRYSTAL DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a method of manufacturing the same. In particular, no disclination occurs in an area adjacent to the end of the pixel electrode and the end of the common electrode, and a sufficient storage capacitor can be secured without lowering the aperture ratio. The present invention relates to a liquid crystal display device and a method of manufacturing the same, by minimizing the difference between the vertical distance between the common electrode and the pixel electrode to prevent the afterimage problem.

BACKGROUND ART In general, liquid crystal display devices have tended to be gradually widened due to their light weight, thinness, and low power consumption. Accordingly, the liquid crystal display device is widely used as a means for displaying a screen in portable computers, mobile phones, office automation equipment and the like.

In general, a liquid crystal display device displays a desired image on a screen by adjusting the amount of light transmitted according to image signals applied to a plurality of control switching elements arranged in a matrix.

The liquid crystal display device includes a liquid crystal panel in which a color filter substrate as an upper substrate and a thin film transistor array substrate as a lower substrate are opposed to each other, and a liquid crystal layer is filled between the two substrates, and a scan signal and image information are supplied to the liquid crystal panel. And a driving unit for operating the liquid crystal panel.

A conventional liquid crystal display device having such a configuration will be described below with reference to the accompanying drawings.

As shown in FIG. 1, a general liquid crystal display device includes a first substrate 1, which is a thin film transistor substrate, and a second substrate (not shown), which is a color filter substrate, and are vertically and horizontally disposed on the first substrate 1. The gate line 2 and the data line 3 defining a plurality of pixels are formed to cross each other.

A thin film transistor 4 including a gate electrode 4a, a source electrode 4b, and a drain electrode 4c is formed in an area where the gate line 2 and the data line 3 of each pixel cross each other. A plurality of pixel electrodes 7 are formed in the pixel so as to be connected to the drain electrode 4c of the thin film transistor 4 in the pixel. Here, the pixel electrode 7 is in contact with the first contact hole 15 through the pixel electrode connecting part 8 to be connected to the drain electrode 4c of the thin film transistor 4, but is not shown in detail in the drawing. The first contact hole 15 is a hole formed in a protective film (not shown). Here, the gate insulating film is a layer formed on the gate electrode 4a, and the protective film is a layer formed on the source electrode 4b and the drain electrode 4c.

Each pixel includes a common electrode 6 arranged to be alternately spaced apart from the pixel electrode 7 at a predetermined interval, and a common voltage portion line 5 is formed at an edge of each pixel. The electrode 6 is in contact with the common voltage partial line 5 through the second contact hole 16. Although not shown in detail in the drawing, the second contact hole 16 is a hole formed simultaneously in the gate insulating film (not shown) and the protective film (not shown).

In the conventional general liquid crystal display having such a configuration, the common voltage partial line 5 formed at the edge of each pixel occupies a large area in the pixel without contributing more than the role of applying the common voltage to the common electrode 6. There is a problem. In the common voltage partial line 5, only the region overlapping the pixel electrode connection 8 forms the storage capacitor Cst. Thus, the pixel electrode connection part is required to secure a sufficient storage capacitor required for driving the liquid crystal display. It is necessary to increase the area where (8) and the common voltage partial line 5 overlap, in which case there is a problem that the aperture ratio is lowered.

In the conventional liquid crystal display device having the above-described configuration, since the common electrode 6 and the pixel electrode 7 formed in each pixel are formed of the same material on the same layer, the CD (critical dimension) changes due to process dispersion. Is sensitively generated, which causes a problem that the variation range of the gray curve becomes large.

In addition, in the conventional general liquid crystal display device having the above-described configuration, since the pixel electrode 6 and the common electrode 7 are formed on the same layer, the pixel electrode connection portion 8 and the pixel electrode connection portion 8 are formed at both ends of the pixel electrode 6. One end connected to the common electrode 7 may not be formed at the left and right sides, and one end connected to the common voltage partial line 8 is positioned at both ends of the common electrode 7 such that the pixel electrode 6 is positioned at the left and right. It is impossible to form, and this causes a foreground line to occur in the areas adjacent to both ends of the pixel electrode 6 and the common electrode 7, resulting in a decrease in luminance and contrast ratio.

In the conventional liquid crystal display having the above configuration, as described above, since the first contact hole 15 and the second contact hole 16 are formed in the pixel, the layer is formed in the process of forming the protective film. In the overlap (layer overlap) has a disadvantage that requires precise work.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to secure a sufficient storage capacitor without lowering the aperture ratio, and to change the CD (critical dimension) of the common electrode and the pixel electrode caused by process dispersion. Minimization, generation of foreground lines (disclination) in the area adjacent to the end of the pixel electrode and the end of the common electrode is minimized, and since no contact hole is formed in the pixel, in the layer overlap process in forming the passivation layer The present invention provides a liquid crystal display device and a method of manufacturing the same, which do not require precise work.

According to an exemplary embodiment of the present invention, a liquid crystal display includes: a substrate in which a plurality of pixels are defined by crossing a gate line and a data line; A thin film transistor formed at an area where the gate line and the data line of each pixel of the substrate cross each other and having a gate electrode, a source electrode, and a drain electrode; A common voltage partial line branched at each pixel of the substrate to cross the data line and be parallel to the gate line; A plurality of common electrodes branched from the common voltage partial line to be parallel to the data lines; And a pixel electrode which is branched into a plurality of staggered mutually with the common electrode to form a horizontal electric field together with the common electrode. The gate line, the gate electrode, the common voltage partial line, and the common electrode are formed to include a first gate layer formed of the same material on the same layer, and the gate line, the gate electrode, and the common voltage partial line. Is formed by including a second gate layer on the first gate layer, and the data line, the source electrode, the drain electrode, and the pixel electrode are formed by including a first source / drain layer formed of the same material on the same layer. The line, source electrode, and drain electrode are formed including a second source / drain layer on the first source / drain layer.

In addition, a method of manufacturing a liquid crystal display according to an exemplary embodiment of the present invention for achieving the above object comprises the steps of preparing a substrate in which a plurality of pixels are defined; A gate line, a gate electrode, a common voltage partial line, and a common electrode including a first gate layer are formed on the substrate using a first mask, and the gate line, the gate electrode, and the common voltage partial line are formed on the first gate layer. Forming a second gate layer on the substrate; Forming a gate insulating layer on the gate line, the gate electrode, the common voltage partial line, and the common electrode; Forming an active layer on the gate insulating layer so as to overlap a portion of the gate electrode by using a second mask; And a data line, a source electrode, a drain electrode, and a pixel electrode including a first source / drain layer on the substrate using a third mask, wherein the data line, the source electrode, and the drain electrode are formed of a first source / drain layer. Forming a second source / drain layer on the substrate; It is made, including.

According to the present invention having the above-described configuration and manufacturing method, since the common electrode and the pixel electrode are formed on different layers, the CD (critical dimension) change of the common electrode and the pixel electrode due to process dispersion is small.

In addition, according to the present invention having the above-described configuration and manufacturing method, the common voltage partial line is formed such that the predetermined area overlaps the first and second pixel electrode connection lines with the gate insulating film interposed therebetween. It is possible to form the common electrode so that the pixel electrode is positioned to the left and right of both ends of the common electrode, so that the foreground line does not occur in the region adjacent to both ends of the pixel electrode and the region adjacent to both ends of the common electrode. have.

In addition, according to the present invention comprising the above-described configuration and manufacturing method, since the pixel electrode is formed on the same layer as the drain electrode of the thin film transistor, a contact hole for the purpose of connecting the pixel electrode and the drain electrode is not necessary. Since the common electrode is formed on the same layer with the same material as the common voltage connection line, a contact hole for the purpose of connecting the common electrode and the common voltage connection line is not necessary. The advantage is that no work is required.

Hereinafter, a liquid crystal display and a manufacturing method thereof according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

First, a configuration of a liquid crystal display according to a preferred embodiment of the present invention will be described with reference to FIGS. 2 and 3 as follows.

2 and 3, the liquid crystal display according to the exemplary embodiment of the present invention includes a first substrate 101 in which a plurality of pixels are defined by the gate line 102 and the data line 103 crossing each other. ; It is formed in an area where the gate line 102 and the data line 103 of each pixel of the first substrate 101 cross each other, and include a gate electrode 104a, a source electrode 104b, and a drain electrode 104c. Thin film transistor 104; A common voltage partial line 105 branched at each pixel of the first substrate 101 to cross the data line 103 and be parallel to the gate line 102; A common electrode 106 branched from the common voltage partial line 105 to be parallel to the data line 103; And a pixel electrode 107 which is divided into a plurality of staggered with the common electrode 106 to form a horizontal electric field together with the common electrode 106; It is configured to include. Here, the gate line 102, the gate electrode 104a, the common voltage partial line 105, and the common electrode 106 may be formed to include the first gate layer 110a formed of the same material on the same layer. The gate line 102, the gate electrode 104a, and the common voltage subline 105 are formed to include the second gate layer 110b on the first gate layer 110a, and the data line 103 and the source electrode. 104b, the drain electrode 104c, and the pixel electrode 107 are formed to include the first source / drain layer 109a formed of the same material on the same layer, and the data line 103 and the source electrode 104b. The drain electrode 104c is formed including a second source / drain layer 109b on the first source / drain 109a layer.

Each component of the liquid crystal display according to the preferred embodiment of the present invention having such a configuration will be described in detail as follows.

Although not shown in detail in the drawings, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel including a first substrate 101 which is a thin film transistor array substrate and a second substrate which is a color filter substrate (not shown). A liquid crystal layer (not shown) is formed between the first substrate 101 and the second substrate.

Referring to FIG. 2, a gate line 102 and a data line 103 are formed on the first substrate 101 to cross each other longitudinally and horizontally to define a plurality of pixels, and the gate line 102 and the data of each pixel are formed. The thin film transistor 104 is formed in an area where the line 103 intersects and is connected to the gate line 102 and the data line 103.

Each pixel includes a plurality of pixel electrodes 107 branched in parallel with the data line 103 to be connected to the drain electrode 104a. In addition, each pixel includes a first pixel electrode connection line 108a connecting lower ends of the plurality of pixel electrodes 107 and a second pixel electrode connection line 108b connecting upper ends of the plurality of pixel electrodes 107. ) Is formed. The lower end of the pixel electrode 107 is a region relatively adjacent to the gate line 102 connected to the pixel, and the upper end of the pixel electrode 107 is relatively spaced apart from the gate line 102 connected to the pixel. Area.

Referring to FIG. 2, the first pixel electrode connection line 108a is directly connected to the drain electrode 104c of the thin film transistor 104 in the pixel, and the second pixel electrode connection line 108b is a pixel in the pixel. The electrode 107 is indirectly connected to the drain electrode 104c of the thin film transistor 104.

As such, the second pixel electrode connection line 108b connecting the upper end of the pixel electrode 107 may be formed with the pixel electrode 107 and the common electrode 106 interposed between the gate insulating layer 104d. This is because they are formed in different layers from each other.

Referring to FIG. 2, the thin film transistor 104 may include a gate electrode 104a formed on the first substrate 101, a gate insulating film 104d formed on the gate electrode 104a, and the gate insulating film 104d. ) And an active layer 104e formed on the active layer 104e, and a source electrode 104b and a drain electrode 104c formed on the active layer 104e.

The gate electrode 104a of the thin film transistor 104 is connected to the gate line 102 by being integrally formed on the same layer using the same material as the gate line 102, and the source electrode 104b is connected to a data line ( It is connected to the data line 103 by being integrally formed on the same layer using the same material as that of 103, and the drain electrode 104c is integrally formed on the same layer by using the same material as the pixel electrode 107. It is connected to the electrode 107.

2 and 3, the source electrode 104b, the data line 103, the drain electrode 104c and the pixel electrode 107 may be formed of the same material on the same layer as the first source / drain layer 109a. The source electrode 104b, the data line 103, and the drain electrode 104c are further formed to include a second source / drain layer 109b on the first source / drain layer 109a. .

That is, the pixel electrode 107 is formed of a single layer consisting of only the first source / drain layer 109a, and the source electrode 104b, the data line 103 and the drain electrode 104c are formed of the first source / drain. It is formed of a double layer consisting of a drain layer 109a and a second source / drain layer 109b. In this case, the first source / drain layer 109a is formed of a conductive metal, and serves to serve as a signal transmission line and to increase adhesion of the line or to improve contact resistance. It is a barrier layer.

3 illustrates that the first and second pixel electrode connection lines 108a and 108b are formed of a double layer including a first source / drain layer 109a and a second source / drain layer 109b. The first and second pixel electrode connection lines 109a and 109b may be partially or entirely formed of the first source / drain layer 109a without departing from the gist of the present invention. It is possible.

The first source / drain layer 109a is formed of one selected from molybdenum (Mo), molybdenum alloy, and chromium (Cr), and the second source / drain layer 109b is made of aluminum (Al) and aluminum alloy (Al). , Copper (Cu) is formed of any one selected.

Although not shown in the drawing, a common voltage line (not shown) for supplying a common voltage to the common electrode 106 is formed on the first substrate 101.

Referring to FIG. 2, a common voltage partial line 105 is formed in each pixel including a region formed to branch from a common voltage line to cross the data line 103 and be parallel to the gate line 102. The voltage partial line 105 applies a common voltage from the common voltage line to the common electrode 106 of each pixel.

2 and 3, the common electrode 106 is formed by diverging from the common voltage partial line 105 so as to cross the pixel electrode 107, and forms a horizontal electric field together with the pixel electrode 107. To drive the liquid crystal layer.

The common electrode 106 is formed on a different layer from the pixel electrode 107. Thus, the CD (critical dimension) change of the common electrode 106 and the pixel electrode 107 due to process dispersion is small. have.

Referring to FIG. 2, a portion of the common voltage partial line 105 overlaps a portion of the first and second pixel electrode connection lines 108a and 108b with the gate insulating layer 104d therebetween, so that the storage capacitor ( Cst1 and Cst2 are formed to overlap the first pixel electrode connection line 108a to form the first storage capacitor Cst1 and overlap the second pixel electrode connection line 108b to form the second storage capacitor Cst2. Form.

As a result, sufficient storage capacitors Cst1 and Cst2 can be secured as compared with conventional liquid crystal displays without sacrificing the aperture ratio.

As such, the common voltage partial line 105 overlaps a predetermined area with the first and second pixel electrode connection lines 108a and 108b with the gate insulating layer 104d interposed therebetween. Since the common electrode 106 is located at the left and right and the pixel electrodes 107 are positioned at the left and right at both ends of the common electrode 106, the regions adjacent to both ends of the pixel electrode 107 and at both ends of the common electrode 106 are located. This is advantageous in that foreground lines do not occur in adjacent areas.

2 and 3, the gate electrode 104a, the gate line 102, the common voltage partial line 105, and the common electrode 106 are formed of the same material on the same layer as the first gate layer 110a. The gate electrode 104a, the gate line 102, and the common voltage partial line 105 may further include a second gate layer 110b on the first gate layer 110a.

That is, the common electrode 106 is formed of a single layer composed of only the first gate layer 110a, and the gate electrode 104a, the gate line 102, and the common voltage partial line 105 are formed of a first gate layer ( It is formed of a double layer consisting of 110a) and the second gate layer (110b). In this case, the first gate layer 110a is formed of a conductive metal, and serves as a signal transmission line, and at the same time, a barrier layer provided for the purpose of increasing the adhesion of the line or improving the contact resistance ( barrier layer).

The first gate layer 110a is formed of one selected from molybdenum (Mo), molybdenum alloy, and chromium (Cr), and the second gate layer 110b is made of aluminum (Al), aluminum alloy (Al), and copper (Cu). It is formed of any one selected.

In FIG. 3, the common voltage partial line 105 is formed as a double layer including a first gate layer 110a and a second gate layer 110b, but is not limited thereto. Within the range, the common voltage partial line 105 may be a variety of examples, such as a part or the entire area of the first gate layer 110a.

Referring to FIG. 3, in the gate insulating film 104d formed on the gate line 102, the gate electrode 104a, the common voltage subline 105, and the common electrode 106 as mentioned above, a thin film transistor The thickness of the region overlapping the active layer 104e of 104 is at least twice the thickness of the region overlapping the region other than the active layer 104e.

In addition, the thickness of the region of the gate insulating layer 104d overlapping with the active layer 104e of the thin film transistor 104 has a thickness of about 4000 GPa in order to secure the characteristics of the thin film transistor 104.

Accordingly, it can be seen that the thickness of the gate insulating layer 104d except for the region overlapping with the active layer 104e of the thin film transistor 104 is 2000 kPa or less.

Hereinafter, a method of manufacturing a liquid crystal display device according to an exemplary embodiment of the present invention will be described with reference to FIGS. 4A to 4O. In the description of the manufacturing method of the liquid crystal display according to the preferred embodiment of the present invention, the components not shown in FIGS. 4A to 4O will be referred to FIG. 2.

For reference, the first to third photosensitive films 203, 213, and 223 used in the following description are taken as a positive type in which the exposed portion is removed. However, the first to third photoresist films 203. 213 and 223 applied to the method of manufacturing the liquid crystal display according to the preferred embodiment of the present invention may have a negative type in which an unexposed part is removed.

First, a first substrate (see 101 in FIG. 4A) in which a plurality of pixels are defined is prepared.

Next, as shown in FIG. 4A, after the first metal layer 201, the second metal layer 202, and the first photosensitive film 203 are sequentially formed on the first substrate 101, the common electrode (refer to FIG. 4E). 106). First photolithography is performed using a first mask 204 provided with a diffraction region (or a semi-transmissive region) in the region where the first photoresist pattern is to be formed, as shown in FIG. 4B. To form.

In this case, the region of the first mask 204 corresponding to the common electrode (see 106 of FIG. 4E) to be formed later forms a diffraction region (or transflective region), and the gate line to be formed later (102 of FIG. 2). 4), the region corresponding to the gate electrode (see 104a in FIG. 4e), the common voltage subline (see 105 in FIG. 4e) and the gate pad (see 111 in FIG. 4e) constitute a non-transmissive region, and the diffraction region and the non-transmissive region The remaining areas except the one constitute a transmissive area. Of course, the structure of the first mask 204 is according to the case of a positive type, but when the first mask is a negative type, the non-transmissive area and the transmissive area are opposite as compared to the case of a positive type. Will be.

In addition, the first photoresist pattern 203a has a thickness thinner than a region corresponding to the non-transmissive region of the first mask 204 and a region corresponding to the diffractive region of the first mask 204 and corresponds to the transmission region. All of these have a removed shape.

Next, the second metal layer 202 and the first metal layer 201 are selectively removed using the first photoresist layer pattern 203a, so that the second metal layer pattern 202a and the first metal layer as shown in FIG. 4C are removed. The metal layer pattern 201a is formed.

Next, all regions corresponding to the diffraction regions of the first mask 204 in the first photoresist pattern 203a are removed to form a second photoresist pattern 203b as illustrated in FIG. 4D. Here, the second photoresist pattern 203b has a shape in which only a region corresponding to the non-transmissive region of the first mask 204 is left and all regions corresponding to the diffraction region and the transmission region are removed.

Next, the second metal layer pattern 202a and the first metal layer pattern 201a are selectively removed using the second photoresist layer pattern 203b, and as shown in FIG. 4E, the first gate layer 110a and the first gate layer 110a and the second metal layer pattern 203b are removed. A gate line (see 102 in FIG. 2), a gate electrode 104a, and a common voltage subline 105 formed of the second gate layer 110b are formed, and a common electrode 106 formed of the first gate layer 110a is formed. do.

Although the common voltage partial line 105 of the liquid crystal display according to the preferred embodiment of the present invention is formed of the first gate layer 110a and the second gate layer 110b as an example, the present invention is not limited thereto. The common voltage partial line 105 may be modified in various ways, such that a part or the entire area is formed only of the first gate layer 110a without departing from the gist of the present invention.

Next, as shown in FIG. 4F, the gate is formed on the first substrate 101 on which the gate line (see 102 of FIG. 2), the gate electrode 104a, the common voltage partial line 105, and the common electrode 106 are formed. After the insulating film 104d, the semiconductor layer 205, and the second photosensitive film 213 are formed in sequence, other than the regions other than the active layer (see 104e in FIG. 4J) to be formed later and other gate pad holes (see 112 in FIG. 4H) A second photolithography is performed using a second mask 214 provided with a diffraction region in a region corresponding to the region of the to form a third photoresist pattern 213a as shown in FIG. 4G.

In this case, the second mask 214 is a region corresponding to an active layer to be formed later (see 104e in FIG. 4J) to form a non-transparent region, and a region corresponding to the gate pad hole to be formed later (see 112 in FIG. 4H). Is a transmission region, and the remaining region except for the non-transmissive region and the transmission region forms a diffraction region (or semi-transmissive region).

In addition, the third photoresist pattern 213a has a thickness that is thinner than that of the region corresponding to the non-transmissive region of the second mask 214 and the region corresponding to the diffraction region of the second mask 214, and corresponds to the transmission region. All of these have a removed shape.

Next, the semiconductor layer 205 and the gate insulating layer 104d are selectively removed using the third photoresist pattern 213a to expose a portion of the gate pad 111 as shown in FIG. 4H. The hole 112 is formed.

Next, all of the regions corresponding to the diffraction regions of the second mask 214 in the third photoresist pattern 213a are removed to form the fourth photoresist pattern 213b as illustrated in FIG. 4I. Here, the fourth photoresist pattern 213b has a shape in which only a region corresponding to the non-transmissive region of the second mask 214 remains and all regions corresponding to the diffraction region and the transmission region are removed.

Next, the semiconductor layer 205 is selectively removed using the fourth photoresist pattern 213b to form an active layer 104e as shown in FIG. 4J, and the fourth photoresist pattern 213b is used. By selectively removing the gate insulating film 104d, the thickness of the region overlapping with the active layer 104e in the gate insulating film 104d is at least 2 times the thickness of the region overlapping with the region other than the active layer 104e. Form to be doubled. At this time, the region overlapping with the active layer 104e in the gate insulating film 104d is preferably around 4000 mW to secure the characteristics of the thin film transistor 104. As a result, the common electrode 106 and the pixel electrode (see FIG. 107) is not more than 2000Å.

Next, as shown in FIG. 4K, the third metal layer 211, the fourth metal layer 212, and the third photosensitive film 223 are formed on the first substrate 101 on which the active layer 104e and the gate pad hole 112 are formed. ) Is formed in sequence, and a third photolithography is performed using a third mask 224 having a diffraction region in a region corresponding to a pixel electrode to be formed later (see 107 of FIG. 4O). A fifth photosensitive film pattern 223a is formed as shown.

In this case, the third mask 224 may be formed at a later data line (see 103 in FIG. 2), a source electrode (see 104b in FIG. 4O), a drain electrode (see 104c in FIG. 4O), and a first pixel electrode connection line ( 4A), a region corresponding to the second pixel electrode connection line (see 108B of FIG. 2) forms a non-transmissive region, and a region corresponding to the pixel electrode 107 to be formed later is a diffraction region (or semi-transmissive region). ), And the other regions except for the non-transmissive region and the diffraction region form a transmission region.

In addition, the fifth photoresist pattern 223a has a thickness that is thinner than that of the region corresponding to the non-transmissive region of the third mask 224, and the region corresponding to the diffraction region of the third mask 224, and corresponds to the transmission region. All of these have a removed shape.

Next, the fourth metal layer 212 and the third metal layer 211 are selectively removed using the fifth photosensitive film pattern 223a, and as shown in FIG. 4M, the fourth metal layer pattern 212a and the third metal layer. A pattern 211a is formed and an area corresponding to the gate pad hole 112 is exposed.

Next, all of the regions corresponding to the diffraction regions of the third mask 224 in the fifth photoresist pattern 223a are removed to form the sixth photoresist pattern 223b as illustrated in FIG. 4N. Here, the sixth photoresist pattern 223b has a shape in which only the region corresponding to the non-transmissive region of the third mask 224 remains and all regions corresponding to the diffraction region and the transmission region are removed.

Next, the fourth metal layer pattern 212a and the third metal layer pattern 211a are selectively removed using the sixth photoresist layer pattern 223b, and as shown in FIG. 4O, the first source / drain layer 109a. And a data line (see 103 in FIG. 2), a source electrode 104b, and a drain electrode 104c formed of a second source / drain layer 109b and a pixel electrode formed of the first source / drain layer 109a. After forming 107, the sixth photosensitive film pattern 223b is removed. At this time, the first pixel electrode connection line 108a and the second pixel electrode connection line (refer to 108b of FIG. 2) which connect the ends of the pixel electrode 107 in each pixel are also formed. Some or all of the first pixel electrode connection line 108a and the second pixel electrode connection line 108a (see 108b of FIG. 2) may be formed as the first source / drain layer 109a and the second source / drain layer 109b. Some regions overlap the common electrode connection line 106 to form first and second storage capacitors (see Cst1 and Cst2 of FIG. 2).

According to the present invention made of the above-described configuration and manufacturing method, since the common electrode 106 and the pixel electrode 107 are formed on different layers from each other, the CD of the common electrode 106 and the pixel electrode 107 due to process dispersion ( critical dimension) has the advantage of less change.

In addition, the common voltage partial line 105 is formed to overlap a predetermined area with the first and second pixel electrode connection lines 108a and 108b with the gate insulating layer 104d interposed therebetween. The common electrode 106 may be disposed at the pixel electrode 107, and the pixel electrode 107 may be positioned at left and right ends of the common electrode 106. There is an effect that the foreground discretization does not occur in an area adjacent to both ends.

The common voltage partial line 105 overlaps the first pixel electrode connection line 108a to form the first capacitor Cst1 and overlaps the second pixel electrode connection line 108b to form the second capacitor Cst2. As a result, compared with the conventional liquid crystal display device, there is an advantage in that sufficient storage capacitors Cst1 and Cst2 can be secured without lowering the aperture ratio.

Further, since the pixel electrode 107 is formed on the same layer as the drain electrode 104c of the thin film transistor 104, a contact hole for connecting the pixel electrode 107 and the drain electrode 104c is not necessary. In addition, since the common electrode 106 is formed on the same layer as the common voltage connection line 105, a contact hole for connecting the common electrode 106 and the common voltage connection line 105 is not necessary. In the process of forming (not shown), there is an advantage that precise work is not required in layer overlap.

1 is a plan view showing a conventional general liquid crystal display device.

2 is a plan view showing a liquid crystal display according to a preferred embodiment of the present invention.

3 is a cross-sectional view taken along the lines II ′ and II-II ′ of FIG. 2.

4A to 4O are cross-sectional views illustrating steps of manufacturing the liquid crystal display of FIG. 3.

** Description of the symbols for the main parts of the drawings **

101: first substrate

102 gate line 103 data line

104: thin film transistor 104a: gate electrode

104b: source electrode 104c: drain electrode

104d: gate insulating film 104e: active layer

105: common voltage partial line 106: common electrode

107: pixel electrode

108a: first pixel electrode connection line 108b: second pixel electrode connection line

109a: first source / drain layer 109b: second source drain layer

110a: first gate layer 110b: second gate layer

111: gate pad 112: gate pad hole

Claims (15)

A substrate in which a plurality of pixels are defined by crossing a gate line and a data line with each other; A thin film transistor formed at an area where the gate line and the data line of each pixel of the substrate cross each other and having a gate electrode, a source electrode, and a drain electrode; A common voltage partial line branched at each pixel of the substrate to cross the data line and be parallel to the gate line; A plurality of common electrodes branched from the common voltage partial line to be parallel to the data lines; And A pixel electrode which is divided into a plurality of the common electrodes so as to cross the common electrode and forms a horizontal electric field together with the common electrode; It is configured to include, The gate line, the gate electrode, the common voltage partial line, and the common electrode may include a first gate layer formed of the same material on the same layer, and the gate line, gate electrode, and common voltage partial line may be formed on the first gate layer. Is formed including two gate layers, The data line, the source electrode, the drain electrode, and the pixel electrode may include a first source / drain layer formed of the same material on the same layer, and the data line, the source electrode, and the drain electrode may be formed on the first source / drain layer. A liquid crystal display comprising two source / drain layers. The gate insulating layer of claim 1, wherein a gate insulating layer is formed on the gate line, the gate electrode, the common voltage partial line, and the common electrode. And the thickness of the region overlapping with the active layer in the gate insulating layer is at least twice the thickness of the region overlapping with the region other than the active layer. The liquid crystal display device according to claim 2, wherein a vertical distance between the common electrode and the pixel electrode is 2000 m or less. The liquid crystal display of claim 1, wherein the common electrode and the common voltage partial line are integrally formed through a first gate layer. The liquid crystal display of claim 1, wherein the pixel electrode and the drain electrode are integrally formed through a first source / drain layer. The method of claim 1, wherein each pixel is formed with a pixel electrode connection line connecting the ends of the plurality of pixel electrodes, And a portion of the pixel electrode connection line overlaps a portion of the common voltage partial line to form a storage capacitor. The pixel electrode connection line of claim 6, wherein the pixel electrode connection line comprises a first pixel electrode connection line connecting a lower end of the pixel electrode, and a second pixel electrode connection line connecting an upper end of the pixel electrode. The storage capacitor includes a first storage capacitor formed by overlapping a first pixel electrode connection line and a common voltage partial line, and a second storage capacitor formed by overlapping a second pixel electrode connection line and a common voltage partial line. A liquid crystal display device. Preparing a substrate in which a plurality of pixels are defined; A gate line, a gate electrode, a common voltage partial line, and a common electrode including a first gate layer are formed on the substrate using a first mask, and the gate line, the gate electrode, and the common voltage partial line are formed on the first gate layer. Forming a second gate layer on the substrate; Forming a gate insulating layer on the gate line, the gate electrode, the common voltage partial line, and the common electrode; Forming an active layer on the gate insulating layer so as to overlap a portion of the gate electrode by using a second mask; And A data line, a source electrode, a drain electrode, and a pixel electrode including a first source / drain layer are formed on the substrate using a third mask, wherein the data line, the source electrode, and the drain electrode are formed on the first source / drain layer. Forming a second source / drain layer in the substrate; Method of manufacturing a liquid crystal display device comprising a. The method of claim 8, wherein the forming of the gate line, the gate electrode, the common voltage partial line, and the common electrode using the first mask comprises: Sequentially forming a first metal layer, a second metal layer, and a first photosensitive film on the first substrate; Forming a first photoresist pattern by performing first photolithography using a first mask having a diffraction region in a region where a common electrode is to be formed; Selectively removing the second metal layer and the first metal layer by using the first photoresist pattern to form a second metal layer pattern and a first metal layer pattern; Removing a region of the first photoresist pattern corresponding to the diffraction region of the first mask to form a second photoresist pattern; Selectively removing a second metal layer pattern and a first metal layer pattern using the second photoresist layer pattern to form a gate line, a gate electrode, and a common voltage partial line including the first gate layer and the second gate layer, and a first gate Forming a common electrode made of a layer; Method of manufacturing a liquid crystal display device comprising a. The method of claim 8, wherein in the forming of the active layer using the second mask, a gate pad hole is formed to expose a portion of the end of the gate line. Forming an active layer and a gate pad hole using the second mask, Forming a semiconductor layer and a second photosensitive film on the substrate; Forming a third photoresist pattern by performing second photolithography using a second mask having a diffraction region in regions other than the active layer and the gate pad hole to be formed later; Selectively removing a semiconductor layer and a gate insulating layer using the third photoresist pattern to form a gate pad hole; Removing a region corresponding to the diffraction region of the second mask in the third photoresist pattern to form a fourth photoresist pattern; Selectively removing a semiconductor layer using the fourth photoresist pattern to form an active layer; Method of manufacturing a liquid crystal display device comprising a. The method of claim 10, wherein the forming of the active layer by selectively removing the semiconductor layer using the fourth photoresist pattern The gate insulating film is selectively removed using the fourth photoresist pattern so that the thickness of the region overlapping with the active layer in the gate insulating film is at least twice the thickness of the region overlapping with the regions other than the active layer. Manufacturing method. 12. The method of claim 11, wherein a vertical distance between the common electrode and the pixel electrode formed with the gate insulating layer interposed therebetween is 2000 [mu] s or less. The method of claim 8, wherein the forming of the data line, the source electrode, the drain electrode, and the pixel electrode using the third mask comprises: Sequentially forming a third metal layer, a fourth metal layer, and a third photosensitive film on the substrate; Forming a fifth photoresist pattern by performing third photolithography using a third mask; The third metal layer and the fourth metal layer may be selectively removed using the fifth photoresist pattern to form a data line, a source electrode, and a drain electrode including a first source / drain layer and a second source / drain layer. Forming a pixel electrode formed of a drain layer; Method of manufacturing a liquid crystal display device comprising a. The method of claim 7, wherein in the forming of the data line, the source electrode, the drain electrode, and the pixel electrode using the third mask, And a pixel electrode connection line connecting the ends of the pixel electrodes in each pixel, wherein a portion of the pixel electrode connection line forms a storage capacitor overlapping a portion of the common voltage subline. Method for manufacturing a display device. 15. The method of claim 14, wherein the pixel electrode connection line is formed to include a first pixel electrode connection line connecting the lower end of the pixel electrode and a second pixel electrode connection line connecting the upper end of the pixel electrode. The pixel electrode connection line and the common voltage partial line overlap to form a first storage capacitor, and the second pixel electrode connection line and the common voltage partial line overlap to form a second storage capacitor.

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