KR20090115433A - Method for inlaying chip in a card which is provided with antenna coil and IC chip - Google Patents

Method for inlaying chip in a card which is provided with antenna coil and IC chip Download PDF

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Publication number
KR20090115433A
KR20090115433A KR1020080041293A KR20080041293A KR20090115433A KR 20090115433 A KR20090115433 A KR 20090115433A KR 1020080041293 A KR1020080041293 A KR 1020080041293A KR 20080041293 A KR20080041293 A KR 20080041293A KR 20090115433 A KR20090115433 A KR 20090115433A
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KR
South Korea
Prior art keywords
integrated circuit
circuit chip
antenna coil
chip
card
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KR1020080041293A
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Korean (ko)
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KR101006870B1 (en
Inventor
이웅석
유인종
김동진
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(주)이.씨테크날리지
유인종
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Priority to KR1020080041293A priority Critical patent/KR101006870B1/en
Publication of KR20090115433A publication Critical patent/KR20090115433A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/0775—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card arrangements for connecting the integrated circuit to the antenna
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B42—BOOKBINDING; ALBUMS; FILES; SPECIAL PRINTED MATTER
    • B42D—BOOKS; BOOK COVERS; LOOSE LEAVES; PRINTED MATTER CHARACTERISED BY IDENTIFICATION OR SECURITY FEATURES; PRINTED MATTER OF SPECIAL FORMAT OR STYLE NOT OTHERWISE PROVIDED FOR; DEVICES FOR USE THEREWITH AND NOT OTHERWISE PROVIDED FOR; MOVABLE-STRIP WRITING OR READING APPARATUS
    • B42D25/00—Information-bearing cards or sheet-like structures characterised by identification or security features; Manufacture thereof
    • B42D25/40—Manufacture
    • B42D25/45—Associating two or more layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/12—Supports; Mounting means
    • H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
    • H01Q1/2208—Supports; Mounting means by structural association with other equipment or articles associated with components used in interrogation type services, i.e. in systems for information exchange between an interrogator/reader and a tag/transponder, e.g. in Radio Frequency Identification [RFID] systems
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/36—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith
    • H01Q1/38—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith formed by a conductive layer on an insulating support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525—Means for applying energy, e.g. heating means
    • H01L2224/75252—Means for applying energy, e.g. heating means in the upper part of the bonding apparatus, e.g. in the bonding head
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Credit Cards Or The Like (AREA)

Abstract

PURPOSE: A method for inlaying a chip to a card equipped with an antenna coil and an IC chip is provided to enable the card to be not bended after thermal compression by not forming the card mark in a small empty space. CONSTITUTION: An overlay layer(50) is put on the table. A core board(10) is laminated on the overlying layer for the bottom surface. The antenna coil is inlayed on the core board in the constant pattern. Both terminals of the antenna coil are located on a rim unit(10b) of a hole for the IC chip. A conductive adhesive is applied with the both terminals.

Description

안테나 코일과 집적회로 칩을 구비한 카드에 칩을 인레이하는 방법{method for inlaying chip in a card which is provided with antenna coil and IC chip}Method for inlaying chip in a card which is provided with antenna coil and IC chip}

본 발명은 안테나 코일과 집적회로 칩을 구비한 카드에 칩을 인레이하는 방법에 관한 것이다.The present invention relates to a method of inlaying a chip on a card having an antenna coil and an integrated circuit chip.

안테나 코일과 집적회로 칩을 인레이한 카드는, PVC, PC, PE, 종이 재질의 코어 보드를 보호층인 오버레이층에 의해 윗면 및 밑면이 적층되어 있다.In the card in which the antenna coil and the integrated circuit chip are inlaid, a top surface and a bottom surface are laminated on a core board made of PVC, PC, PE, or paper by an overlay layer serving as a protective layer.

상기 코어 보드의 상면에는, 안테나 코일이 배설되어 있고, 안테나 코일의 양 단자는 집적회로 칩의 입출력 단자와 도전성 접착제에 의해 접착되어 서로 전기적으로 접촉이 이루어져서, 상기 집적회로 칩의 상기 입출력 단자와 상기 안테나 코일의 양 단자가 서로 도전된 상태로 유지된다.An antenna coil is disposed on an upper surface of the core board, and both terminals of the antenna coil are bonded to each other by the conductive adhesive with the input / output terminal of the integrated circuit chip, and thus are electrically contacted with each other. Both terminals of the antenna coil are kept in a conductive state with each other.

상기 집적회로 칩은 베이스 필름 상에 부착되어 있다.The integrated circuit chip is attached on a base film.

상기와 같이 구성된 카드는 종래에는, 도 1에 도시된 바와 같은 방식으로 제조되었다.The card configured as described above is conventionally manufactured in the manner as shown in FIG.

먼저, 테이블 상에 밑면용 오버레이층(50)을 깔아 놓은 상태에서, 집적회로 칩을 삽입할 구멍(10a)이 펀치가공에 의해 형성된 코어 보드(10)를 적층시킨다.First, in a state where the bottom overlay layer 50 is laid on the table, the hole 10a into which the integrated circuit chip is to be inserted stacks the core board 10 formed by punching.

그 다음 베이스 필름(21)이 상기 구멍(10a)을 통하여 상기 밑면용 오버레이층(50) 상에 놓여져 아이씨 칩(22)의 몰드부분이 위를 향하게 상기 구멍(10a)으로부터 노출시키는 상태로, 상기 구멍(10a)에 상기 집적회로 칩(22)을 삽입한다.The base film 21 is then placed on the underlay overlay layer 50 through the holes 10a to expose the mold portion of the IC chip 22 from the holes 10a with the mold facing upwards. The integrated circuit chip 22 is inserted into the hole 10a.

그 다음, 상기 코어 보드(10) 상에 안테나 코일(14)을 일정 패턴으로 배설하되, 상기 안테나 코일(14)의 양 단자(15, 15')가 상기 구멍(10a)을 가로지르게 하여, 상기 베이스 필름(21) 상에 구비된 입출력 단자(17, 17')와 접촉하게 한다.Next, the antenna coil 14 is disposed on the core board 10 in a predetermined pattern, and both terminals 15 and 15 'of the antenna coil 14 cross the hole 10a. It comes into contact with the input / output terminals 17 and 17 'provided on the base film 21.

그 다음, 상기 접촉부에 도전성 접착제를 도포한다. Then, a conductive adhesive is applied to the contact portion.

그 다음, 상기 집적회로 칩(22)을 제외한 상기 베이스 필름(21) 구역과 상기 구멍(10a)을 제외한 모든 코어 보드(10) 구역 상에 적층되게 놓여 질 수 있도록 관통구멍(40A)이 형성된 충전층(40)을 상기 코어 보드(10) 상에 놓는다.Next, the fill hole 40A is formed so that it can be stacked on the base film 21 area except the integrated circuit chip 22 and all the core board 10 areas except the hole 10a. Layer 40 is placed on the core board 10.

그 다음, 윗면용 오버레이층(30)을 상기 충전층(40)과 집적회로 칩(22)을 커버하게 상기 충전층(40) 상에 적층시킨 다음 상기 적층된 것들을 열압착시킨다.Next, an upper overlay layer 30 is laminated on the charging layer 40 to cover the charging layer 40 and the integrated circuit chip 22, and then the laminated ones are thermocompressed.

상기와 같은 방식으로 집적회로 칩을 인레이하는 방법은 다음과 같은 문제가 있다.The method of inlaying an integrated circuit chip in the above manner has the following problems.

먼저, 집적회로 칩(22)을 부착하고 있는 상기 베이스 필름(21)을 상기 구멍(10a)에 정확하게 위치결정시켜야만 상기 안테나 코일(14)의 양 단자(15, 15')를 상기 베이스 필름(21) 상에 배설할 수 있게 되어, 정확한 위치결정작업 및 기계가 요구될 뿐만 아니라 전체적으로 공정이 복잡하다고 하는 문제가 있다.First, the base film 21 to which the integrated circuit chip 22 is attached must be correctly positioned in the hole 10a so that both terminals 15 and 15 'of the antenna coil 14 can be placed on the base film 21. It is possible to be excreted in the above, so that accurate positioning work and machinery are required, and the overall process is complicated.

또한, 상기 종래의 집적회로 칩 인레이 방법은 비 압착식으로 4개의 층을 적층시키는 방식이어서 그 구조가 비대칭적이고 층수가 4개의 층으로 되어 있어 카드 의 두께가 두꺼워 진다고 하는 문제가 있다.In addition, the conventional integrated circuit chip inlay method is a method of stacking four layers in a non-compression method, so that the structure is asymmetrical and the number of layers is four, resulting in a thick card.

또한, 상기 집적회로 칩(22)과 상기 베이스 필름(21)을 사이에 두고 상기 오버레이층(30, 50)과 충전층(40) 및 코어 보드(10)에 의해 구획형성된 빈 공간이 커서 열압축에 의한 빈 공간으로 인한 카드자국이 형성된다고 하는 문제가 있고, 아울러 열압축 후에도 빈 공간이 잔존하게 되어 카드의 강도가 낮아지고 카드가 쉽게 굽혀진다고 하는 문제가 있다.In addition, the thermal space is large because the empty space partitioned by the overlay layers 30 and 50, the filling layer 40, and the core board 10 with the integrated circuit chip 22 and the base film 21 interposed therebetween. There is a problem that the card marks are formed due to the empty space, and the empty space remains even after thermal compression, so that the strength of the card is lowered and the card is easily bent.

본 발명의 해결하고자 하는 과제는, 상기된 문제점을 해결하는 것에 있다.The problem to be solved of the present invention is to solve the above problems.

본 발명은, 상기 과제를 해결하기 위해, 테이블 상에 밑면용 오버레이층을 깔아 놓은 상태에서, 집적회로 칩을 삽입할 구멍이 펀치가공에 의해 형성된 코어 보드를 상기 밑면용 오버레이층 상에 적층시키는 단계; 상기 코어 보드 상에 안테나 코일을 일정 패턴으로 배설하되, 상기 안테나 코일의 양 단자가 상기 집적회로 칩용 구멍을 구획형성하고 있는 상기 집적회로 칩용 구멍 측의 테두리부에 위치되게 하는 단계; 상기 양 단자에 도전성 접착제를 도포하는 단계; 테두리부에 입출력 단자가 구비된 베이스 필름 상에 부착되어 돌출되어 있는 상기 집적회로 칩이 상기 집적회로 칩용 구멍을 통하여 삽입되어, 상기 집적회로 칩의 선단이 상기 밑면용 오버레이층과 면하고 있는 상태에서, 상기 베이스 필름의 테두리부가 상기 집적회로 칩용 구멍 측의 상기 테두리부에 걸치게 하여, 상기 입출력 단자에 도포된 상기 도전성 접착제와 접촉되게 하는 단계; 및 상기 코어 보드와 상기 베이스 필름을 커버하게, 상기 코어 보드 상에 윗면용 오버레이층을 적층시킨 다음 상기 적층된 것들을 열압착시키는 단계를 포함하는 것으로 되어 있다.The present invention, in order to solve the above problems, in the state of laying the bottom overlay layer on the table, the step of laminating a core board formed by the punching hole on the bottom overlay layer to insert the integrated circuit chip ; Disposing an antenna coil on the core board in a predetermined pattern, such that both terminals of the antenna coil are positioned at an edge portion of the hole side for the integrated circuit chip which defines the hole for the integrated circuit chip; Applying a conductive adhesive to both terminals; The integrated circuit chip, which is attached to the base film having an input / output terminal and protrudes from the edge portion, is inserted through the hole for the integrated circuit chip, and the tip of the integrated circuit chip faces the overlay layer for the bottom surface. And making the edge portion of the base film hang over the edge portion of the hole side for the integrated circuit chip to be in contact with the conductive adhesive applied to the input / output terminal; And laminating an overlay layer on the core board to cover the core board and the base film, and then thermally compressing the stacked ones.

본 발명은 상기와 같은 방법에 의해 정확한 위치결정작업이 요구되지 않아 공정이 단순하고, 압착식으로 3개의 층을 적층시키는 방식이어서 그 구조가 대칭적 이고 카드의 두께가 얇아지며, 빈 공간이 작아 카드자국이 거의 형성되지 않아서 열압축 후에도 카드의 강도가 낮아지지 않아서 카드가 쉽게 굽혀지지 않게 한다.The present invention does not require accurate positioning by the above method, so the process is simple, and the three layers are laminated by pressing, so that the structure is symmetrical, the thickness of the card is thin, and the empty space is small. Since card marks are hardly formed, the strength of the card does not decrease even after thermal compression, so that the card does not bend easily.

이하, 본 발명의 실시예에 따른 칩 실장 카드 제조 방법을 도 2 내지 도 4를 참조하여 상세히 설명될 것이다.Hereinafter, a method of manufacturing a chip mounting card according to an embodiment of the present invention will be described in detail with reference to FIGS. 2 to 4.

테이블 상에 밑면용 오버레이층(50)을 깔아 놓은 상태에서, 집적회로 칩을 삽입할 구멍(10a)이 펀치가공에 의해 형성된 코어 보드(10)를 적층시킨다.With the overlay layer 50 for the bottom laid on the table, the holes 10a for inserting the integrated circuit chips stack the core boards 10 formed by punching.

그 다음, 상기 코어 보드(10) 상에 안테나 코일(14)을 일정 패턴으로 배설하되, 상기 안테나 코일(14)의 양 단자(15, 15')가 상기 구멍(10a)을 구획형성하고 있는 상기 구멍(10a) 측의 테두리부(10b)에 위치되게 한다.Next, the antenna coil 14 is disposed on the core board 10 in a predetermined pattern, and both terminals 15 and 15 'of the antenna coil 14 partition the hole 10a. It is located in the edge portion 10b on the side of the hole 10a.

그 다음, 상기 양 단자(15, 15')에 도전성 접착제를 도포한다. Then, a conductive adhesive is applied to both terminals 15 and 15 '.

그 다음, 테두리부(21a)에 입출력 단자(17, 17')가 구비된 베이스 필름(21) 상에 부착되어 돌출되어 있는 집적회로 칩(22)이 상기 구멍(10a)을 통하여 삽입되어, 상기 집적회로 칩(22)의 선단이 상기 밑면용 오버레이층(50)과 면하고 있는 상태에서, 상기 베이스 필름(21)의 테두리부(21a)가 상기 테두리부(10b)에 걸치게 하여, 상기 입출력 단자(17, 17')에 도포된 도전성 접착제와 접촉되게 한다.Then, an integrated circuit chip 22 attached to the base film 21 provided with the input / output terminals 17 and 17 'at the edge portion 21a and protruding is inserted through the hole 10a. In the state where the tip of the integrated circuit chip 22 faces the overlay layer 50 for the bottom surface, the edge portion 21a of the base film 21 extends over the edge portion 10b, and thus the input / output It makes contact with the conductive adhesive applied to the terminals 17 and 17 '.

여기에서, 상기 집적회로 칩(22)은, 도 2에 도시된 바와 같이, 그 하단 모서리부가 모따기 처리되어 있으면, 상기 구멍(10a)에 삽입될 때 정확하게 상기 구멍(10a)의 중앙에 위치결정될 수 있다는 점에서 바람직하다.Here, the integrated circuit chip 22, as shown in Figure 2, if the bottom edge is chamfered, can be accurately positioned in the center of the hole (10a) when inserted into the hole (10a) It is preferable in that it exists.

그 다음, 윗면용 오버레이층(30)을 상기 코어 보드(10)와 베이스 필름(21)을 커버하게 상기 코어 보드(10) 상에 적층시킨 다음 상기 적층된 것들을 도 3에 도시된 바와 같은 형상으로 열압착시킨다.Then, the upper overlay layer 30 is laminated on the core board 10 so as to cover the core board 10 and the base film 21, and the stacked ones are formed in the shape as shown in FIG. Thermocompress.

상기 열압착은 도 4에 도시된 표와 같은 조건에서 행하는 것이 바람직하다.The thermocompression bonding is preferably carried out under the conditions shown in the table shown in FIG. 4.

즉, 온도에 있어서, 8~15분에 걸쳐 140~180℃까지 서서히 승온시키고, 그 다음 14~24분 동안 150~170℃를 유지하고, 그 다음 18~24분에 걸쳐서 상온(바람직하게는 18~25℃)까지 서서히 냉각시키며, 그리고 압력에 있어서, 1~2분 동안 압력을 주지 않고, 그 다음 26~30분 동안 40~70bar로 압착하고, 그 다음 15~25분 동안 80~150bar로 압착한 후 압력을 해제하는 것이 바람직하다.That is, in temperature, the temperature is gradually raised to 140 to 180 ° C. over 8 to 15 minutes, then 150 to 170 ° C. for 14 to 24 minutes, and then at room temperature (preferably 18 to 24 minutes). To 25 ° C.), and at pressure, without pressure for 1 to 2 minutes, then to 40 to 70 bar for 26 to 30 minutes, then to 80 to 150 bar for 15 to 25 minutes It is then desirable to release the pressure.

그 이유는 도 3에 도시된 바와 같이, 0.06mm 두께의 밑면용 오버레이층(50), 0.38mm 두께의 코어 보드(10), 0.3mm 두께의 아이씨 칩(22)에 의해 구획형성된 빈공간(S)을 채우면서 코어 보드(10)의 구멍(10a) 측 테두리부(10b)가 0.07mm 깊이로 아래쪽으로 함몰되면서 베이스 필름(21)의 테두리부(21a)가 상기 함몰된 부분에 안착되고, 그리고 윗면용 오버레이층(30)이 위쪽으로 0.03 깊이로 함몰되면서 그 함몰된 부분에 상기 베이스 필름(21)의 일부가 삽입되게 되어, 종래보다 얇고 굽힘에 대한 저항성이 높아져 카드의 강도가 증대된다. The reason for this is as shown in FIG. 3, the void space S partitioned by the overlay layer 50 for the bottom surface having a thickness of 0.06 mm, the core board 10 having a thickness of 0.38 mm, and the IC chip 22 having a thickness of 0.3 mm. ) While the edge portion 10b of the hole 10a side of the core board 10 is recessed downward to a depth of 0.07 mm, and the edge portion 21a of the base film 21 is seated in the recessed portion. As the upper overlay layer 30 is recessed to a depth of 0.03 upward, a portion of the base film 21 is inserted into the recessed portion, which is thinner than the conventional one and increases resistance to bending, thereby increasing the strength of the card.

도 1은 안테나 코일과 집적회로 칩을 구비한 카드의 단면도 및 평면도,1 is a cross-sectional view and a plan view of a card having an antenna coil and an integrated circuit chip;

도 2는 본 실시예의 단면도,2 is a cross-sectional view of this embodiment,

도 3은 도 2의 카드의 최종 상태를 도시하는 설명도,3 is an explanatory diagram showing a final state of the card of FIG. 2;

도 4는 열압착공정시의 히팅과 압력 조건에 대한 그래프.Figure 4 is a graph of the heating and pressure conditions during the thermocompression bonding process.

Claims (3)

테이블 상에 밑면용 오버레이층을 깔아 놓은 상태에서, 집적회로 칩을 삽입할 구멍이 펀치가공에 의해 형성된 코어 보드를 상기 밑면용 오버레이층 상에 적층시키는 단계;Stacking a core board formed by punching a hole for inserting an integrated circuit chip on the bottom overlay layer while laying the bottom overlay layer on the table; 상기 코어 보드 상에 안테나 코일을 일정 패턴으로 배설하되, 상기 안테나 코일의 양 단자가 상기 집적회로 칩용 구멍을 구획형성하고 있는 상기 집적회로 칩용 구멍 측의 테두리부에 위치되게 하는 단계;Disposing an antenna coil on the core board in a predetermined pattern, such that both terminals of the antenna coil are positioned at an edge portion of the hole side for the integrated circuit chip which defines the hole for the integrated circuit chip; 상기 양 단자에 도전성 접착제를 도포하는 단계;Applying a conductive adhesive to both terminals; 상기 테두리부에 입출력 단자가 구비된 베이스 필름 상에 부착되어 돌출되어 있는 상기 집적회로 칩이 상기 집적회로 칩용 구멍을 통하여 삽입되어, 상기 집적회로 칩의 선단이 상기 밑면용 오버레이층과 면하고 있는 상태에서, 상기 베이스 필름의 테두리부가 상기 집적회로 칩용 구멍 측의 상기 테두리부에 걸치게 하여, 상기 입출력 단자에 도포된 상기 도전성 접착제와 접촉되게 하는 단계; 및The integrated circuit chip, which is attached to the base film having an input / output terminal and protrudes from the edge portion, is inserted through the hole for the integrated circuit chip, and the front end of the integrated circuit chip faces the overlay layer for the bottom surface. In which the edge portion of the base film extends over the edge portion of the hole side for the integrated circuit chip so as to be in contact with the conductive adhesive applied to the input / output terminal; And 상기 코어 보드와 상기 베이스 필름을 커버하게, 상기 코어 보드 상에 윗면용 오버레이층을 적층시킨 다음 상기 적층된 것들을 열압착시키는 단계를 포함하는 것을 특징으로 하는 안테나 코일과 집적회로 칩을 구비한 카드에 칩을 인레이하는 방법.Stacking an overlay layer for top surface on the core board to cover the core board and the base film, and then thermally compressing the stacked ones to a card having an antenna coil and an integrated circuit chip. How to inlay chips. 제 1항에 있어서,The method of claim 1, 상기 집적회로 칩은, 그 하단 모서리부가 모따기 처리되어 있는 것을 특징으로 하는 안테나 코일과 집적회로 칩을 구비한 카드에 칩을 인레이하는 방법.The integrated circuit chip is a method of inlaying a chip on a card having an antenna coil and integrated circuit chip, characterized in that the lower edge portion is chamfered. 제 1항에 있어서,The method of claim 1, 상기 열압착은, The thermal compression is, 온도에 있어서, 8~15분에 걸쳐 140~180℃까지 서서히 승온시키고, In temperature, it is heated up gradually to 140-180 degreeC over 8-15 minutes, 그 다음 14~24분 동안 150~170℃를 유지하고, Then hold 150-170 ° C. for 14-24 minutes, 그 다음 18~24분에 걸쳐서 18~25℃)까지 서서히 냉각시키며, 그리고 Then slowly cool to 18-25 ° C. over 18-24 minutes, and 압력에 있어서, 1~2분 동안 압력을 주지 않고, In pressure, without pressure for 1-2 minutes, 그 다음 26~30분 동안 40~70bar로 압착하고, Then squeeze at 40-70 bar for 26-30 minutes, 그 다음 15~25분 동안 80~150bar로 압착한 후 압력을 해제하는 것을 특징으로 하는 안테나 코일과 집적회로 칩을 구비한 카드에 칩을 인레이하는 방법.And then releasing the pressure after squeezing at 80 to 150 bar for 15 to 25 minutes to release the pressure.
KR1020080041293A 2008-05-02 2008-05-02 method for inlaying chip in a card which is provided with antenna coil and IC chip KR101006870B1 (en)

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