KR20090110488A - Method for fabricating semiconductor device - Google Patents

Abstract

PURPOSE: A method for fabricating a semiconductor device is provided to realize a transistor in which a single channel effect is improved in a peripheral circuit area without influencing a contact forming process of a cell area. CONSTITUTION: A method for fabricating a semiconductor device comprises the following steps. A gate(25) is formed on a substrate(21). The first gate spacer(26) is formed in both sides of the gate. Protruded source and drain areas(27A) are formed on a substrate exposed to both side walls of the first gate spacer. The second gate spacer is formed on the exposed side wall of the first gate spacer. Impurity is doped in the protruded source and drain areas.

Description

Manufacturing method of semiconductor device {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having an elevated source / drain (ESD) structure.

As the degree of integration of semiconductor devices increases, the gate length of a metal oxide semiconductor field effect transistor (MOSFET) is also getting shorter. As a result, there is a problem in that a short channel effect such as a reduction of a threshold voltage and a drain induced barrier lowering (DIBL) occurs. This short channel effect can be solved by shallowly forming the source and drain junctions.

However, if the source and drain junctions are formed to be shallow, the resistance of the source and drain regions is increased. If the doping is carried out at a high concentration to reduce the resistance of the source and drain regions, it is difficult to form a shallow junction. trade off) relationship.

Recently, the so-called Elevated Source / Drain (ESD) which elevate the source and drain regions by forming a source and drain region having a shallow junction and lowering the resistance of the source and drain regions. A structure has been proposed. The elevated source / drain structure is a method of forming an elevated source and drain region by selectively forming an epitaxial layer only in a predetermined region of the source and drain region using Selective Epitaxial Growth (SEG). The application of an elevated source / drain structure to a semiconductor device has the advantage of reducing the resistance of the source and drain regions and forming a shallow junction through high concentration doping of the raised source and drain regions.

When the elevation source / drain structure is applied to a semiconductor memory device such as a DRAM (Dynamic Random Access Memory), the contact resistance of the cell region can be lowered and a contact margin can be secured. Further, in the peripheral circuit region, the short channel effect can be effectively prevented while reducing the gate length. Typically, the epitaxial layer for the elevation source / drain structure proceeds after forming the gate spacer, which is formed simultaneously in the cell region and the peripheral circuit region for process simplicity. At this time, the transistor in the cell region requires a thin gate spacer to secure contact margins, and the transistor in the peripheral circuit region has a relatively thick gate spacer compared to the gate spacer in the cell region to prevent short channel effects. Required. That is, a trade off relationship is established between the gate spacer thickness of the cell region and the gate spacer thickness of the peripheral circuit region.

1A and 1B are cross-sectional views illustrating a semiconductor device having an elevation source / drain according to the prior art, and FIG. 1A is a cross-sectional view illustrating a case where a gate spacer required by a transistor in a cell region is formed on a front surface thereof. 1b is a cross-sectional view showing the case where the gate spacer required by the transistors in the peripheral circuit region is formed on the entire surface.

As shown in FIGS. 1A and 1B, a semiconductor device having an elevation source / drain structure according to the related art includes a substrate 11 having a cell region and a peripheral circuit region, and a gate 12 formed on the substrate 11. ), Gate spacers 13A and 13B formed on both side walls of the gate 12, and raised source and drain regions 14.

As shown in FIG. 1A, when the gate spacer 13A having the thickness t1 required by the transistor in the cell region is formed on both sidewalls of the gate 12 of the cell region and the peripheral circuit region, the gate ( It is possible to secure an etching margin for subsequent contact formation by securing a gap (S1) between 12). However, in the peripheral circuit region, the short channel effect occurs because the gate length L1 required by the transistor cannot be secured. This causes a problem that the transistor characteristics of the peripheral circuit area deteriorate.

On the other hand, as shown in FIG. 1B, when the gate spacer 13B having the thickness t2 required by the transistors in the peripheral circuit region is formed on both side walls of the gate 12 of the cell region and the peripheral circuit region, the peripheral portion of the gate spacer 13B is formed. It is possible to secure the gate length L2 required by the transistor in the circuit area to prevent the short channel effect from occurring. However, in the cell region, the gate spacer 13B fills the gaps between the gates 12 so that the gap S2 between the gates 12 becomes narrow. As a result, a problem arises in that an etching margin cannot be secured during subsequent contact formation.

In order to solve this problem, when the epitaxial layers for the gate spacers 13A and 13B and the raised source and drain regions 14 are formed in the cell region and the peripheral circuit region, the process time and the step are increased. There is a problem that the manufacturing yield (yield) of the semiconductor device is lowered. In addition, there is a problem that the characteristics of the semiconductor device deteriorate due to the thermal burden generated in the process of forming the epitaxial layer a plurality of times.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and provides a method of manufacturing a semiconductor device capable of simultaneously forming a raised source and drain region in a cell region and a peripheral circuit region.

Another object of the present invention is to provide a method of manufacturing a semiconductor device having a gate spacer having a thickness required by a transistor in a cell region and a transistor in a peripheral circuit region.

In addition, another object of the present invention to provide a method for manufacturing a semiconductor device that can increase the gate length in the semiconductor device having an elevated source / drain structure without additional processing.

According to one aspect of the present invention, a method of manufacturing a semiconductor device includes: forming a gate on a substrate; Forming a first gate spacer on both sidewalls of the gate; Forming an elevated source and drain region on the substrate exposed to both sides of the first gate spacer; Forming a second gate spacer on the exposed sidewalls of the first gate spacer and doping impurities in the raised source and drain regions. The method may further include cleaning the surface of the substrate exposed to both sides of the gate before forming the raised source and drain regions. The method may further include a heat treatment step for activating the doped impurities after doping the doped source and drain regions with impurities.

The raised source and drain regions may be formed as an epitaxial layer through epitaxial growth. The epitaxial layer may be formed of any one selected from the group consisting of an epitaxial silicon layer, an epitaxial silicon germanium layer, an epitaxial silicon carbon layer, and an epitaxial silicon germanium carbon layer or a laminated film in which they are laminated.

The first gate spacer may include a nitride film, and the second gate spacer may include an oxide film.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including: forming a gate on each region of a substrate having a cell region and a peripheral circuit region; Forming a first gate spacer on both sidewalls of the gate; Forming an elevated source and drain region on the substrate exposed to both sides of the first gate spacer; And forming a second gate spacer on exposed sidewalls of the first gate spacer of the peripheral circuit region and doping impurities in the raised source and drain regions. The method may further include cleaning the surface of the substrate exposed to both sides of the gate before forming the raised source and drain regions. The method may further include a heat treatment step for activating the doped impurities after doping the doped source and drain regions with impurities.

The raised source and drain regions may be formed as an epitaxial layer through epitaxial growth. The epitaxial layer may be formed of any one selected from the group consisting of an epitaxial silicon layer, an epitaxial silicon germanium layer, an epitaxial silicon carbon layer, and an epitaxial silicon germanium carbon layer or a laminated film in which they are laminated.

The first gate spacer may include a nitride film, and the second gate spacer may include an oxide film.

The forming of the second gate spacer may include forming an insulating film for a spacer on the entire surface of the substrate; Forming a first photoresist film covering the cell region and opening the peripheral circuit region; and forming a second gate spacer on the exposed sidewall of the first gate spacer of the peripheral circuit region through a front surface etching process. It may include.

Doping impurities in the raised source and drain regions may include forming a first photoresist film covering the cell region and opening the peripheral circuit region to an elevated source and drain region of the peripheral circuit region with an ion implantation barrier. Doping the impurity; Removing the first photoresist film; Doping a second photoresist film covering the peripheral circuit region and opening the cell region with an ion implantation barrier in the raised source and drain regions of the cell region and removing the second photoresist layer. It may include.

The first impurity and the second impurity may be N-type impurities, the first impurity may be a P-type impurity, and the second impurity may be an N-type impurity.

The present invention based on the above-described problem solving means has an effect that can implement a transistor with improved short channel effect in the peripheral circuit region, without affecting the contact forming process of the cell region.

In addition, according to the present invention, the epitaxial layer of the cell region and the epitaxial layer of the peripheral circuit region can be formed at the same time, thereby reducing the process time and the process step. In addition, it is possible to reduce the thermal burden generated during the epitaxial layer forming process.

In addition, the present invention can provide a semiconductor device having a gate spacer having a thickness required by a transistor in a cell region and a transistor in a peripheral circuit region. Through this, it is possible to secure a contact margin in the cell region and to prevent a short channel effect due to a decrease in the gate length of the peripheral circuit region.

In addition, the present invention can increase the gate length of a semiconductor device having an elevated source / drain structure without additional processing. Through this, the short channel effect can be prevented more effectively.

Thus, the present invention has the effect of improving the reliability and manufacturing yield (yield) of the semiconductor device.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device having an elevated source / drain (ESD) structure in order to improve a short channel effect (SCE) due to high integration of a semiconductor device. The technical principle is to simultaneously form an epitaxial layer for the elevated source and drain regions of the cell region and the peripheral circuit region while providing the gate spacer thickness required by the transistors in the and peripheral circuit regions.

2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

As shown in FIG. 2A, a gate 25 is formed on each region of the substrate 21 having a cell region and a peripheral circuit region. At this time, the cell region is a region where the spacing between patterns is narrow, and the peripheral circuit region is a region where the spacing between patterns is relatively wider than the cell region. Although not shown in the drawing, an element isolation film for inter-element separation is formed before the gate 25 is formed.

The substrate 21 may use a Si substrate.

The gate 25 may be formed to have a structure in which the gate insulating film 22, the gate electrode 23, and the gate hard mask film 24 are sequentially stacked. The gate insulating film 22 may be formed of an oxide film, for example, silicon oxide film (SiO ₂ ), and the silicon oxide film may be formed by thermal oxidation. The gate electrode 23 may be formed of any one selected from the group consisting of a polysilicon film, a metal film, a conductive metal nitride film, a conductive metal oxide film, and a metal silicide film or a laminated film in which these are stacked. Tungsten (W), iron (Fe), tantalum (Ta), or titanium (Ti) may be used as the metal film. A titanium nitride film (TiN) or a tantalum nitride film (TaN) may be used as the conductive metal nitride film. An iridium oxide film (IrO ₂ ) can be used as the conductive metal oxide film. As the metal silicide film, a titanium silicide film (TiSi) or a tungsten silicide film (WSi) may be used. The gate hard mask film 24 may be formed of any one selected from the group consisting of an oxide film, a nitride film, an oxynitride, and an amorphous carbon layer, or a laminated film in which these layers are stacked. Oxides include silicon oxide (SiO ₂ ), BPSG (Boron Phosphorus Silicate Glass), PSG (Phosphorus Silicate Glass), TEOS (Tetra Ethyle Ortho Silicate), USG (Un-doped Silicate Glass), High Density Plasma, HDP), Spin On Glass (SOG), or Spin On Dielectric (SOD) may be used. As the nitride film, a silicon nitride film (Si ₃ N ₄ ) may be used. As the oxynitride film, a silicon oxynitride film (SiON) can be used.

Next, an insulating film (not shown) for spacers is formed on the entire surface of the substrate 21 including the gate 25, and then an entire surface etching process, for example, an etch back is performed to remove the spacer 25 from both sides of the gate 25. One gate spacer 26 is formed. In this case, the thickness t1 of the first gate spacer 26 may be formed to have a thickness required by the transistor in the cell region.

In addition, the first gate spacer 26 may be formed of any one selected from the group consisting of an oxide film, a nitride film, and an oxynitride. Preferably, the first gate spacer 26 is formed of a nitride film. The thickness t1 of the first gate spacer 26 formed on both sidewalls of the gate 25 of the cell region and the thickness t2 of the first gate spacer 26 formed on both sidewalls of the gate 25 of the peripheral circuit region. Are identical to each other (t1 = t2).

Here, the surface of the substrate 21 exposed by controlling process conditions such as bias power and etching gas during the front side etching process in order to facilitate the epitaxial layer forming process for the subsequent raised source and drain regions. It is desirable to prevent damage as much as possible. Therefore, it is preferable to control the front surface etching process so that the thickness of the substrate 21 lost during the front surface etching process is 100 kPa or less (for example, 1 kPa to 100 kPa).

Through the above-described process, it is possible to secure the thickness of the gate spacer required by the transistor in the cell region.

Meanwhile, an etch by product may occur in the process of forming the first gate spacer 26. If an etch by-product remains on the exposed surface of the substrate 21, in particular, on the surface of the substrate 21 in a predetermined region of the raised source and drain regions, defects in the epitaxial layer during subsequent epitaxial growth due to the etch by-products ) May occur or the adhesion between the epitaxial layer and the substrate 21 may be lowered, so that the epitaxial layer may not grow properly.

 In addition, during the entire surface etching process for forming the first gate spacer 26, the surface of the substrate 21 in the predetermined region of the raised source and drain regions may be damaged, thereby causing defects on the surface of the substrate 21. This can happen. Defects formed on the surface of the substrate 21 may extend into the epitaxial layer during subsequent epitaxial layer growth, thereby degrading the film quality of the epitaxial layer.

Therefore, in order to remove the etching by-products remaining on the surface of the substrate 21 in the predetermined region of the raised source and drain region and to cure the defects formed on the surface of the substrate 21, as shown in FIG. Carry out a cleaning treatment. The cleaning process may be performed by wet cleaning or dry cleaning alone, or by a combination of wet and dry cleaning.

For example, dry cleaning may be performed using a gas containing fluorine (F), for example, CF ₄ gas, and wet cleaning may be a mixed solution of sulfuric acid (H ₂ SO ₄ ) and hydrogen peroxide (H ₂ O ₂ ). Alternatively, BOE (Buffered Oxide Echant, a mixed solution of NH ₄ F and HF) may be used.

In addition, it is preferable to use a gas or a solution having a good selectivity for the cleaning treatment so as to minimize the loss of the first gate spacer 26. In addition, the washing treatment is preferably carried out in a low temperature range of room temperature to 600 ℃. The cleaning process may also proceed in-situ in subsequent epitaxial layer forming equipment.

As such, by removing the residues such as the natural oxide film and the etching by-products remaining on the surface of the substrate 21 in the predetermined region of the source and drain regions through the cleaning treatment, the surface of the substrate 21 is cured, Subsequent processes can prevent the occurrence of defects in the epitaxial layer to be formed.

As shown in FIG. 2C, an epitaxial layer 27 is formed on both sides of the gate 25 of the cell region and the peripheral circuit region, specifically, on the substrate 21 having surfaces exposed on both sides of the first gate spacer 26. ). Here, the epitaxial layer 27 acts as an elevated source and drain region through a subsequent process.

The epitaxial layer 27 may be formed using epitaxial growth, for example, selective epitaxial growth (SEG) or solid phase epitaxial growth (SPE).

In addition, the epitaxial layer 27 may include low pressure CVD (LPCVD), very low pressure CVD (VLPCVD), plasma enhanced-CVD (PE-CVD), ultrahigh vacuum CVD (UHVCVD), rapid thermal CVD (RTCVD), and APCVD (APCVD). It can be formed using any one device selected from the group consisting of Atmosphere Pressure CVD) and Molecular Beam Epitaxy (MBE).

In addition, the epitaxial layer 27 may be formed at a temperature in the range of 400 ° C to 800 ° C, and may be formed to have a thickness in the range of 400 ° C to 1200 ° C.

In addition, the epitaxial layer 27 includes an epitaxial silicon layer, and the epitaxial silicon layer contains either germanium (Ge) or carbon, or all of them. It can be formed with a tactile silicon layer. For example, the epitaxial layer 27 may include an epitaxial silicon layer, an epitaxial silicon germanium layer, an epitaxial silicon carbon layer, and an epitaxial silicon germanium layer. Epitaxial SiGeC layer) may be formed of a single film composed of any one selected from the group consisting of a group or a laminated film in which they are laminated.

In addition, the epitaxial layer 27 may be formed of a doped epitaxial layer 27 doped with an impurity or an undoped epitaxial layer 27 not doped with an impurity. In this case, the doped epitaxial layer 27 may be formed by forming an epitaxial layer 27 and implanting impurities in-situ. As an impurity, a P-type impurity such as boron (B) or an N-type impurity such as phosphorus (P) or arsenic (As) may be used, and the type of the impurity is determined according to the electrical characteristics of the semiconductor device.

As shown in FIG. 2D, an insulating film 29 for spacers is formed on the entire surface of the substrate 21. The spacer insulating layer 29 is formed on both sidewalls of the gate 25 of the peripheral circuit region, specifically, to form the second gate spacer 29A on the exposed sidewall of the first gate spacer 26. It is preferable to form the gate spacer having the thickness required.

In addition, the spacer insulating film 29 is preferably formed by using a low temperature deposition method such as low pressure CVD (LPCVD) or plasma enhanced-CVD (PECVD) to reduce the thermal burden on the semiconductor device. The spacer insulating film 29 may be formed of any one selected from the group consisting of an oxide film, a nitride film, and an oxynitride film. Preferably, the spacer insulating layer 29 is formed of a material having an etching selectivity with the first gate spacer 26, for example, a nitride film. Therefore, the insulating film 29 for spacers is preferably formed of an oxide film, and more preferably formed of BPSG (Boron Phosphorus Silicate Glass) or TEOS (Tetra Ethyle Ortho Silicate), which can be formed using a low temperature deposition method. Do.

Next, a first passivation layer 28 is formed to cover the cell region and to open the peripheral circuit region. In this case, the first passivation layer 28 may be formed of photoresist (PR).

On the other hand, after forming the first protective film 28, the insulating film 29 for spacers may be formed. However, since the scum may occur in the cell region where the gap between the patterns is narrow during the process of removing the first passivation layer 28 formed of the subsequent photoresist, the first passivation layer 28 may be formed before the spacer insulating layer 29. It is not desirable to form.

Next, the entire surface of the gate 25 of the peripheral circuit region may be etched, for example, by etching the entire surface of the first protective layer 28 using an etch barrier. The second gate spacer 29A is formed on the sidewalls. Here, the gate spacer thickness t3 of the peripheral circuit region transistor is a sum of the thickness t1 of the first gate spacer 36 and the thickness t2 of the second gate spacer 29A (t3 = t1 + t2).

Through the above-described process, the thickness of the gate spacer required by the transistor in the peripheral circuit region can be secured.

As shown in FIG. 2E, impurities are deposited on the epitaxial layer 27 of the peripheral circuit region using the first passivation layer 28, the gate 25, and the second gate spacer 29A as an ion implantation barrier. Ion implantation (hereinafter abbreviated as primary ion implantation). When the transistor in the peripheral circuit region is NMOS during primary ion implantation, N-type impurities such as phosphorus (P) and arsenic (As) can be ion-implanted, and in the case of PMOS, P-type impurities such as boron (B) Ion implantation is possible. In addition, the doping concentration may be 1 × 10 ¹⁷ to 1 × 10 ²¹ atoms / cm ³ during primary ion implantation.

Here, in the epitaxial layer 27 of the peripheral circuit region, the second gate spacer 29A covers the gate 25 and the upper portion of the adjacent epitaxial layer 27. As a result, impurities implanted into the epitaxial layer 27 in the peripheral circuit region are spaced apart from the side walls of the gate 25 by the thickness t2 of the second gate spacer 29A.

Meanwhile, as mentioned in FIG. 2C, the epitaxial layer 27 may be a doped epitaxial layer 27 doped with impurities. For example, when the transistor of the peripheral circuit region is to be formed of PMOS, the epitaxial layer 27 is a doped epitaxial layer 27 doped with P-type impurities, and the doping concentration is required by the semiconductor device, for example, 1 In the case of having a doping concentration in the range of x10 ¹⁷ to 1x10 ²¹ atoms / cm ³ , the above-described primary ion implantation process may be omitted.

On the other hand, when the transistor in the peripheral circuit region is to be formed of PMOS, if the epitaxial layer 27 is a doped epitaxial layer 27 doped with N-type impurities, the epitaxial layer is subjected to counter doping during primary ion implantation. The conductivity type of the tactile layer 27 can be converted from N type to P type.

Next, the first protective film 28 is removed. In this case, the first passivation layer 28 may be removed using a strip process.

Next, the spacer insulating film 29 covering the cell region and the second gate spacer 29A formed on both side walls of the gate 25 of the peripheral circuit region are removed. The spacer insulating layer 29 and the second gate spacer 29A may be removed using a dry etch or a wet etch alone, or a combination of these methods. For example, when the insulating film 29 for spacers and the second gate spacer 29A are formed of an oxide film, a dry etching method may be used to remove the gas plasma containing fluorine (F), and the hydrofluoric acid method is hydrofluoric acid. Can be removed using (HF) solution. As the gas containing fluorine, CF ₄ gas or CHF ₃ gas may be used.

On the other hand, removing the second gate spacer 29A after ion implantation of impurities into the epitaxial layer 27 in the peripheral circuit region has no effect on the electrical characteristics of the semiconductor device.

As shown in FIG. 2F, the cell region is opened and a second passivation layer 30 covering the peripheral circuit region is formed. The second passivation layer 30 may be formed using the same material as the first passivation layer 28. That is, the second passivation layer 30 may be formed of photoresist PR.

Next, impurities are implanted into the epitaxial layer 27 of the cell region using the second passivation layer 30, the gate 25 and the first gate spacer 26 (hereinafter, abbreviated as secondary ion implantation). do). In the case of the secondary ion implantation, when the transistor in the cell region is NMOS, N-type impurities such as phosphorus (P) and arsenic (As) can be ion implanted. In the case of PMOS, P-type impurities such as boron (B) are ionized. Can be injected. In addition, the doping concentration may be 1 × 10 ¹⁷ to 1 × 10 ²¹ atoms / cm ³ at the time of secondary ion implantation.

Meanwhile, as mentioned in FIG. 2C, the epitaxial layer 27 may be a doped epitaxial layer 27 doped with impurities. For example, when the transistor in the cell region is to be formed of NMOS, the epitaxial layer 27 is a doped epitaxial layer 27 doped with N-type impurities, and the doping concentration is required by the semiconductor device, for example, 1 ×. When the doping concentration is in the range of 10 ¹⁷ to 1 × 10 ²¹ atoms / cm ³ , the above-described secondary ion implantation process may be omitted.

On the other hand, if the epitaxial layer 27 is a doped epitaxial layer 27 doped with P-type impurities when the transistor of the cell region is to be formed of NMOS, the epitaxial layer is subjected to counter doping during secondary ion implantation. The conductivity type of the shir layer 27 can be converted from P type to N type.

As shown in FIG. 2G, heat treatment is performed to activate impurities implanted into the epitaxial layer 27 during the primary ion implantation process and the secondary ion implantation process. The heat treatment can be carried out using a furnace heat treatment or rapid heat treatment method. As a result, some of the impurities implanted into the epitaxial layer 27 of the cell region and the peripheral circuit region diffuse into the substrate 21 to form a raised source and drain region 27A having a shallow junction. have.

Here, in the raised source and drain regions 27A of the peripheral circuit region, the impurity implanted into the epitaxial layer 27 due to the second gate spacer 29A has the thickness of the second gate spacer from both side walls of the gate 25. Spaced apart. As a result, when impurities are diffused during the heat treatment, the diffusion is hardly diffused into the substrate 21 adjacent to the gate 25 due to the distance difference. As a result, the transistors in the peripheral circuit region may have a gate length that is longer than a predetermined gate length. In detail, the predetermined gate length L1 may be defined as the sum of the length of the gate 25 and the thickness of the first gate spacer 26 formed on both sidewalls of the gate 25. In contrast, the extended gate length L2 of the present invention may be defined as the sum of the length of the gate 25, the thickness of the first gate spacer 26, and the thickness of the second gate spacer 29A. This may increase the gate length of a semiconductor device having an elevated source / drain structure without any additional process.

Through the above-described process, a semiconductor device having an elevated source / drain structure may be completed.

As described above, according to the present invention, the epitaxial layer 27 serving as the source and drain regions 27A is simultaneously formed in the cell region and the peripheral circuit region, thereby applying the semiconductor element in the process of forming the epitaxial layer 27. It can reduce the thermal burden. In addition, the manufacturing time of the semiconductor device may be improved by shortening the process time and the process step.

In addition, the present invention can provide a semiconductor device having the thickness of the gate spacer required by the transistors in the cell region and the peripheral circuit region by separately forming the first gate spacer 26 and the second gate spacer 29A. have. Through this, the contact margin of the cell region can be secured and the short channel effect due to the reduction of the gate length of the peripheral circuit region can be prevented.

In addition, the present invention may form the second gate spacer 29A after the epitaxial layer 27 is formed, thereby increasing the gate length of the semiconductor device having an elevated source / drain structure without any additional process. have. Through this, the short channel effect can be prevented more effectively.

In summary, the present invention can improve the stability and manufacturing yield of semiconductor devices having an elevated source / drain structure.

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will appreciate that various embodiments within the scope of the technical idea of the present invention are possible.

1A and 1B are cross-sectional views illustrating semiconductor devices having an elevated source / drain according to the prior art.

2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

* Description of symbols on the main parts of the drawings *

21 substrate 22 gate insulating film

23 gate electrode 24 gate hard mask film

25 gate 26 first gate spacer

27: epitaxial layer 27A: raised source and drain regions

28: first protective film 29: insulating film for spacer

29A: second gate spacer 30: second protective film

Claims (13)

Forming a gate on the substrate; Forming a first gate spacer on both sidewalls of the gate; Forming an elevated source and drain region on the substrate exposed to both sides of the first gate spacer; Forming a second gate spacer on the exposed sidewall of the first gate spacer; And Doping impurities in the raised source and drain regions Method of manufacturing a semiconductor device comprising a. Forming a gate on each region of the substrate having a cell region and a peripheral circuit region; Forming a first gate spacer on both sidewalls of the gate; Forming an elevated source and drain region on the substrate exposed to both sides of the first gate spacer; Forming a second gate spacer on an exposed sidewall of the first gate spacer of the peripheral circuit region; And Doping impurities in the raised source and drain regions Method of manufacturing a semiconductor device comprising a. The method according to claim 1 or 2, And the raised source and drain regions are formed as an epitaxial layer through epitaxial growth. The method of claim 3, The epitaxial layer is any one selected from the group consisting of an epitaxial silicon layer, an epitaxial silicon germanium layer, an epitaxial silicon carbon layer and an epitaxial silicon germanium layer, or a semiconductor device manufacturing method of forming a laminated film of these . The method according to claim 1 or 2, And cleaning the surface of the substrate exposed to both sides of the gate prior to forming the raised source and drain regions. The method according to claim 1 or 2, And a heat treatment step for activating the doped impurities after doping the doped source and drain regions with impurities. The method according to claim 1 or 2, The first gate spacer includes a nitride film. The method according to claim 1 or 2, And the second gate spacer comprises an oxide film. The method according to claim 1 or 2, The first gate spacer includes a nitride film and the second gate spacer comprises an oxide film. The method of claim 2, Forming the second gate spacer, Forming an insulating film for a spacer on the entire surface of the substrate; Forming a first photoresist film covering the cell region and opening the peripheral circuit region; And Forming a second gate spacer on an exposed sidewall of the first gate spacer of the peripheral circuit region through an entire surface etching process; Method of manufacturing a semiconductor device comprising a. The method of claim 2, Doping impurities in the raised source and drain regions, Doping a first photoresist film covering the cell region and opening the peripheral circuit region to an elevated source and drain region of the peripheral circuit region with an ion implantation barrier; Removing the first photoresist film; Doping a second photoresist film covering the peripheral circuit region and opening the cell region with an ion implantation barrier in the raised source and drain regions of the cell region; And Removing the second photoresist film Method of manufacturing a semiconductor device comprising a. The method of claim 11, Wherein the first impurity and the second impurity are N-type impurities. The method of claim 11, Wherein the first impurity is a P-type impurity, and the second impurity is an N-type impurity.

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