KR20090108374A - Control circuit for semiconductor memory device - Google Patents

Abstract

PURPOSE: A control circuit for semiconductor memory device is provided to reduce the size of the switch for the short. CONSTITUTION: The control circuit of the semiconductor memory device includes a comparison unit, an amplification, and a feedback and a short. The comparison compares the reference voltage with the feedback voltage. The amplification is generated the peri voltage as much as the difference of the comparison unit. The feedback supplies as the comparison unit by feedback of the peri voltage generated in the amplification means. The comparison unit shorts the reference voltage from the external power voltage as the burn in test signal is in the enable state. The short inverts the burn in test signal to provide it to the PMOS transistor.

Description

CONTROL CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICE}

The present invention relates to a control circuit of a semiconductor memory device, and more particularly, to a control circuit of a semiconductor memory device for controlling a short between a reference voltage of an internal power supply voltage and an external power supply voltage during a burn-in test.

Semiconductor memory devices use various types of internal voltages by using externally supplied power voltages. In particular, in the case of a semiconductor memory device (DRAM), a voltage of VCORE which is a voltage used in a core region of the memory device, a VPP voltage which is higher than an external potential VDD applied to a cell transistor gate (word line), and a cell The negative voltage VBB, which is lower than the ground voltage VSS used for the bulk of the transistor, is used.

Charge pumping (VBB, VPP) and down converting (VCORE) are used to make these internal voltages. After the reference voltage (VREF) is made, using this method to create a second internal voltage (VBB, VPP, VCORE) again.

1 illustrates a circuit for generating reference voltages of internal power supplies used for various purposes in a general semiconductor memory device.

That is, as shown, the reference voltages of the internal power supplies used for various purposes in the semiconductor memory device are generated by the reference voltage generator 10 (REF_GEN) and the trimming circuit 20 (Trimming Block). The reference voltage VR0 generated from the reference voltage generator 10 is supplied to the trimming circuit 20. The trimming circuit 20 divides the voltage into appropriate sizes to generate reference voltages VREF1 to VREF3 suitable for each purpose.

Similarly, the internal power supply voltage VPERI used in the burn-in device is also generated using one of the reference voltages VREF1 to VREF3 generated by the reference voltage generator. Hereinafter, the reference voltage for generating the internal power supply voltage VPERI is described as VREFD.

2 is a configuration diagram of a circuit for generating an internal power supply voltage VPERI used in a conventional burn-in apparatus.

As shown, the internal power supply voltage VPERI generation circuit comprises NMOS transistors N1 and N2 for differential comparison between a reference voltage VREFD and a feedback voltage formed by distributing the generated power supply voltage VPERI. A comparator comprising a PMOS transistor P3 for generating and outputting an amplified internal power supply voltage VPERI in response to an output signal of the comparator; And a feedback voltage generator for generating voltage feedback by R6), generating a feedback voltage for monitoring the output of the internal power supply voltage, and providing the feedback voltage to the NMOS transistor N2. A control switching unit composed of an NMOS transistor N3 for controlling the operation of the comparator, and a current mirror composed of PMOS transistors P1 and P2 are included.

The conventional internal power supply voltage VPERI circuit configured as described above supplies a bias voltage to the gate terminal of the NMOS transistor N3 constituting the control switching unit so that the operating point of the comparison unit is determined by the control switching unit. It is controlled.

When the bias voltage is applied to the NMOS transistor N3 and is turned on, the NMOS transistor N1 is turned on by the external reference voltage VREFD, so that the transistor N1 and the transistor N3 are turned on. ), The drain voltage is lowered. Accordingly, a low level signal is applied to the gate terminal of the PMOS transistor P3 operated by the voltage applied to the drain terminal of the transistor N1, and the internal power voltage VPERI output while the transistor P3 is turned on. ) Increases.

When the internal power supply voltage VPERI is raised, the feedback voltage is also raised while turning on the transistor N2. When the transistor N2 is turned on, the gate terminal voltages of the PMOS transistors P1 and P2 are lowered. When the gate terminal voltages of the PMOS transistors P1 and P2 are lowered, the potential of the drain terminal of the NMOS transistor N1 is gradually increased while being turned on. In other words, the gate voltage of the transistor P3 is gradually raised. This operation is performed until the feedback voltage and the reference voltage VREFD are equal.

That is, the conventional internal power supply voltage generation circuit inputs a reference voltage VREFD for generating the internal power supply voltage VPERI, and if the input reference voltage VREFD level is higher than the feedback voltage FEED, the PMOS transistor ( The internal voltage level (VPERI) generated by lowering the gate voltage of P3) is adjusted to increase. On the contrary, when the reference voltage VREFD level is lower than the feedback voltage FEED level, the level of the internal power supply voltage VPERI generated by increasing the gate voltage of the PMOS transistor P3 is adjusted to be lowered.

On the other hand, the semiconductor memory device performs a burn-in test as a control for monitoring whether the product operates normally. When performing the burn-in test, the internal power supply voltage (ferry voltage) is shorted with an external supply power supply VDD, as shown in FIG. This is because the ferry voltage is used for the control operation of the burn-in test. If the ferry voltage level is changed, it is difficult to perform normal operation of the burn-in test, and therefore, the ferry voltage is shorted with the external power voltage to maintain the external power voltage level regardless of the ferry voltage level when controlling the burn-in test. .

However, the above control operation causes the following problems. Burn-in test operation typically raises the supply voltage to a very high level to verify the operation and degradation of the circuit. Therefore, in the case of the circuit using the ferry power source, the ferry voltage is not very different from the external power supply voltage VDD, and the transistors of the circuit using the ferry voltage and the external power supply voltage are the same. As described above, a circuit for inputting the burn-in signal BI and shorting the ferry voltage and the external power supply voltage is configured. In this case, the PMOS transistor P14 acts as a switch and plays a role of shorting the ferry voltage and the external power supply voltage.

However, in the case of the ferry voltage, since the amount of current to be supplied is very large since it is used almost all over the semiconductor memory device, the PMOS transistor P14 responsible for shortening the ferry voltage with an external power supply voltage is very large. Must have a size. This has a problem in that the area portion, the heat dissipation portion, etc. adversely affect the design of the semiconductor memory device.

Accordingly, the present invention is to solve the above problems, and is a structure for shorting the reference voltage used when the ferry voltage is generated during the burn-in test with the external reference voltage, the semiconductor memory device capable of controlling the size of the switch for the short Its purpose is to provide a control circuit.

A control circuit of a semiconductor memory device according to an embodiment of the present invention for achieving the above object is characterized in that it comprises a short circuit for shorting the reference voltage used for generating a ferry voltage with an external power supply voltage during burn-in test.

A control circuit of a semiconductor memory device according to another embodiment of the present invention includes: comparison means for comparing a reference voltage with a feedback voltage; Amplifying means for generating a ferry voltage by the difference of the comparing means; Feedback means for feeding back the ferry voltage generated by the amplification means to the comparison means; And a short means for shorting a reference voltage applied to the comparison means with an external power supply voltage when the burn-in test signal is in an enabled state.

A control circuit of a semiconductor memory device according to another embodiment of the present invention, the reference voltage generator for generating a reference voltage; A trimming circuit which generates reference voltages suitable for each purpose using the reference voltage generated by the reference voltage generator; And a short circuit generated in the trimming circuit during the burn-in test and shorting the reference voltage to be used for generating the ferry voltage to an external power supply voltage.

 The present invention shorts the reference voltage VREFD, which is used when generating a ferry voltage (internal power supply voltage) during burn-in test, with an external power supply voltage. Therefore, the present invention has the advantage that a small size switch transistor can be used by shortening the reference voltage used for generating the ferry voltage without directly shorting the ferry voltage using a high current. In addition, the present invention also has the advantage of reducing the circuit area usage due to the use of small size transistors.

Hereinafter, a control circuit of a semiconductor memory device according to the present invention will be described in detail with reference to the accompanying drawings.

4 is a control circuit diagram of a semiconductor memory device according to an embodiment of the present invention.

The present invention according to the illustrated embodiment is configured to short the reference voltage (VREFD) used when generating a ferry voltage (internal power supply voltage) during the burn-in test with the external power supply voltage. To this end, the present invention includes a short portion for shorting the reference voltage with the external power supply voltage in the internal power supply voltage control circuit.

The short portion is composed of an inverter IV13 and a PMOS transistor P16. The inverter IV13 inputs and inverts a burn-in test signal BI and applies it to the gate terminal of the PMOS transistor P16. The PMOS transistor P16 connects a source terminal to a supply power supply VDD and a drain terminal to a reference voltage VREFD used as a reference voltage when the ferry voltage VPERI is generated.

The PMOS transistor P16 constituting the short portion functions as a switch, and the PMOS transistor P16 is applied to the circuit configuration and is not limited to the PMOS transistor. For example, an NMOS transistor or a diode capable of functioning as a switch is also possible. The PMOS transistor P16 may be large enough to handle the reference voltage VREFD and the external power supply VDD. That is, compared with the PMOS transistor used in the conventional short circuit, the size is relatively small.

The present invention provides a comparator comprising NMOS transistors N11 and N12 to differentially compare a feedback voltage and a reference voltage VREFD, which are generated by distributing the generated power supply voltage VPERI, to an output signal of the comparator. In order to generate and output the amplified internal power supply voltage VPERI, an amplifier having a configuration of the PMOS transistor P13, and the output internal power supply voltage are divided by the resistors R15 and R16 to output the internal power. And a feedback voltage generator for generating a feedback voltage for monitoring the power supply voltage and providing the feedback voltage to the NMOS transistor N12. A control switching unit composed of an NMOS transistor N13 for controlling the operation of the comparator, and a current mirror composed of PMOS transistors P11 and P12 are included.

The control circuit of the semiconductor memory device of the present invention configured as described above operates as follows.

First of all, when the normal operation is performed, the burn-in test signal BI is in a deactivated state (low state), so that the high signal inverted in the inverter IV13 controls the PMOS transistor P16 to turn off to control the operation of the short unit. Block it. That is, the reference voltage VREFD is normally applied to the gate terminal of the NMOS transistor N11.

In this state, a bias voltage is supplied to the gate terminal of the NMOS transistor N13 constituting the control switching unit, and the control switching unit controls the operating point of the comparison unit.

When the bias voltage is applied to the NMOS transistor N13 and is turned on, the NMOS transistor N11 is turned on by the applied reference voltage VREFD, so that the transistors N11 and N13 are turned on. The drain voltage is lowered. Accordingly, a low level signal is applied to the gate terminal of the PMOS transistor P13 operated by the voltage applied to the drain terminal of the transistor N11, and the internal power voltage VPERI output while the transistor P13 is turned on. ) Increases.

When the internal power supply voltage VPERI is increased, the feedback voltage is also increased while turning on the transistor N12. When the transistor N12 is turned on, the gate terminal voltages of the PMOS transistors P11 and P12 are lowered. When the gate terminal voltage of the PMOS transistors P11 and P12 is lowered, the potential of the drain terminal of the NMOS transistor N11 is gradually increased while being turned on. In other words, the gate voltage of the transistor P13 is gradually increased. This operation is performed until the feedback voltage and the reference voltage VREFD are equal.

Therefore, according to the embodiment of the present invention, if the reference voltage VREFD for generating the internal power supply voltage VPERI is input, and the input reference voltage VREFD level is higher than the feedback voltage FEED level, the PMOS transistor ( The internal voltage level (VPERI) generated by lowering the gate voltage of P13) is adjusted to increase. On the contrary, when the reference voltage VREFD level is lower than the feedback voltage FEED level, the level of the internal power supply voltage VPERI generated by increasing the gate voltage of the PMOS transistor P13 is adjusted to be lowered.

Next, when the burn-in test is performed, when the burn-in test signal BI is in the enabled state (high), the low signal inverted in the inverter IV13 turns on the PMOS transistor P16. When the PMOS transistor P16 is turned on, the reference voltage VREFD and the external power supply voltage VDD are shorted, and the voltage applied to the gate terminal of the NMOS transistor N11 increases to the external power supply voltage VDD level. .

In this state, a bias voltage is supplied to the gate terminal of the NMOS transistor N13 constituting the control switching unit, and the control switching unit controls the operating point of the comparison unit.

When a bias voltage is applied to the NMOS transistor N13 and turned on, the NMOS transistor N11 is turned on by an external power supply voltage VDD, and thus the transistor N11 and the transistor N13 are turned on. ), The drain voltage is lowered. Accordingly, a low level signal is applied to the gate terminal of the PMOS transistor P13 operated by the voltage applied to the drain terminal of the transistor N11, and the internal power voltage VPERI output while the transistor P13 is turned on. ) Increases.

On the other hand, when the internal power supply voltage (ferry voltage) is increased, the feedback voltage is increased at the same time, but the feedback voltage FEED input to the gate terminal of the transistor N12 is an external power source input to the gate terminal of the transistor N11. It always has a state lower than the voltage VDD.

Therefore, the NMOS transistor N11 that inputs the external power supply voltage VDD is continuously turned on. Since the turn-on resistance of the PMOS transistor P13 generating the ferry voltage is negligibly small compared to the resistance values of the voltage distribution resistors R15 and R16 generating the feedback node voltage, the output voltage is It is raised until it is close to the external power supply voltage (VDD) level.

Therefore, according to the present invention, when the burn-in test signal transitions from the low level to the high level, the reference voltage VREFD is shorted to the external power supply voltage VDD, and the reference voltage level rises to the external power supply voltage level. . In this case, since the external power supply voltage level is higher than the feedback voltage level, the NMOS transistor N11 for inputting the external power supply voltage is turned on. Therefore, the PMOS transistor P13 to which the output node is connected is also turned on, so that the output signal level rises.

Since the feedback voltage level is always lower than the external power supply voltage level, the NMOS transistor N11 inputting the external power supply voltage is continuously turned on, so that the PMOS transistor P13 driving the ferry voltage is turned on. Since the resistance is negligibly small compared with the resistance of the voltage divider resistor that generates the feedback voltage, the voltage of the output node rises until it approaches the level of the external power supply voltage VDD.

Next, FIG. 5 shows a control circuit diagram of a semiconductor memory device according to another embodiment of the present invention.

In the illustrated embodiment, in order to short the reference voltage used for generating the ferry voltage with an external power supply voltage, the short circuit is included in the reference voltage generating circuit for generating the reference voltage VREFD used for generating the ferry voltage.

That is, as shown, the reference voltage of the internal power supplies used for various purposes in the semiconductor memory device is generated by the reference voltage generator 30 (REF_GEN) and the trimming circuit 40 (Trimming Block). The reference voltage VR0 generated from the reference voltage generator 30 is supplied to the trimming circuit 40. The trimming circuit 40 divides the voltage into appropriate sizes by using the voltage divider resistors R7 to R10 in order to generate the reference voltages VREFD and VREF2 to VREF3 suitable for each purpose.

Similarly, the internal power supply voltage VPERI used in the burn-in device is also generated using the reference voltage VREFD generated by the reference voltage generator.

Therefore, in the control circuit of the present invention, the reference voltage VREFD used for generating the ferry voltage is shorted to the external power supply voltage VDD during the burn-in test. That is, the switch P15 which is turned on / off by the burn-in test signal BI is connected between the external power supply voltage VDD and the output node of the reference voltage VREFD. An inverter IV12 is connected to the switch P15.

According to this configuration, in the present invention, when the burn-in test signal BI is in an enabled state, the low signal generated while being inverted in the inverter IV12 turns on the PMOS transistor P15. In this operation, the node outputting the reference voltage VREFD is shorted to the external power supply voltage VDD, and the output voltage becomes the external power supply voltage VDD. Thereafter, in the internal power supply voltage (ferry voltage) generation circuit, the external power supply voltage VDD is input as the reference voltage VREFD, and the subsequent operation is the same as that described in FIG.

Also in the embodiment described above, the PMOS transistor P15 constituting the short portion functions as a switch, and the PMOS transistor is applied to the circuit configuration and is not limited to the PMOS transistor. For example, an NMOS transistor or a diode capable of functioning as a switch is also possible. The PMOS transistor P15 may be large enough to handle the reference voltage VREFD and the external power supply VDD. That is, compared with the PMOS transistor used in the conventional short circuit, the size is relatively small.

The above-described preferred embodiment of the present invention is disclosed for the purpose of illustration, and may be applied to the case where the ferry voltage is shorted with the external power supply voltage during burn-in test in the semiconductor memory device. Therefore, those skilled in the art will be able to improve, change, substitute or add other embodiments within the technical spirit and scope of the present invention disclosed in the appended claims.

1 is a reference voltage generation circuit diagram according to the prior art;

2 is a circuit diagram for generating a conventional internal reference voltage (ferry voltage);

3 is a circuit diagram for short control of a conventional ferry voltage and an external power supply voltage;

4 is a control circuit diagram of a semiconductor memory device according to an embodiment of the present invention;

5 is a control circuit diagram of a semiconductor memory device according to another embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

P11 to P16: PMOS transistor N11 to N13: NMOS transistor

R7 ~ R16: Resistor IV12, IV13: Inverter

30: reference voltage generator 40: trimming circuit

Claims (6)

And a short circuit for shorting a reference voltage used for generating a ferry voltage with an external power supply voltage during a burn-in test. Comparison means for comparing the reference voltage with the feedback voltage; Amplifying means for generating a ferry voltage by the difference of the comparing means; Feedback means for feeding back the ferry voltage generated by the amplification means to the comparison means; And shorting means for shorting a reference voltage applied to said comparing means with an external power supply voltage when the burn-in test signal is in an enabled state. The method of claim 2, The short means includes a switching element connected between the reference voltage input terminal of the comparison means and an external power supply voltage, And the switching device is turned on when the burn-in test signal is in an enabled state. The method of claim 3, wherein The switching element is a control circuit of a semiconductor memory device, characterized in that the PMOS transistor. The method of claim 4, wherein And said shorting means further comprises an inverter for inverting said burn-in test signal and providing it to said PMOS transistor. A reference voltage generator for generating a reference voltage; A trimming circuit which generates reference voltages suitable for each purpose using the reference voltage generated by the reference voltage generator; And a short circuit generated in the trimming circuit during the burn-in test, which short-circuits a reference voltage to be used for generating a ferry voltage to an external power supply voltage.

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