CN114373497A - Fuse burning circuit - Google Patents
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- CN114373497A CN114373497A CN202210021600.0A CN202210021600A CN114373497A CN 114373497 A CN114373497 A CN 114373497A CN 202210021600 A CN202210021600 A CN 202210021600A CN 114373497 A CN114373497 A CN 114373497A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/18—Auxiliary circuits, e.g. for writing into memory
Abstract
Provided is a fuse burning circuit including: the grid electrode of the burning transistor is connected with the burning enabling signal and is configured to be switched on or switched off under the control of the burning enabling signal; a fuse resistor connected in series with the burning transistor between a power voltage and a ground voltage and configured to be blown out to perform burning when the burning transistor is turned on; a read circuit connected to a first end of the fuse resistor and configured to output a burning output signal indicating whether the fuse burning circuit has performed burning; and a latch configured to latch a burst output signal output through the read circuit. According to the fuse burning circuit design scheme, the fuse burning and the burning information reading can be achieved by adopting a simple circuit connection mode and elements, the accuracy of a chip is improved, and a small-size and high-reliability fuse circuit is achieved.
Description
Technical Field
The disclosure relates to the field of integrated circuit design, and in particular to a fuse burning circuit.
Background
With the continuous development of the integrated circuit industry, the chip technology is continuously updated, the size of the chip is gradually reduced, and meanwhile, the precision requirement on the circuit is gradually improved. However, in the chip manufacturing process, due to the influence of the process deviation of manufacturers, layout mismatch, different chip production batches and the like, the actual circuit test result may have a large deviation from the expected value in the simulation design. Thus, it is possible to incorporate a fuse (fuse) circuit at the time of circuit design according to the prior art or to achieve an adjustment and permanent solidification of some circuit parameters or controls according to ROM or OTP technology. Because the fuse circuit has a relatively simple structure and high reliability when the chip is produced in large scale, the fuse circuit is widely applied to the high-precision design of the chip at present. When the chip is tested, the test result can be compared with the design value, and fine adjustment is carried out through the fuse circuit, so that the precision of the circuit is improved.
Disclosure of Invention
Technical problem
At present, the erasable ROM or OTP technology is widely adopted in circuit design, and the technology needs special process support or only can purchase IP of a chip manufacturer and is not easy to customize. However, customized fuses may allow for more compact and flexible circuit designs. Therefore, some circuits need to be designed to realize fuse burning and information whether the circuit has burned or not can be "read" by the circuits.
Solution to the problem
An embodiment of the present disclosure provides a fuse burning circuit, including: the grid electrode of the burning transistor is connected with the burning enabling signal and is configured to be switched on or switched off under the control of the burning enabling signal; a fuse resistor connected in series with the burning transistor between a power voltage and a ground voltage and configured to be blown out to perform burning when the burning transistor is turned on; a read circuit connected to a first end of the fuse resistor and configured to output a burning output signal indicating whether the fuse burning circuit has performed burning; and a latch configured to latch a burst output signal output through the read circuit.
According to the embodiment of the disclosure, the reading circuit comprises a first current source, a second current source, a reference resistor and a comparator, wherein the source electrode of the burning transistor is connected with the power supply voltage, and the drain electrode of the burning transistor is connected with the first end of the fuse resistor; the first current source is connected between the power supply voltage and a first end of the fuse resistor; the second end of the fuse resistor is connected with the ground voltage; the second current source is connected in series with the reference resistor between the power supply voltage and the ground voltage; and a first input of the comparator is connected to a first terminal of the fuse resistance, a second input of the comparator is connected to a first terminal of the reference resistance, and an output of the comparator is connected to an input of the latch.
According to the embodiment of the disclosure, the reading circuit comprises a reference resistor and a comparator, wherein the source electrode of the burning transistor is connected with the power supply voltage, and the drain electrode of the burning transistor is connected with the first end of the fuse resistor; the second end of the fuse resistor is connected with the ground voltage; the reference resistor is connected between the power supply voltage and a first end of the fuse resistor; and a first input of the comparator is connected to a first terminal of the fuse resistance, a second input of the comparator is connected to a reference voltage, and an output of the comparator is connected to an input of the latch.
According to the embodiment of the disclosure, the reading circuit comprises a reference resistor and a comparator, wherein the source electrode of the burning transistor is connected with the ground voltage, and the drain electrode of the burning transistor is connected with the first end of the fuse resistor; the second end of the fuse resistor is connected with the power supply voltage; the reference resistor is connected between a first end of the fuse resistor and the ground voltage; and a first input of the comparator is connected to a reference voltage, a second input of the comparator is connected to a first terminal of the fuse resistance, and an output of the comparator is connected to an input of the latch.
According to the embodiment of the disclosure, the reading circuit comprises a reference resistor and N inverters, wherein N is a positive integer, a source electrode of the burning transistor is connected with the power supply voltage, and a drain electrode of the burning transistor is connected with a first end of the fuse resistor; the second end of the fuse resistor is connected with the ground voltage; the reference resistor is connected between the power supply voltage and a first end of the fuse resistor; and the N inverters are connected in series in sequence, wherein the input end of the first inverter of the N inverters is connected with the first end of the fuse resistor, and the output end of the Nth inverter of the N inverters is connected with the input end of the latch.
According to the embodiment of the disclosure, the reading circuit comprises a reference resistor and N inverters, wherein N is a positive integer, a source electrode of the burning transistor is connected with the ground voltage, and a drain electrode of the burning transistor is connected with a first end of the fuse resistor; the second end of the fuse resistor is connected with the power supply voltage; the reference resistor is connected between a first end of the fuse resistor and the ground voltage; and the N inverters are connected in series in sequence, wherein the input end of the first inverter of the N inverters is connected with the first end of the fuse resistor, and the output end of the Nth inverter of the N inverters is connected with the input end of the latch.
According to the embodiment of the present disclosure, an inverter is further provided before the input terminal of the latch or after the output terminal of the latch to adjust the level of the output signal of the latch.
According to an embodiment of the present disclosure, the fuse burning circuit further includes a switch connected in series with the reference resistance and/or the fuse resistance and configured to be opened after burning is completed.
According to the embodiment of the disclosure, the burning transistor is a PMOS transistor or an NMOS transistor.
According to an embodiment of the present disclosure, the comparator is a current comparator or a voltage comparator.
Advantageous effects
The invention provides several fuse burning circuit design schemes, which can realize fuse burning and burning information reading by adopting a simple circuit connection mode and elements, improve the precision of a chip and realize a small-size and high-reliability fuse circuit. The design scheme of the fuse burning circuit provided by the disclosure comprises the steps of respectively adopting circuit structures of a burning transistor, a comparator, a burning transistor, an inverter and the like to burn the fuse, wherein the circuit structures are simpler than the traditional structure, small in size, low in cost and low in power consumption, and the reliability of the fuse circuit is enhanced while the accuracy of a chip is improved.
Drawings
The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description when taken in conjunction with the accompanying drawings, in which:
fig. 1 illustrates an example 100 of a fuse according to an embodiment of the present disclosure.
Figure 2 illustrates an example circuit structure 200 of a fuse burning circuit according to an embodiment of the present disclosure.
FIG. 3 illustrates an example circuit configuration 300 of a fuse burn circuit that employs PMOS transistors and comparators for fuse burn in accordance with an embodiment of the disclosure.
FIG. 4 illustrates an example circuit structure 400 of a fuse burning circuit that employs PMOS transistors and comparators for fuse burning in accordance with an embodiment of the disclosure.
FIG. 5 illustrates an example circuit structure 500 of a fuse burning circuit that employs NMOS transistors and comparators for fuse burning, according to an embodiment of the disclosure.
FIG. 6 illustrates an example circuit structure 600 of a fuse burning circuit that employs PMOS transistors and inverters for fuse burning according to an embodiment of the disclosure.
FIG. 7 illustrates an example circuit structure 700 of a fuse burning circuit that employs NMOS transistors and inverters for fuse burning, according to an embodiment of the disclosure.
Detailed Description
Before proceeding with the following detailed description, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document. The terms "couple," "connect," and derivatives thereof refer to any direct or indirect communication or connection between two or more elements, whether or not those elements are in physical contact with one another. The terms "transmit," "receive," and "communicate," as well as derivatives thereof, encompass both direct and indirect communication. The terms "include" and "comprise," as well as derivatives thereof, mean inclusion without limitation. The term "or" is inclusive, meaning and/or. The phrases "associated with … …," "corresponding to … …," and derivatives thereof, mean including, included within … …, interconnected, contained within … …, connected or connected with … …, coupled or coupled with … …, in communication with … …, mated, interleaved, juxtaposed, proximate, bound or bound with … …, having an attribute, having a relationship with … …, and the like. The term "controller" refers to any device, system, or part thereof that controls at least one operation. Such a controller may be implemented in hardware, or a combination of hardware and software and/or firmware. The functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. The phrase "at least one of, when used with a list of items, means that a different combination of one or more of the listed items can be used and only one item in the list may be required. For example, "at least one of A, B, C" includes any one of the following combinations: A. b, C, A and B, A and C, B and C, A and B and C.
Definitions for other specific words and phrases are provided throughout this patent document. Those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases.
In this patent document, the application combination of modules and the division levels of sub-modules are only used for illustration, and the application combination of modules and the division levels of sub-modules may have different manners without departing from the scope of the present disclosure. Embodiments of the present disclosure may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey exemplary embodiments to those skilled in the art. Embodiments of the present disclosure may be combined to form further embodiments.
Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.
Fig. 1 illustrates an example of a fuse according to an embodiment of the present disclosure. As shown in fig. 1, the fuse (100) itself may be implemented using a small segment of wiring within the integrated circuit. It may be a poly resistor or a metal wire, but it is typically a very narrow wire, which itself has a weak ability to overpower a DC current. Such a wire may be "blown" when a large current is passed through it. In this context, "blown" may be that it is blown or that the resistance becomes larger, e.g., much larger than the resistance of a particular reference resistance, due to electromigration. Embodiments of the present disclosure provide circuits that can enable fuse burning and by which information whether the circuit has been burned can be "read".
Figure 2 illustrates an example circuit structure 200 of a fuse burning circuit according to an embodiment of the present disclosure.
As shown in fig. 2, the fuse burning circuit 200 may include: a burning transistor 201, a Fuse resistance (Fuse _ R)202, a reading circuit 203, and a latch 204. According to an embodiment of the present disclosure, the burning transistor 201 may be a PMOS transistor or an NMOS transistor. In fig. 2, as an example, the burn transistor 201 is shown as a PMOS transistor. The gate of the burning transistor 201 may be connected to a burning enable signal (e.g., Fuse _ En) for controlling whether to perform burning, and the burning transistor 201 may be configured to be turned on or off under the control of the burning enable signal. The fuse resistor 202 may be connected in series with the burn transistor 201 between a power supply Voltage (VDD) and a Ground voltage (Ground), and may be configured to be blown to perform burn when the burn transistor 201 is turned on. The read circuit 203 can be used to read the burst output signal from a particular node in the circuit. For example, an input terminal of the reading circuit 203 may be connected to a first terminal of the fuse resistor 202 and configured to output the programming output signal. The programming output signal can be used to indicate whether the fuse programming circuit 200 has performed programming. An input of the latch 204 may be connected to an output of the read circuit 203 and may be configured to latch the burst output signal output via the read circuit 203.
In some embodiments, the read circuit 203 may include a first current source, a second current source, a reference resistance, and a comparator. In the present disclosure, the comparator may be a current comparator or a voltage comparator. According to the embodiment of the disclosure, the source of the burning transistor may be connected to a power supply voltage, and the drain of the burning transistor may be connected to the first end of the fuse resistor; the first current source may be connected between a power supply voltage and a first terminal of the fuse resistance; the second terminal of the fuse resistor may be connected to a ground voltage; the second current source may be connected in series with the reference resistor between the power supply voltage and the ground voltage; a first input of the comparator may be connected to a first terminal of the fuse resistance, a second input of the comparator may be connected to a first terminal of the reference resistance, and an output of the comparator may be connected to an input of the latch.
More specifically, fig. 3 shows an example circuit structure 300 of a fuse burning circuit that employs PMOS transistors and comparators for fuse burning according to an embodiment of the disclosure.
As shown in fig. 3, the source terminal of the transistor 305 is connected to VDD, the drain terminal is connected to the Fuse resistor 301, and the gate terminal is connected to the programming enable signal (Fuse _ En signal); the positive end of the current source 303 is connected with VDD, and the negative end is connected with the fuse resistor 301; the positive terminal of the current source 304 is connected to VDD, and the negative terminal is connected to the reference resistor 302; the positive end of the comparator 306 is connected with the fuse resistor 301, and the negative end is connected with the reference resistor 302; the output end of the comparator 306 is connected with the input end of the latch 307; the latch 307 outputs a signal of burning Data Fuse _ Data. When the circuit is programmed, Fuse _ En is at a low level for a period of time, Fuse resistor 301 is blown or the resistance of resistor 301 becomes larger due to electromigration, for example, as mentioned above, it is much larger than the resistance of the reference resistor. When the circuit needs to be read to write information, the comparator 306 may be turned on, the write output signal output by the comparator 306 is at a high level, and enters the latch 307, and the output signal Fuse _ Data is at a high level. If the program is not recorded, the Fuse _ En signal is always high, the transistor 305 is turned off, and the Fuse resistor 301 is not blown. Since the resistance of the Fuse resistor 301 is much smaller than that of the reference resistor 302 when it is not blown, when reading information, the comparator 306 outputs a low level, the output signal (i.e., the programming output signal) of the comparator 306 enters the latch 307, and the latch 307 outputs the generated Fuse _ Data signal as a low level. In some embodiments, the information about whether the circuit is burned or not can be obtained by reading the burning output signal output by the comparator 306 or the burning Data Fuse _ Data output by the latch 307. In the case of reading the burning Data Fuse _ Data output by the latch 307 to obtain the information about whether the circuit is burning, the fact that whether Fuse _ Data is burnt can be artificially defined by using a high level or a low level can be realized by adding an inverter before or after the latch. For example, the level of the output signal Fuse _ Data of the latch may be adjusted by providing one or more inverters before the input of the latch and/or after the output of the latch.
In some embodiments, the read circuit 203 may include a reference resistor and a comparator. The comparator may be a current comparator or a voltage comparator, and the voltage comparator is described as an example below. According to the embodiment of the disclosure, the source of the burning transistor may be connected to a power supply voltage, and the drain of the burning transistor may be connected to the first end of the fuse resistor; the second terminal of the fuse resistor may be connected to a ground voltage; the reference resistor may be connected between a power supply voltage and a first terminal of the fuse resistor; a first input of the comparator may be connected to a first terminal of the fuse resistance, a second input of the comparator may be connected to a reference voltage, and an output of the comparator may be connected to an input of the latch.
More specifically, fig. 4 shows an example circuit structure 400 of a fuse burning circuit that employs PMOS transistors and comparators for fuse burning according to an embodiment of the disclosure.
As shown in fig. 4, an example circuit structure 400 may include: fuse resistance Fuse _ R401, reference resistance R0402, PMOS burning transistor MP 1403, voltage comparator 404 and latch 405.
According to the embodiment shown in fig. 4, the transistor 403 has a source terminal connected to VDD, a drain terminal connected to the Fuse resistor 401, the reference resistor 402 and the non-inverting input terminal of the comparator 404, and a gate terminal connected to the Fuse _ En signal; the fuse resistor 401 and the reference resistor 402 are connected in series; the negative phase input of the comparator 404 is connected to the reference voltage Vref, and the output is connected to the input of the latch 405, and according to the embodiment of the present invention, the reference voltage Vref may be any voltage between the power voltage and the ground voltage, but the present invention is not limited thereto, and may be other voltages; latch 405 outputs a signal Fuse _ Data. When the circuit needs to be programmed, Fuse _ En is at a low level for a period of time, and Fuse resistor 401 is blown. When it is necessary to read the information whether the circuit is burned or not, only the output of the comparator 404 or the output of the latch 405 may be needed to be seen. If the programming is done, the output of the comparator 404 is at a high level, and if the programming is not done, the output is at a low level, and the programming output signal output by the comparator 404 can enter the latch 405, thereby outputting the signal Fuse _ Data. One or more switches may be connected in series to the fuse resistor 401 and/or the reference resistor 402, and the comparator and the switch connected in series may be turned off after the programming or the information reading is completed, so that the fuse unit does not consume power when the circuit operates, and this design may be applied to any embodiment of the present disclosure, and will not be described in detail below. Whether Fuse _ Data is represented by high level or low level for burning can be artificially defined, and can be realized by adding an inverter before or after the latch. For example, the level of the output signal Fuse _ Data of the latch may be adjusted by providing one or more inverters before the input of the latch and/or after the output of the latch.
In some embodiments, the read circuit 203 may include a reference resistor and a comparator. The comparator may be a current comparator or a voltage comparator, and the voltage comparator is described as an example below. According to the embodiment of the disclosure, the source electrode of the burning transistor can be connected with the ground voltage, and the drain electrode of the burning transistor can be connected with the first end of the fuse resistor; the second terminal of the fuse resistor may be connected to a supply voltage; the reference resistor may be connected between a first terminal of the fuse resistor and a ground voltage; a first input of the comparator may be coupled to a reference voltage, a second input of the comparator may be coupled to a first terminal of the fuse resistance, and an output of the comparator may be coupled to an input of the latch.
More specifically, fig. 5 illustrates an example circuit structure 500 of a fuse burning circuit that employs NMOS transistors and comparators for fuse burning according to an embodiment of the disclosure.
As shown in fig. 5, an example circuit structure 500 may include: fuse resistance Fuse _ R501, reference resistance R0502, NMOS programming transistor MN1, voltage comparator 504, and latch 505.
According to the embodiment shown in fig. 5, the transistor 503 has a source terminal connected to ground, a drain terminal connected to the Fuse resistor 501, the reference resistor 502 and the negative input terminal of the comparator 504, and a gate terminal connected to the Fuse _ En signal; the fuse resistor 501 is connected in series with the reference resistor 502; the positive phase input end of the comparator 504 is connected with the reference voltage Vref, and the output end is connected with the input end of the latch 505; the latch 505 output signal is Fuse _ Data. When the circuit is programmed, Fuse _ En is at high level for a period of time, and Fuse resistor 501 is blown. When the information about whether the circuit is burned or not needs to be read, the output of the comparator 504 or the output of the latch 505 can be only needed to be seen. If the program is burned, the output of the comparator 504 is high level, and enters the latch 505, and the output signal Fuse _ Data is high level. If not, comparator 504 outputs a low level. Whether Fuse _ Data is represented by high level or low level for burning can be artificially defined, and can be realized by adding an inverter before or after the latch. For example, the level of the output signal Fuse _ Data of the latch may be adjusted by providing one or more inverters before the input of the latch and/or after the output of the latch.
According to the embodiment of the disclosure, when the resistance value of the fuse resistor is larger after the fuse resistor is blown, an inverter can be used for replacing a voltage comparator for circuit simplification.
In some embodiments, the read circuit 203 may include a reference resistor and N inverters, N being a positive integer. According to the embodiment of the disclosure, the source of the burning transistor may be connected to a power supply voltage, and the drain of the burning transistor may be connected to the first end of the fuse resistor; the second terminal of the fuse resistor may be connected to a ground voltage; the reference resistor may be connected between a power supply voltage and a first terminal of the fuse resistor; the N inverters may be connected in series, for example, the output of a first inverter is connected to the input of a second inverter, the output of the second inverter is connected to the input of a third inverter, and so on. An input terminal of a first one of the N inverters may be connected to a first terminal of the fuse resistor, and an output terminal of an nth one of the N inverters may be connected to an input terminal of the latch.
More specifically, fig. 6 shows an example circuit structure 600 of a fuse burning circuit that employs PMOS transistors and inverters for fuse burning according to an embodiment of the disclosure.
As shown in fig. 6, an example circuit structure 600 may include: a Fuse resistor Fuse _ R601, a reference resistor R0602, a PMOS burning transistor MP 1603, two inverters 604 and 605, and a latch 606. It should be understood that the number N of inverters can be flexibly customized or selected depending on the high and low levels of the desired output, and is not limited herein.
According to the embodiment shown in fig. 6, the source terminal of the transistor 603 is connected to VDD, the drain terminal is connected to the Fuse resistor 601, the reference resistor 602, and the input terminal of the inverter 604, and the gate terminal is connected to the Fuse _ En signal; the fuse resistor 601 is connected in series with the reference resistor 602; the inverter 604 is connected with the inverter 605 in series, and the output end of the inverter 605 is connected with the input end of the latch 606; the latch 606 outputs a signal Fuse _ Data. When the circuit is programmed, Fuse _ En is at low level, Fuse resistor 601 is blown, inverter 605 outputs at high level, and enters latch 606, and output signal Fuse _ Data is at high level.
In some embodiments, the read circuit 203 may include a reference resistor and N inverters, N being a positive integer. According to the embodiment of the disclosure, the source of the burning transistor may be connected to a power supply voltage, and the drain of the burning transistor may be connected to the first end of the fuse resistor; the second terminal of the fuse resistor may be connected to a ground voltage; the reference resistor may be connected between a power supply voltage and a first terminal of the fuse resistor; the N inverters may be connected in series, for example, the output of a first inverter is connected to the input of a second inverter, the output of the second inverter is connected to the input of a third inverter, and so on. An input terminal of a first one of the N inverters may be connected to a first terminal of the fuse resistor, and an output terminal of an nth one of the N inverters may be connected to an input terminal of the latch.
More specifically, fig. 7 shows an example circuit structure 700 of a fuse burning circuit that employs NMOS transistors and inverters for fuse burning according to an embodiment of the present disclosure.
As shown in fig. 7, an example circuit structure 700 may include: fuse resistance Fuse _ R701, reference resistance R0702, NMOS burning transistor MN 1703, inverter 704 and latch 705.
According to the embodiment shown in fig. 7, the transistor 703 has a source terminal connected to ground, a drain terminal connected to the Fuse resistor 701, the reference resistor 702, and the input terminal of the inverter 704, and a gate terminal connected to the Fuse _ En signal; the fuse resistor 701 is connected in series with the reference resistor 702; the output end of the inverter 704 is connected with the input end of the latch 705; latch 705 outputs a signal Fuse _ Data. When the circuit is programmed, Fuse _ En is at high level, Fuse resistor 701 is blown, inverter 704 outputs at high level, and enters latch 705, and output signal Fuse _ Data is at high level.
An example burning process and burning information reading process of the fuse burning circuit according to the embodiment of the disclosure are described below by taking fig. 4-7 as an example again.
In the case of the exemplary circuit configuration 400 shown in fig. 4, as shown in fig. 4, when a Fuse unit needs to be burned, the Fuse _ En may be set to a low level for a while, the transistor 403 is turned on, and the Fuse resistor 401 is blown or the resistance becomes large in a short time due to the generation of a large current. Fuse _ En is only set low for a period of time when the cell needs to be burned. The process of reading the burning information can be as follows: when the burning information needs to be read, current can be injected into the fuse resistor 401 and the reference resistor 402. If the cell is not programmed, the resistance of the fuse resistor 401 is much smaller than the reference resistor 402, so the positive input terminal of the comparator 404 is at a low level, the voltage value is smaller than Vref, and the output terminal is at a low level. The output signal of comparator 404 enters latch 405 and latch 405 outputs the generated Fuse _ Data signal as a low level. If the cell is programmed, the resistance value of fuse resistor 401 after fuse is much greater than the resistance value of reference resistor 402, so the positive input terminal of comparator 404 is at high level, the voltage value is greater than Vref, and the output terminal is at high level. The output signal of comparator 404 enters latch 405 and latch 405 outputs the generated Fuse _ Data signal as high. As described above, when it is necessary to read the information about whether the circuit is burned, the output of the comparator or the output of the latch may be read. After reading this information we can turn off these currents and comparators so that the cell does not generate power consumption during actual circuit operation. In some embodiments, the burning information can be kept as long as the power of the chip is not turned off. If the chip is powered off and then powered on next time, the reading process can be repeated, so that the burning information can be obtained again.
In the case of the example circuit configuration 500 shown in fig. 5, when the Fuse _ En signal is low, the transistor 503 is turned off and the Fuse resistor 501 is not blown, as shown in fig. 5. Since the resistance of the fuse resistor 501 is much smaller than that of the reference resistor 502 when the fuse resistor 501 is not blown, the negative input terminal of the comparator 504 is at a high level, the voltage value is greater than Vref, and the output terminal is at a low level. The output signal of the comparator 504 enters the latch 505, and the latch 505 outputs the generated Fuse _ Data signal as a low level. When Fuse _ En is at a high level, the transistor 503 is turned on, and the Fuse resistor 501 is blown in a short time by generating a large current. Since the resistance value of the fuse resistor 501 after being fused is much larger than that of the reference resistor 502, the negative input terminal of the comparator 504 is at a low level, the voltage value is smaller than Vref, and the output terminal is at a high level. The output signal of the comparator 504 enters the latch 505, the latch 505 outputs the generated Fuse _ Data signal as high level, and the Fuse circuit completes burning. As described above, when it is necessary to read the information about whether the circuit is burned, the output of the comparator or the output of the latch may be read.
In the case of the example circuit configuration 600 shown in fig. 6, when the Fuse _ En signal is high, the transistor 603 is turned off and the Fuse resistor 601 is not blown, as shown in fig. 6. Since the resistance of the fuse resistor 601 is much smaller than that of the reference resistor 602 when the fuse resistor is not blown, the input end of the inverter 604 is at a low level, and the output end is at a high level; inverter 605 has a high input and a low output. The output signal of inverter 605 enters latch 606, and the output of latch 606 generates the Fuse _ Data signal as a low level. When Fuse _ En is at a low level, the transistor 603 is turned on, and the Fuse resistor 601 is blown in a short time by generating a large current. Because the resistance value of the fuse resistor 601 after being fused is far larger than that of the reference resistor 602, the input end of the inverter 604 is at a high level, and the output end thereof is at a low level; the inverter 605 has a low input and a high output. The output signal of the inverter 605 enters the latch 606, the latch 606 outputs a Fuse _ Data signal which is generated to be at a high level, and the Fuse circuit finishes burning. When the information whether the circuit is burned or not needs to be read, the output of the inverter or the output of the latch can be read.
In the case of the example circuit configuration 700 shown in fig. 7, when the Fuse _ En signal is low, the transistor 703 is turned off and the Fuse resistor 701 is not blown, as shown in fig. 7. Since the resistance of fuse resistor 701 is much smaller than reference resistor 702 when it is not blown, the input of inverter 704 is at high level and the output is at low level. The output signal of inverter 704 enters latch 705, and latch 705 outputs a Fuse _ Data signal that is low. When Fuse _ En is at a high level, the transistor 703 is turned on, and the Fuse resistor 701 is blown in a short time by generating a large current. Since the resistance of the fuse resistor 701 after being fused is much larger than the resistance of the reference resistor 702, the input terminal of the inverter 704 is at a low level and the output terminal thereof is at a high level. The output signal of the inverter 704 enters the latch 705, the latch 705 outputs a Fuse _ Data signal which is generated to be at a high level, and the Fuse circuit finishes burning. As described above, when it is necessary to read the information about whether the circuit is burned, the output of the comparator or the output of the latch may be read.
Although the present disclosure has been described with exemplary embodiments, various changes and modifications may be suggested to one skilled in the art. The present disclosure is intended to embrace such alterations and modifications as fall within the scope of the appended claims.
None of the description in this disclosure should be read as implying that any particular element, step, or function is an essential element which must be included in the claims scope. The scope of patented subject matter is defined only by the claims.
Exemplary embodiments in accordance with the present disclosure have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purposes of limitation. In some instances, features, characteristics, and/or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics, and/or elements described in connection with other embodiments unless stated otherwise. Accordingly, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the claims.
Claims (10)
1. A fuse burning circuit, comprising:
the grid electrode of the burning transistor is connected with the burning enabling signal and is configured to be switched on or switched off under the control of the burning enabling signal;
a fuse resistor connected in series with the burning transistor between a power voltage and a ground voltage and configured to be blown out to perform burning when the burning transistor is turned on;
a read circuit connected to a first end of the fuse resistor and configured to output a burning output signal indicating whether the fuse burning circuit has performed burning; and
a latch configured to latch a burst output signal output via the read circuit.
2. The fuse burning circuit of claim 1,
the read circuit includes a first current source, a second current source, a reference resistance, and a comparator, wherein,
the source electrode of the burning transistor is connected with the power supply voltage, and the drain electrode of the burning transistor is connected with the first end of the fuse resistor;
the first current source is connected between the power supply voltage and a first end of the fuse resistor;
the second end of the fuse resistor is connected with the ground voltage;
the second current source is connected in series with the reference resistor between the power supply voltage and the ground voltage; and is
A first input terminal of the comparator is connected to a first terminal of the fuse resistor, a second input terminal of the comparator is connected to a first terminal of the reference resistor, and an output terminal of the comparator is connected to an input terminal of the latch.
3. The fuse burning circuit of claim 1,
the read circuit includes a reference resistance and a comparator, wherein,
the source electrode of the burning transistor is connected with the power supply voltage, and the drain electrode of the burning transistor is connected with the first end of the fuse resistor;
the second end of the fuse resistor is connected with the ground voltage;
the reference resistor is connected between the power supply voltage and a first end of the fuse resistor; and is
A first input of the comparator is connected to a first terminal of the fuse resistance, a second input of the comparator is connected to a reference voltage, and an output of the comparator is connected to an input of the latch.
4. The fuse burning circuit of claim 1,
the read circuit includes a reference resistance and a comparator, wherein,
the source electrode of the burning transistor is connected with the ground voltage, and the drain electrode of the burning transistor is connected with the first end of the fuse resistor;
the second end of the fuse resistor is connected with the power supply voltage;
the reference resistor is connected between a first end of the fuse resistor and the ground voltage; and is
A first input of the comparator is coupled to a reference voltage, a second input of the comparator is coupled to a first end of the fuse resistor, and an output of the comparator is coupled to an input of the latch.
5. The fuse burning circuit of claim 1,
the reading circuit includes a reference resistor and N inverters, N being a positive integer, wherein,
the source electrode of the burning transistor is connected with the power supply voltage, and the drain electrode of the burning transistor is connected with the first end of the fuse resistor;
the second end of the fuse resistor is connected with the ground voltage;
the reference resistor is connected between the power supply voltage and a first end of the fuse resistor; and is
The N phase inverters are sequentially connected in series, wherein the input end of a first phase inverter of the N phase inverters is connected with the first end of the fuse resistor, and the output end of an Nth phase inverter of the N phase inverters is connected with the input end of the latch.
6. The fuse burning circuit of claim 1,
the reading circuit includes a reference resistor and N inverters, N being a positive integer, wherein,
the source electrode of the burning transistor is connected with the ground voltage, and the drain electrode of the burning transistor is connected with the first end of the fuse resistor;
the second end of the fuse resistor is connected with the power supply voltage;
the reference resistor is connected between a first end of the fuse resistor and the ground voltage; and is
The N phase inverters are sequentially connected in series, wherein the input end of a first phase inverter of the N phase inverters is connected with the first end of the fuse resistor, and the output end of an Nth phase inverter of the N phase inverters is connected with the input end of the latch.
7. The fuse burning circuit of claim 1, wherein an inverter is further disposed before the input terminal of the latch or after the output terminal of the latch for adjusting the level of the output signal of the latch.
8. The fuse burning circuit of any one of claims 2-6, further comprising a switch in series with the reference resistance and/or the fuse resistance and configured to open after burning is complete.
9. The fuse burning circuit of claim 1, wherein the burning transistor is a PMOS transistor or an NMOS transistor.
10. The fuse burning circuit of any one of claims 2-6, wherein the comparator is a current comparator or a voltage comparator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210021600.0A CN114373497A (en) | 2022-01-10 | 2022-01-10 | Fuse burning circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210021600.0A CN114373497A (en) | 2022-01-10 | 2022-01-10 | Fuse burning circuit |
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| CN114373497A true CN114373497A (en) | 2022-04-19 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210021600.0A Pending CN114373497A (en) | 2022-01-10 | 2022-01-10 | Fuse burning circuit |
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| WO2023221390A1 (en) * | 2022-05-19 | 2023-11-23 | 长鑫存储技术有限公司 | Anti-fuse circuit and method for real-time verification of burning state of anti-fuse unit |
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