KR20090104973A - Method for fabricating fine pattern of semiconductor device - Google Patents

Method for fabricating fine pattern of semiconductor device Download PDF

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KR20090104973A
KR20090104973A KR1020080030167A KR20080030167A KR20090104973A KR 20090104973 A KR20090104973 A KR 20090104973A KR 1020080030167 A KR1020080030167 A KR 1020080030167A KR 20080030167 A KR20080030167 A KR 20080030167A KR 20090104973 A KR20090104973 A KR 20090104973A
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sacrificial
spacer
layer
film
pattern
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KR1020080030167A
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Korean (ko)
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정영균
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주식회사 하이닉스반도체
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Publication of KR20090104973A publication Critical patent/KR20090104973A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H01L21/28141—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects insulating part of the electrode is defined by a sidewall spacer, e.g. dummy spacer, or a similar technique, e.g. oxidation under mask, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE: A method for fabricating a fine pattern of a semiconductor device is provided to form a normal fine etch pattern by solving a problem that a sharp pattern of a spacer pattern is transferred on a target layer. CONSTITUTION: A method for fabricating a fine pattern of a semiconductor device is comprised of the steps: forming a plurality of first sacrificing layers on an etched layer(22); forming a spacer(24) at both sides of the first sacrificing layer; forming the second sacrificing layer(25A) filling a spacer gap; etching a part of a first and second scarification layer and exposing the sharp pattern of the spacer to the outside; and forming the third sacrificing layer(26) covering the sharp pattern.

Description

반도체 소자의 미세 패턴 제조 방법{METHOD FOR FABRICATING FINE PATTERN OF SEMICONDUCTOR DEVICE}METHOD FOR FABRICATING FINE PATTERN OF SEMICONDUCTOR DEVICE}

본 발명은 반도체 소자의 제조 기술에 관한 것으로, 특히 반도체 소자의 미세 패턴 제조 방법에 관한 것이다.TECHNICAL FIELD This invention relates to the manufacturing technique of a semiconductor element. Specifically, It is related with the manufacturing method of the fine pattern of a semiconductor element.

반도체 소자의 제조에 있어서, 패턴 사이즈의 감소는 수율 향상을 위해 중요 핵심이 되는 사항이다. 이로 인하여 40nm급 이하의 반도체 소자에서 불화아르곤(ArF) 포토레지스트가 도입되었으나, 이도 점차 높아지는 반도체 소자의 집적도를 만족시키지 못하고 있다. 그래서, 도입된 기술이 SPT(Spacer Patterning Technology)이다.In the manufacture of semiconductor devices, the reduction of the pattern size is an important point for improving the yield. As a result, argon fluoride (ArF) photoresists have been introduced in the semiconductor devices of 40 nm or less, but they also do not satisfy the increasing degree of integration of semiconductor devices. Thus, the introduced technology is SPT (Spacer Patterning Technology).

도 1a 및 도 1b는 종래기술의 SPT에 따른 반도체 소자의 미세패턴 제조 방법을 나타낸 공정단면도이다.1A and 1B are cross-sectional views illustrating a method of manufacturing a fine pattern of a semiconductor device according to a SPT of the related art.

도 1a에 도시된 바와 같이, 기판(11)에 피식각층(12)을 형성하고, 피식각층(12) 상에 복수의 희생막패턴(13)을 형성한다. 이어서, 희생막패턴(13)의 양측에 스페이서(14, spacer)를 형성한다. 이후, 희생막패턴(13)을 제거한다.As shown in FIG. 1A, an etched layer 12 is formed on the substrate 11, and a plurality of sacrificial film patterns 13 are formed on the etched layer 12. Subsequently, spacers 14 are formed on both sides of the sacrificial layer pattern 13. Thereafter, the sacrificial layer pattern 13 is removed.

도 1b에 도시된 바와 같이, 스페이서(14)를 식각장벽으로 피식각층(12)을 식각하여 미세 패터닝된 피식각층패턴(12A)을 형성한다.As shown in FIG. 1B, the etched layer 12 is etched using the spacer 14 as an etch barrier to form a fine patterned etched layer pattern 12A.

그러나, 위와 같은 SPT에서 스페이서(14)의 표면은 경사져(slope) 있어서 상부에 첨점 형상으로 형성되어 있으며, 이를 식각장벽으로 피식각층(12)을 식각할 경우, 스페이서(14)의 경사진 표면으로 인해 식각율(etch rate)차가 발생하며 이에 따라, 스페이서(14)의 첨점 형상이 피식각층패턴(12A)에 전사된다.However, in the SPT as described above, the surface of the spacer 14 is inclined to form a pointed shape at the top, and when the etching layer 12 is etched by the etching barrier, the spacer 14 is inclined to the inclined surface. As a result, an etch rate difference occurs, whereby the point shape of the spacer 14 is transferred to the etched layer pattern 12A.

도 2는 스페이서(14)의 첨점 형상이 피식각층패턴(12A)에 전사된 것을 촬영한 전자현미경 사진이다.FIG. 2 is an electron micrograph photographing the point shape of the spacer 14 transferred to the etched layer pattern 12A.

도 2를 참조하면, (a)에서 스페이서(14)가 첨점 형상을 갖고 있음을 확인할 수 있으며, (b)에서 스페이서(14)를 이용한 식각공정 후의 피식각층패턴(12A)도 첨점 형상인 것을 확인할 수 있다.Referring to FIG. 2, it can be seen that the spacer 14 has a cubic shape in (a), and the etching target layer pattern 12A after the etching process using the spacer 14 in (b) also has a cubic shape. Can be.

이와 같은 스페이서(14) 형상의 전사는 피식각층패턴(12A)의 형상을 불량하게 하여, 피식각층패턴(12A)간의 폭 차이 및 피식각층패턴(12A)의 높이 차를 유발한다.Such transfer of the shape of the spacer 14 makes the shape of the etched layer pattern 12A poor, causing a difference in width between the etched layer patterns 12A and a height difference between the etched layer patterns 12A.

본 발명은 상기한 종래기술의 문제점을 해결하기 위해 제안된 것으로서, 스페이서패턴의 첨점 형상이 피식각층에 전사되는 문제점을 해결하는 반도체 소자의 미세 패턴 제조 방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the above problems of the prior art, and an object of the present invention is to provide a method for manufacturing a fine pattern of a semiconductor device that solves the problem that the cusp shape of the spacer pattern is transferred to the etching target layer.

상기의 목적을 달성하기 위한 본 발명의 반도체 소자의 미세패턴 제조 방법은 피식각층 상에 복수의 제1희생막을 형성하는 단계, 상기 제1희생막의 양측에 스페이서를 형성하는 단계, 상기 스페이서 사이를 채우는 제2희생막을 형성하는 단계, 상기 제1희생막 및 상기 제2희생막의 일부를 식각하여 상기 스페이서의 첨점을 노출시키는 단계, 상기 첨점을 덮는 제3희생막을 형성하는 단계, 상기 제3희생막과 상기 첨점을 제거하는 단계, 상기 제1희생막 및 제2희생막을 제거하는 단계 및 상기 첨점이 제거된 상기 스페이서를 식각장벽으로 피식각층을 식각하는 단계를 포함한다.In order to achieve the above object, a method of manufacturing a micropattern of a semiconductor device of the present invention may include forming a plurality of first sacrificial films on an etched layer, forming spacers on both sides of the first sacrificial film, and filling the spaces between the spacers. Forming a second sacrificial film, etching a portion of the first sacrificial film and the second sacrificial film to expose the peaks of the spacer, forming a third sacrificial film covering the peaks, and the third sacrificial film; Removing the cusp, removing the first sacrificial film and the second sacrificial film, and etching the etched layer using the spacer from which the cusp is removed as an etch barrier.

상술한 바와 같은 과제 해결 수단을 바탕으로 하는 본 발명은 스페이서패턴의 첨점 형상이 피식각층에 전사되는 문제점을 해결하여, 정상적인 형상의 미세한 피식각층패턴을 형성한다.The present invention based on the problem solving means described above solves the problem that the cusp shape of the spacer pattern is transferred to the etched layer, thereby forming a fine etched layer pattern having a normal shape.

따라서, 반도체 소자의 패턴 형상의 신뢰도를 향상시킬 수 있으며, 나아가 수율을 향상시킬 수 있는 효과를 갖는다.Therefore, the reliability of the pattern shape of a semiconductor element can be improved, and also there exists an effect which can improve a yield.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위해 본 발명의 가장 바람직한 실시예를 첨부한 도면을 참조하여 설명한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

도 3a 내지 도 3h는 본 발명의 실시예에 따른 반도체 소자의 미세패턴 제조 방법을 나타낸 공정단면도이다.3A to 3H are cross-sectional views illustrating a method of manufacturing a fine pattern of a semiconductor device according to an exemplary embodiment of the present invention.

도 3a에 도시된 바와 같이, 기판(21) 상에 피식각층(22)을 형성한다.As shown in FIG. 3A, the etched layer 22 is formed on the substrate 21.

피식각층(22)은 산화막, 폴리실리콘막, 질화막, TEOS막, 폴리실리콘막, 질화막이 순차적으로 적층된 박막일 수 있다.The etched layer 22 may be a thin film in which an oxide film, a polysilicon film, a nitride film, a TEOS film, a polysilicon film, and a nitride film are sequentially stacked.

이어서, 피식각층(22) 상에 복수의 제1희생막(23)을 형성한다.Subsequently, a plurality of first sacrificial films 23 are formed on the etched layer 22.

제1희생막(23)은 피식각층(22) 상에 산화막을 증착한 후, 포토레지스트 패턴을 이용한 패터닝 공정을 진행하여 형성한다. 또한, 제1희생막(23)은 DPT(Double Patterning Technology) 공정을 진행하여 형성할 수도 있다.The first sacrificial film 23 is formed by depositing an oxide film on the etched layer 22 and then performing a patterning process using a photoresist pattern. In addition, the first sacrificial layer 23 may be formed by performing a double patterning technology (DPT) process.

도 3b에 도시된 바와 같이, 제1희생막(23)의 양측에 스페이서(24)를 형성한다.As shown in FIG. 3B, spacers 24 are formed on both sides of the first sacrificial film 23.

스페이서(24)는 제1희생막(23)이 형성된 기판의 단차를 따라 폴리실리콘막을 형성한 후, 비등방성 식각 공정을 진행하여 형성한다. 이에 따라 스페이서(24)의 상부 표면은 경사지며 첨점 형상을 갖는다.The spacer 24 is formed by forming a polysilicon film along a step of the substrate on which the first sacrificial film 23 is formed, and then performing an anisotropic etching process. Accordingly, the upper surface of the spacer 24 is inclined and has a pointed shape.

도 3c에 도시된 바와 같이, 상기 제1희생막(23) 및 스페이서(24)를 덮는 제2희생막(25)을 형성한다.As shown in FIG. 3C, a second sacrificial layer 25 covering the first sacrificial layer 23 and the spacer 24 is formed.

제2희생막(25)은 제1희생막(23)과 동일한 박막으로 형성하며, 따라서, 제2희생막(25)은 산화막으로 형성한다.The second sacrificial film 25 is formed of the same thin film as the first sacrificial film 23, and therefore, the second sacrificial film 25 is formed of an oxide film.

도 3d에 도시된 바와 같이, 제2희생막(25)의 일부와 제1희생막(23)의 일부를 식각하여 스페이서(24)의 첨점을 노출시킨다. 이하, 일부가 식각된 제2희생막(25)과 제1희생막(23)의 도면부호를 제2희생막(25A)과 제1희생막(23A)으로 변경 표기한다.As shown in FIG. 3D, a portion of the second sacrificial layer 25 and a portion of the first sacrificial layer 23 are etched to expose the peaks of the spacer 24. Hereinafter, reference numerals of the second and second sacrificial films 25 and 23 that have been partially etched will be referred to as the second and second sacrificial films 25A and 23A.

제2희생막(25A)과 제1희생막(23A)의 형성은 부분 에치백(partial etch back) 공정으로 진행한다. 그리고, 부분 에치백 공정은 스페이서(24)의 첨점 형상이 모두 노출될때까지 진행하는 것이 바람직하다.Formation of the second sacrificial film 25A and the first sacrificial film 23A is performed by a partial etch back process. The partial etch back process is preferably performed until all the cue-shaped shapes of the spacers 24 are exposed.

도 3e에 도시된 바와 같이, 에피택셜 성장(epitaxial growth) 공정을 진행하여 제3희생막(26)을 형성한다.As shown in FIG. 3E, an epitaxial growth process is performed to form a third sacrificial layer 26.

제3희생막(26)은 에피택셜 성장 공정에서 스페이서(24)와 동일 결정성을 가지면서 성장한 박막이기 때문에 스페이서(24)와 동일 성질을 나타낸다. 즉, 스페이서(24)를 폴리실리콘막으로 형성하였기 때문에, 제3희생막(26)도 폴리실리콘막으로 성장된다.Since the third sacrificial film 26 is a thin film grown while having the same crystallinity as the spacer 24 in the epitaxial growth process, the third sacrificial film 26 has the same properties as the spacer 24. That is, since the spacer 24 is formed of the polysilicon film, the third sacrificial film 26 is also grown into the polysilicon film.

도 3f에 도시된 바와 같이, 제3희생막(26)에 대한 평탄화 공정, 예컨대 에치백 또는 화학적기계적연마(Chemical Mechanical Polishing, CMP) 공정을 진행하여 제3희생막(26)과 함께 스페이서(24)의 첨점을 제거한다. 이하, 첨점이 제거된 스페이서(24)의 도면부호를 (24A)로 변경 표기한다.As shown in FIG. 3F, a planarization process for the third sacrificial layer 26 may be performed, for example, an etch back or chemical mechanical polishing (CMP) process, and the spacer 24 may be disposed together with the third sacrificial layer 26. Remove the punctuation of). In the following, reference numerals of the spacers 24 from which the sharp points are removed are referred to as (24A).

이에 따라 스페이서(24A)는 표면이 평탄화되고, 균일한 폭을 갖는 기둥 형상(pillar profile)으로 형성된다. Accordingly, the spacer 24A is flattened and formed into a pillar profile having a uniform width.

도 3g에 도시된 바와 같이, 제2희생막(25A)과 제1희생막(23A)을 제거하여 스페이서(24A)의 측벽을 노출시킨다.As shown in FIG. 3G, the sidewalls of the spacer 24A are exposed by removing the second sacrificial film 25A and the first sacrificial film 23A.

제2희생막(25A)과 제1희생막(23A)의 제거는 습식 딥 아웃(wet dip out)으로 진행하며, 제2희생막(25A)과 제1희생막(23A)을 산화막으로 형성하였는바, BOE(Bufferd Oxide Etchant) 용액 또는 불화수소(HF) 용액을 사용한다.Removal of the second sacrificial film 25A and the first sacrificial film 23A proceeds to a wet dip out, and the second sacrificial film 25A and the first sacrificial film 23A are formed of an oxide film. Bar BOE (Buffered Oxide Etchant) solution or hydrogen fluoride (HF) solution is used.

도 3h에 도시된 바와 같이, 스페이서(24A)를 식각장벽으로 피식각층(22)을 식각하여 미세 패터닝된 피식각층패턴(22A)을 형성한다.As shown in FIG. 3H, the etched layer 22 is etched using the spacer 24A as an etch barrier to form a fine patterned etched layer pattern 22A.

전술한 바와 같은 본 발명의 실시예는, 스페이서(24) 상에 제3희생막(26)을 형성하고, 평탄화 공정을 진행하여 표면이 평탄화되고 균일한 폭의 스페이서(24A)를 형성한다. 이와 같은 스페이서(24A)로 피식각층(22)을 식각하면, 균일 폭, 균일 높이를 갖는 피식각층패턴(22)을 형성할 수 있다.In the embodiment of the present invention as described above, the third sacrificial film 26 is formed on the spacer 24 and the planarization process is performed to form the spacer 24A having a flat surface and a uniform width. When the etching target layer 22 is etched using the spacer 24A, the etching target layer pattern 22 having a uniform width and a uniform height can be formed.

한편, 스페이서(24)의 첨점 형상을 제거하기 위해 플라즈마 산화(plasma oxide) 공정 후 식각공정을 통해 제거하거나, 화학적기계적연마(CMP) 공정을 진행하여 제거할 수도 있다.On the other hand, in order to remove the cusp shape of the spacer 24 may be removed by an etching process after the plasma oxide (plasma oxide) process, or may be removed by a chemical mechanical polishing (CMP) process.

하지만, 플라즈마 산화 공정을 통해 첨점 형상을 제거할 경우, 폴리실리콘막으로 형성된 스페이서 계면에 실리콘산화막이 형성되어 후속 스페이서 식각시 프로 파일이 불량해지는 문제점이 발생한다. 또한, 화학적기계적연마 공정으로 첨점 형상을 제거할 경우, 첨점 형상을 덮지 않고 진행하기 때문에 스페이서가 무너지는 문제점이 발생한다.However, when the point shape is removed through a plasma oxidation process, a silicon oxide film is formed on a spacer interface formed of a polysilicon film, thereby causing a problem in that a profile becomes poor during subsequent spacer etching. In addition, when removing the peak shape by the chemical mechanical polishing process, the spacer is collapsed because the process proceeds without covering the point shape.

그러나, 폴리실리콘막 에피택셜 성장 공정을 이용할 경우, 실리콘산화막의 형성 및 스페이서의 무너짐 현상이 방지되어 공정을 안정성을 향상시킬 수 있다.However, when the polysilicon film epitaxial growth process is used, the formation of the silicon oxide film and the collapse of the spacer may be prevented, thereby improving the process stability.

또한, 제3희생막과 스페이서의 막질이 동일하기 때문에 후속 첨점이 제거된 스페이서 형성시 기본 공정인 자연산화막(native oxide)의 제거 공정을 생략해도 된다.In addition, since the film quality of the third sacrificial film and the spacer is the same, the step of removing the native oxide, which is a basic step in forming a spacer from which subsequent cubits are removed, may be omitted.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

도 1a 및 도 1b는 종래기술의 SPT에 따른 반도체 소자의 미세패턴 제조 방법을 나타낸 공정단면도.1A and 1B are cross-sectional views illustrating a method of manufacturing a fine pattern of a semiconductor device according to the SPT of the prior art.

도 2는 스페이서의 경사진 형상이 피식각층패턴에 전사된 것을 촬영한 전자현미경 사진.2 is an electron micrograph photographing the inclined shape of the spacer transferred to the etched layer pattern.

도 3a 내지 도 3h는 본 발명의 실시예에 따른 반도체 소자의 미세패턴 제조 방법을 나타낸 공정단면도.3A to 3H are cross-sectional views illustrating a method of manufacturing a fine pattern of a semiconductor device in accordance with an embodiment of the present invention.

* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

21 : 기판 22 : 피식각층21 substrate 22 etched layer

23 : 제1희생막 24 : 스페이서23: first sacrificial film 24: spacer

25 : 제2희생막 26 : 제3희생막25: second sacrificial membrane 26: third sacrificial membrane

24A : 첨점이 제거된 스페이서24A: Cucumber-free spacer

Claims (5)

피식각층 상에 복수의 제1희생막을 형성하는 단계;Forming a plurality of first sacrificial films on the etched layer; 상기 제1희생막의 양측에 스페이서를 형성하는 단계;Forming spacers on both sides of the first sacrificial film; 상기 스페이서 사이를 채우는 제2희생막을 형성하는 단계;Forming a second sacrificial layer filling the spacers; 상기 제1희생막 및 상기 제2희생막의 일부를 식각하여 상기 스페이서의 첨점을 노출시키는 단계;Etching portions of the first and second sacrificial films to expose the peaks of the spacers; 상기 첨점을 덮는 제3희생막을 형성하는 단계;Forming a third sacrificial film covering the cusp; 상기 제3희생막과 상기 첨점을 제거하는 단계;Removing the third sacrificial layer and the cusp; 상기 제1희생막 및 제2희생막을 제거하는 단계; 및Removing the first and second sacrificial membranes; And 상기 첨점이 제거된 상기 스페이서를 식각장벽으로 피식각층을 식각하는 단계Etching the layer to be etched using the spacer from which the peaks are removed as an etch barrier 를 포함하는 반도체 소자의 미세패턴 제조 방법.Micropattern manufacturing method of a semiconductor device comprising a. 제1항에 있어서,The method of claim 1, 상기 첨점이 제거된 상기 스페이서는 표면이 평탄하고, 균일한 폭을 갖는 기둥 형상(pillar profile)으로 형성되는 반도체 소자의 미세패턴 제조 방법.The spacer from which the cusp is removed has a flat surface and is formed in a pillar profile having a uniform width. 제1항에 있어서,The method of claim 1, 상기 제3희생막은 에피택셜 성장 공정으로 형성하는 반도체 소자의 미세패턴 제조 방법.The third sacrificial film is a fine pattern manufacturing method of a semiconductor device formed by an epitaxial growth process. 제1항에 있어서,The method of claim 1, 상기 스페이서와 상기 제3희생막은 폴리실리콘막으로 형성하고, 상기 제1희생막과 상기 제2희생막은 산화막으로 형성하는 반도체 소자의 미세패턴 제조 방법.And the spacer and the third sacrificial film are formed of a polysilicon film, and the first and second sacrificial films are formed of an oxide film. 제1항에 있어서,The method of claim 1, 상기 제3희생막과 상기 첨점을 제거하는 단계는 에치백 또는 화학적기계적 연마로 진행하는 반도체의 소자 미세패턴 제조 방법.The removing the third sacrificial layer and the peaks is a method of manufacturing a device micropattern of the semiconductor proceeds by etch back or chemical mechanical polishing.
KR1020080030167A 2008-04-01 2008-04-01 Method for fabricating fine pattern of semiconductor device KR20090104973A (en)

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