KR20090100025A - Manufacturing method for semiconductor array package - Google Patents

Abstract

PURPOSE: A manufacturing method for a semiconductor array package is provided to improve bonding ability of a plating layer while increasing plating cohesive power. CONSTITUTION: A manufacturing method for a semiconductor array package is comprised of the steps: A DFR(dry film photoresist)(20) is formed on the surface the penetration hole in which a reference point is formed on a base of the flat type. More than one penetration hole is formed by performing the first exposure and development process. The DFR is formed on the surface of the base of the flat type in which the penetration hole is formed. The die attach section and pattern formation sections are sectioned by the residual DFR a part is developed among the top surface of the base with the second exposure at least.

Description

MANUFACTURING METHOD FOR SEMICONDUCTOR ARRAY PACKAGE

The present invention relates to a method for manufacturing an array semiconductor package, and more particularly, to fabricate an array semiconductor package suitable for a portable device through ultra-precision multilayer plating, and to create an optimal plating environment to enhance plating adhesion while bonding the bonding surface (Bonder). The present invention relates to a method of manufacturing an array semiconductor package capable of increasing mobility.

1 shows a conventional semiconductor package.

The semiconductor package includes conductive lead frames 1, 2, 3, wires 4 that couple the semiconductor die 5 to various elements of the lead frames 1, 2, 3, and the semiconductor die 5. And a molding compound 6 of plastic or resin capsule for sealing the wire 4.

And the lead frames 1, 2, 3 comprise a die attach pad 1 for receiving the semiconductor die 5, a ring 2 provided adjacent the die attach pad 1 to provide a reference plane, An external connection lead 3.

Such a semiconductor package can be made light and small, and thus can be applied to various portable devices.

However, the conventional semiconductor package has a problem in that an oxide film is generated on the base during base etching in a process of generating a pattern connected through a semiconductor die and a wire, thereby making it difficult to generate a pattern through plating.

In addition, when the pattern is made of copper, there is a problem in that the reliability of the finished product is lowered due to the lack of bonding ability during wire bonding.

The present invention relates to a method for manufacturing an array semiconductor package, comprising: (a) forming a dry film photoresist (DFR) on a surface to form a through hole which is a manufacturing reference point in a flat base and performing a first exposure and development process And then etching to form at least one through hole; (b) forming a DFR on the upper surface of the base having the through hole formed thereon; (c) subjecting at least a portion of the top surface of the base to secondary exposure and development to define die attach regions and pattern forming regions by residual DFR; (d) plating a plating layer on the upper surface of the base to form die pads and patterns with the plating layer partitioned by the DFR; (e) removing the remaining DFR and attaching a die to a die pad; (f) electrically connecting the die and its surrounding patterns through a wire; And (g) molding the die, wire, die pad and pattern; Characterized in that it comprises a.

Preferably, the base is characterized in that made of copper (Cu).

More preferably, the plating layer may include a first layer of gold (Au) material, a second layer of nickel (Ni) material, a third layer of copper (Cu) material, a fourth layer of nickel (Ni) material, and gold ( It is characterized by consisting of a fifth layer of Au) material.

More preferably, the second layer and the fourth layer of nickel (Ni) material has a thickness of 0.5 to 5.0㎛ to prevent the copper migration (Cu Migration) generated in the third layer during wire bonding. do.

More preferably, after step (a), Oxon and H ₂ SO ₄ are contained in the water of the activator to activate the surface of the base to activate the first exposed and developed base. It is characterized by preventing the formation of an oxide film.

More preferably, after step (c), Oxon and H ₂ SO ₄ are contained in the water of the activator to activate the surface of the base by activating the surface of the base to activate the secondary exposure and developed base. It is characterized by preventing the formation of an oxide film.

More preferably, the oxone (Oxone) in the contents of the activation tank is characterized in that it contains 5 to 15%.

More preferably, H ₂ SO ₄ in the contents of the activation tank is characterized in that it contains 1 to 3%.

More preferably, in the step (b), the DFR formed on the upper surface of the base is characterized by using an alkali-resistant ALPHO 702G40 so that there is no damage by the plating solution.

More preferably, in the multilayer plating process, the plating current waveform of the plating facility is supplied as a chopper current during plating of the first layer of gold (Au) material that is soldered with the base during the multilayer plating.

The method for manufacturing an array semiconductor package according to the present invention is to manufacture an array semiconductor package suitable for portable devices through ultra-precision multilayer plating, and to increase the bonding adhesion of the plated surface while enhancing the plating adhesion by creating an optimal plating environment. It can be effective.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

Hereinafter, the present invention provides an array semiconductor package for fabricating an array semiconductor package suitable for a portable device through ultra-precision multilayer plating, and to increase bonding adhesion of a plated surface while enhancing an adhesion by creating an optimal plating environment. The manufacturing method will be described as a preferred embodiment, but the technical idea of the present invention is not limited to this and can be variously implemented by those skilled in the art.

2A to 2I illustrate a manufacturing process of an array semiconductor package according to the present invention.

Figure 2a is a plan view and a cross-sectional view showing a base manufacturing process of the array semiconductor package according to the present invention, Figure 2b is a plan view and a cross-sectional view showing an exposure and development process of the array semiconductor package according to the present invention, Figure 2c according to the present invention 2A is a plan view and a cross sectional view showing a dry film removing process of an array semiconductor package according to the present invention, and FIG. 2E is a die attach process of an array semiconductor package according to the present invention. 2F is a plan view and a cross-sectional view illustrating a wire bonding process of an array semiconductor package according to the present invention, and FIG. 2G is a plan view and a cross-sectional view illustrating a molding process of an array semiconductor package according to the present invention, and FIG. 2H. Array semiconductor package according to the present invention A plan view and a sectional view showing an etching process, Fig 2i is a plan view and a sectional view showing the cutting process of the array semiconductor package according to the present invention.

First, referring to FIG. 2A, the process is a base fabrication process, and a flat base 10 is illustrated as a stiffer in which a semiconductor process is performed.

The base 10 is plated through a subsequent process and functions as a carrier on which chips are mounted. For this purpose, the base 10 has a semiconductor manufacturing reference point in the upper and lower sides along the longitudinal direction as shown in the figure. Through-holes should be formed.

That is, a plurality of regions corresponding to at least one semiconductor die are formed on the base 10, and at least one semiconductor die is mounted in each region.

The base 10 is made of copper (Cu) as a base metal for supporting the die pad 40 and the pattern 50 which will be described later.

Therefore, in order to form such a through hole, a photoresist, which is usually a photoresist, is formed on the base 10 as a whole, the mask is aligned at a position of the through hole, and a primary exposure and development process is performed to perform etching. Through-holes are obtained through the process.

Here, the base 10 preferably has a thickness of 0.127 mm to 0.152 mm.

Next, referring to FIG. 2B, the secondary exposure and development processes are performed on the base 10 described above.

That is, the photoresist, which is usually a photoresist, is formed on the upper surface of the base 10. In this case, the photosensitive material may be a dry film photoresist film having a predetermined thickness. The DFR 20 is used when manufacturing a high density, high density circuit board such as a printed circuit board (PCB) or a lead frame. It is a photosensitive material.

Moreover, the photomask which abbreviate | omitted drawing representation is aligned above the said DFR 20, and the exposure and image development process which obtains only the required part of the DFR 20 by a photomask is performed.

The DFR 20 of the region exposed to light by the secondary development process (hereinafter referred to as the “exposure region”) remains, and plating is performed in the state of the DFR 20 that has undergone such a development process.

At this time, the exposure area | region in which the DFR 20 pattern is not formed is removed by peeling liquid.

Next, referring to FIG. 2C, the process is a multilayer plating process, and the die pad 40 and the pattern 50 described later on the base 10 on which the DFR 20 is formed through the above-described secondary exposure and development processes are described below. In order to form the plating layer 30 is formed.

In this case, as shown in FIG. 4, the first layer 31 of gold (Au) is plated, and the second layer 32 of nickel (Ni) is plated thereon, as shown in FIG. 4. A third layer 33 of copper (Cu) is plated thereon as an inner intermediate layer, a fourth layer 34 of nickel (Ni) material is plated thereon, and a fifth layer of gold (Au) material thereon 35 is plated.

When the multi-layer plating is performed, the wire 70 is bonded to the fifth layer 35, which is the uppermost layer, and the second and fourth layers 32 and 34 of nickel (Ni) material are formed at a high temperature during wire bonding. It has a thickness of 0.5 to 5.0 μm to prevent copper migration generated from the third layer 33 of copper (Cu) material, which is an inner intermediate layer, to prevent falling of the bonded wire 70. .

The thickness of each layer of the plating layer 30 is 25 to 35 μm in the third layer 33, 0.5 to 5.0 μm in the second layer 32 and the fourth layer 33, and the first layer 31 and It is preferable that the 5th layer 35 is 0.3 micrometer.

Next, referring to FIG. 2D, the process is a DFR removing process, in which only the central die pad 40 and the pattern 50 on the side surface of the plating layer 30 are partitioned through the partition wall of the DFR 20. Remove DFR 20 to remain.

Next, referring to FIG. 2E, the process is a die attaching process, in which a die 60 serving as a center of a semiconductor is seated on a center die pad 40. The semiconductor die 60 and the die pad 40 may be bonded through an adhesive.

Next, referring to FIG. 2F, the process is a wire bonding process, and electrically connects the die 60 at the center and the pattern 50 through the wire 70.

At this time, the wire 70 is preferably made of gold (Au) material.

Next, referring to FIG. 2G, the process is a molding process, in which a molding compound 80 is filled with a molding compound 80 through a molding die to package a plastic capsule forming a sheath in a state where a wire bonding operation is completed. The encapsulation work is completed by curing.

In this case, the molding process is encapsulated as a molding compound 80 that forms a sheath in order to sustain the bonding of the wire-bonded semiconductor die 60 and the pattern 50 and the wire and protect them from the outside. (80) is preferably an epoxy molding compound (EMC).

Next, referring to FIG. 2H, the process is a back etching process, and an etching process is performed to remove the base 10 of copper (Cu) material, which is a reinforcing material in which a semiconductor process is performed.

Next, referring to FIG. 2I, the process is a cutting process, which is trimmed into individual packages by cutting means such as saws.

3 shows a state in which the individual array semiconductor package thus completed is mounted on the PCB.

Now, further details of the improvement in the characteristic overall process of the present invention will be described as follows.

In the above-described first exposure and development process, etching is performed using an etching solution FeCl ₃ (for example, a low concentration etching solution) in order to form an etching surface which is a plating portion of the plating layer 30. An oxide film is formed on the surface of the base (10) made of copper (Cu) by FeCl _{3 as shown} in the following formula (1). This oxide film prevents plating on the surface of the base 10.

2FeCl ₃ + Cu → 2FeCl ₂ + CuCl ₂

The CuCl ₂ remains on the copper (Cu) surface of the base 10 to prevent plating growth.

As a result, an oxide film is formed by oxygen (O). Figure 5a (a) shows the results of the SEM (Scanning Electron Microscope) analysis results of the surface analysis of the sample according to the general etching solution (FeCl ₃ ) treatment, (b) is contained in the sample according to the general etching solution (FeCl ₃ ) treatment It shows the result of analysis of Energy Dispersive Spectroscopy (EDS) that analyzes the elements.

As can be seen from the portion indicated by the circle in FIG. 5A (b), oxygen (O) is contained on the surface of the base 10 made of copper (Cu) as a result of etching using a conventional etching solution (FeCl ₃ ). Can be.

The analysis results of FIG. 5A are shown in Table 1 below.

ingredient Weight% Atomic% O K 0.25 0.97 Cu L 99.75 99.03 Sum 100.00 100.00

As can be seen in Table 1, it can be seen that a small amount of oxygen (O), which is an oxide film that prevents plating, remains on the surface of the base 10.

In fact, the oxide film can be removed by alkali electrolytic degreasing, but in the case of alkali degreasing, the above-mentioned DFR 20 cannot be removed because it is strongly alkaline having a pH of 12 or more.

In order to solve this problem, the base 10 is activated as a whole after the above-described first etching process.

In other words, the activation tank is filled with water and oxone (Oxone) and H ₂ SO ₄ is added and diluted with the added chemical to activate the surface of the base 10 using the corresponding activation tank. The result of this activation process is shown in FIG. 5B. Figure 5b (a) shows the SEM analysis results of the surface analysis of the sample according to the activation treatment to add Oxone and H ₂ SO ₄ , (b) represents Oxone and H ₂ SO ₄ The analysis result of EDS which analyzes the element contained in the sample according to the added activation process is shown.

Here, the oxone (Oxone) added to the activation tank is contained 5 to 15%, preferably 10% of oxone (Oxone) is preferably contained. In particular, the oxone (Oxone) is preferably an oxone (Oxone) PS-16.

In addition, H ₂ SO ₄ added to the activation tank is contained 1 to 3%, preferably 2% of H ₂ SO ₄ is preferably contained.

As can be seen by comparing FIG. 5B (B) with FIG. 5A (B), the oxide of the copper (Cu) surface is removed and appears uniformly through the result of etching using a conventional etching process and an additional activation process. have.

The analysis results of FIG. 5B are shown in Table 2 below.

ingredient Weight% Atomic% O K 0.00 0.00 Cu L 100.00 100.00 Sum 100.00 100.00

As can be seen from Table 1, it can be seen that the oxide film which prevents plating from the surface of the base 10 is removed, so that oxygen (O) is not detected.

In addition, as a result of the chemical addition treatment, as shown in (a) of FIG. 5B, the base surface roughness is increased, thereby increasing the adhesion of the plating.

This activation process proceeds to the next step after the above-described primary exposure and development processes, but can also be further processed for the base after the secondary exposure and development processes. That is, by performing the same activation treatment on the base 10 on which the DFR 20 is formed through the secondary exposure and development processes, corrosion of the base surface can be prevented.

On the other hand, in the multilayer plating process performed after the above-described secondary exposure and development processes, the gold (Au), which is a partial layer of the multilayer plating, has an alkaline PH. Therefore, in the plating using the DFR 20, there is a need for a DFR 20 having no damage to the plating solution.

That is, the general DFR 20 has a structure vulnerable to alkali and has a problem in that the structure of the DFR 20 is broken by an alkaline solution such as NaOH and separated into chips.

Therefore, when the gold (Au) plating Alkali-resistant DFR (20) is required, for this purpose adopts the DFR of ALPHO 702G40.

The actually required DFR should be free of damage in the strong alkaline solution by dipping for 60 seconds at PH 12. The test results for the DFR of the ALPHO 702G40 described above are shown in FIG.

Figure 6 (a) is a diagram showing the chemical resistance test results for ALPHO 702G40 DFR alkali-resistant DFR, (b) is a diagram showing the chemical resistance test results for AR340 DFR another alkali resistance DFR.

As shown in the diagram, both DFRs under conditions of PH 12 and a temperature of 60 ° C. show no damage. However, it is judged that the swelling phenomenon occurs in the AR340 DFR under the severe condition of PH12 and the temperature of 120 ° C.

In conclusion, DFR of ALPHO 702G40 of NICHIGO MORTON CO., LTD of Japan is suitable for alkali-resistant DFR 20 which is needed for gold (Au) plating.

Meanwhile, the plating conditions of gold (Au), which is the partial layer 31 to be soldered with the base 10 during the multi-layer plating in the multi-layer plating process performed after the above-described second exposure and development processes, are optimized as follows to improve wettability (SolderAbility). Secure.

Here, the wettability means liquid spreadability on the surface, and the wettability is improved as the contact angle between the surface and the liquid phase is minimized.

Change of various factors (nickel layer thickness, nickel layer roughness, inter-gap distance) affecting the wettability as a control condition when the plating equipment is a LNC power IGBT with a high frequency control method using a DC converter method. As a result of changing the current waveforms to DC, Ripple, and Chopper, the microwave current is the most important factor for wettability, and the thicker the thickness of nickel (Ni) affects the wettability. there was. It was observed here that the roughness (gloss) of nickel (Ni) did not affect soldering.

These results are shown in FIG. FIG. 7A illustrates a non-conformance state of 90% coverage, and FIG. 7B illustrates a 100% coverage state where microwave current is applied.

The present invention described above is capable of various substitutions, modifications, and changes without departing from the spirit of the present invention for those skilled in the art to which the present invention pertains. It is not limited to the drawing.

1 is a view showing a conventional semiconductor package.

2A-2I illustrate a manufacturing process of an array semiconductor package in accordance with the present invention.

3 illustrates an individual array semiconductor package in accordance with the present invention.

4 is a cross-sectional view showing a plating layer according to the present invention.

5 is a view for comparing the experimental results for the etching process according to the present invention with the prior art.

Figure 6 is a view for explaining the chemical resistance test results DFR according to the present invention.

7 is a view for explaining the wettability test results of the plating layer according to the present invention.

Claims (10)

(a) forming a dry film photoresist (DFR) on a surface to form a through hole, which is a manufacturing reference point, in the flat base, and performing etching and performing at least one through hole to develop at least one through hole. ; (b) forming a DFR on the upper surface of the base having the through hole formed thereon; (c) subjecting at least a portion of the top surface of the base to secondary exposure and development to define die attach regions and pattern forming regions by residual DFR; (d) plating a plating layer on the upper surface of the base to form die pads and patterns with the plating layer partitioned by the DFR; (e) removing the remaining DFR and attaching a die to a die pad; (f) electrically connecting the die and its surrounding patterns through a wire; And (g) molding the die, wire, die pad and pattern; Method of manufacturing an array semiconductor package comprising a. The method of claim 1, And the base is made of copper (Cu). The method of claim 1, The plating layer may include a first layer made of gold (Au), a second layer made of nickel (Ni), a third layer made of copper (Cu), a fourth layer made of nickel (Ni), and a material made of gold (Au) The manufacturing method of the array semiconductor package characterized by consisting of five layers. The method of claim 3, wherein The second layer and the fourth layer of the nickel (Ni) material has a thickness of 0.5 to 5.0㎛ to prevent the copper migration (Cu Migration) generated in the third layer during wire bonding of the array semiconductor package Manufacturing method. The method of claim 1, After step (a), Oxygen and H ₂ SO ₄ is included in the water of the activator to activate the first exposure and developed base to activate the surface of the base to prevent the formation of an oxide film on the surface of the array semiconductor package. Manufacturing method. The method of claim 1, After step (c), Oxygen and H ₂ SO ₄ in the water of the activation tank to activate the secondary exposure and developed base to activate the surface of the base to prevent the formation of an oxide film on the base surface of the array semiconductor package Manufacturing method. The method according to claim 5 or 6, Oxon (Oxone) in the content of the activation tank is characterized in that 5 to 15% of the manufacturing method of the array semiconductor package. The method according to claim 5 or 6, Method of manufacturing an array semiconductor package, characterized in that 1 to 3% of H ₂ SO ₄ contained in the activator. The method according to any one of claims 1 to 3, In step (b), DFR formed on the upper surface of the base using an alkali-resistant ALPHO 702G40 so as not to be damaged by the plating solution. The method of claim 3, A method of manufacturing an array semiconductor package, characterized by supplying a plating current waveform of a plating facility as a chopper current when plating a first layer of gold (Au) material that is soldered with a base during multilayer plating.

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