KR20090098194A - Semiconductor device and method of fabricating the same - Google Patents

Abstract

A semiconductor device and method of fabricating the same are provided to improve the refresh property of device by forming a gate electrode including germanium. The fin type active region(230) is defined in the semiconductor substrate including the device isolation structure. The gate electrode is formed on the fin type active region. The gate electrode comprises the laminating structure of the conductive layer and the silicon germanium layer(Si1-xGex) having germanium. The side(230a) of the fin type active region has a higher germanium concentration than the top part(230b) of the fin type active region. The gate electrode comprises the top gate electrode(260) and bottom gate electrode(250). The bottom gate electrode comprises the laminating structure of the p+ poly-crystal silicon germanium layer and p+ polycrystalline silicon layer.

Description

Semiconductor device and method of manufacturing the same

TECHNICAL FIELD The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device including an improved fin transistor and a method for manufacturing the same.

In general, in a fin channel array transistor (FCAT), a fin channel transistor has a fin channel structure in which a tri gate surrounds a channel. The fin channel structure can be manufactured in a three-dimensional structure without deviating significantly from the existing manufacturing technology, and because of its structural characteristics, the gate control is good due to the structural characteristics, so that the short channel effect can be reduced. Can be minimized. In addition, the fin channel structure can lower the channel doping concentration, thereby improving leakage current through the junction region.

However, in the case where the lower gate electrode of the fin channel transistor is formed of a p + polysilicon layer, the work function of such a p + polysilicon layer is larger than that of the p− silicon substrate, so that the fin channel transistor is formed in the drain region in the OFF state. When there is a voltage of 1 "state, the leakage current in the drain region increases due to a gate induced drain leakage (GIDL) phenomenon. Therefore, the data of the "1" state stored in the storage electrode of the DRAM cell is easily lost, and the refresh characteristic of the DRAM is degraded.

According to the present invention, a fin electrode having a fin channel gate structure is formed of a gate electrode including germanium (Ge) so as to have different germanium (Ge) concentrations in the side channel and the upper channel of the fin channel gate structure. By designing a semiconductor device, the GIDL effect can be improved and the refresh characteristics of the device can be improved.

A semiconductor device according to an embodiment of the present invention,

A stacked structure of a fin active region defined in a semiconductor substrate including an isolation structure, a conductive layer having a germanium (Ge) concentration difference, and a silicon germanium layer (Si _{1 - x} Ge _x ) formed on the fin active region It includes a gate electrode including.

And the manufacturing method of the semiconductor element which concerns on this invention is

Forming a device isolation structure defining a fin-type active region protruding from the upper surface of the semiconductor substrate, filling the fin-type active region, and having a germanium (Ge) concentration difference; a silicon germanium layer (Si _{1 - x} Ge _x ) Forming a gate structure comprising a.

According to the present invention, the lower gate electrode of the fin transistor is formed as a stacked structure of a p + polycrystalline silicon layer and a p + polycrystalline germanium layer, thereby increasing the germanium (Ge) concentration in the side channel of the fin channel gate structure than in the upper channel. Therefore, due to the increased germanium (Ge) concentration, there is an effect that the GIDL characteristics of the side channel than the upper channel can be improved. In addition, the germanium (Ge) concentration is present in the upper channel and the side channel, thereby improving the threshold voltage characteristic.

Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

1 is a layout of a semiconductor device illustrating an active region 101, a recess gate region 103, and a gate region 105 defined by an isolation region 120, according to an embodiment of the inventive concept. In addition, below, the longitudinal direction (II-II 'direction) of the gate area | region 105 is defined as a "vertical direction", and the longitudinal direction (I-I' direction) of the active area 101 is defined as a "horizontal direction". The recess gate region 103 is positioned where the gate region 105 overlaps with the recess gate region 103. The line width in the horizontal direction at one side of the recess gate region 103 is shown to be narrower by D than F (0 ≦ D <F / 2). That is, the horizontal line width of the recess gate region 103 is shown by F-2D.

2 is a cross-sectional view illustrating a semiconductor device in accordance with an embodiment of the present invention, FIG. 2 (i) is a cross-sectional view taken along line II ′ of FIG. 1, and FIG. 2 (ii) is a line II-II ′ of FIG. 1. The cross section along the. The gate structure 280 is formed in a stacked structure of the lower gate electrode 250, the upper gate electrode 260, and the gate hard mask layer 270 on the gate insulating layer 240.

In this case, the lower gate electrode 250 has a stacked structure of the first lower gate electrode 242, the second lower gate electrode 244, and the third lower gate electrode 246 to fill the fin type active region 230. It is preferable. In addition, the first lower gate electrode 242 is preferably a p + polycrystalline silicon layer. In addition, the thickness of the first lower gate electrode 242 is preferably 1 to 50 nm. Meanwhile, although the first lower gate electrode 242 of the present invention is implemented with a p + polycrystalline silicon layer, it should be noted that this is only an example for description. Accordingly, the first lower gate electrode 242 may be a conductive layer used as a diffusion buffer layer of germanium (Ge) ions.

In addition, the second lower gate electrode 244 is preferably formed of a silicon layer including germanium (Ge). In particular, the second lower gate electrode 244 is preferably formed of a p + polycrystalline silicon germanium (Si _1-x Ge _x ) layer 244 (where 0 <X <1). In this case, the thickness of the second lower gate electrode 244 is preferably 5 to 100 nm. Meanwhile, germanium (Ge) ions of the second lower gate electrode 244 are diffused into the first lower gate electrode 242, and the germanium (non-uniform) at the interface between the first gate lower electrode 242 and the gate insulating layer 240 is uneven. Ge) distributed in concentration.

When the concentration coefficient X of Ge is constant in the p + polycrystalline silicon germanium (Si _1-x Ge _x ) layer 244, the first lower gate electrode 242 and the first lower gate electrode 242 may be formed according to the thickness of the p + polycrystalline silicon germanium layer 244. The concentration distributed at the interface of the gate insulating film 240 is different. For example, the germanium concentration of the side surface 230a of the fin-shaped active region is preferably larger than the upper portion 230b of the fin-shaped active region.

As a result, the threshold voltage characteristic may be improved due to the germanium concentration distribution located at the interface between the first lower gate electrode 242 and the gate insulating layer 240. Therefore, it is possible to improve the gate induced drain leakage (GIDL) characteristics of the device. In addition, the germanium concentration of the side surface 230a of the fin-type active region is greater than the upper portion 230b of the fin-type active region, thereby improving the threshold voltage characteristic of the side surface, thereby further improving the GIDL characteristics.

The third lower gate electrode 246 is positioned on the second lower gate electrode 244. In addition, the third lower gate electrode 246 is preferably a p + polycrystalline silicon layer. Meanwhile, although the present invention has been implemented as having the third lower gate electrode 246 positioned between the second lower gate electrode 246 and the upper gate electrode 260, it should be noted that the present disclosure is not limited thereto. do. Therefore, according to another exemplary embodiment, the third lower gate electrode 246 may not be formed.

3A to 3G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention. 3A (i) to 3G (i) are cross-sectional views taken along the line II ′ of FIG. 1, and FIGS. 3A (ii) to 3g (ii) are cross-sectional views taken along the line II-II ′ of FIG. 1. After the pad oxide film 312 and the pad nitride film 314 are formed on the semiconductor substrate 310, the pad nitride film 314 photoresist (not shown) is formed. Next, a photoresist film is exposed and developed with an element isolation mask (not shown) to form a photoresist pattern (not shown) defining an element isolation region.

Thereafter, the pad nitride layer 314, the pad oxide layer 312, and the semiconductor substrate 310 are etched by a predetermined thickness using an photoresist pattern to form a trench (not shown) defining the active region 101 of FIG. 1. Remove the photoresist pattern. Next, after forming an isolation layer (not shown) for filling the trench, the isolation layer 320 is formed by planarization etching of the isolation layer until the pad nitride layer 314 is exposed. In this case, the planarization etching process of the insulating layer for device isolation may be performed by a chemical mechanical polishing (CMP) method or an etch-back method.

Referring to FIG. 3B, after the device isolation structure 320 is selectively etched and lowered, the pad nitride layer 314 and the pad oxide layer 312 are removed to expose the semiconductor substrate 310. In this case, the selective etching process for the device isolation structure 320 is preferably performed by a wet etching method. In addition, the removal process of the pad nitride film 314 and the pad oxide film 312 is preferably performed by a wet etching method. Subsequently, after the first oxide film 322 is formed on the exposed semiconductor substrate 310, a photoresist film (not shown) is formed on the semiconductor substrate 310. Subsequently, a photoresist layer is exposed and developed with a mask that exposes a cell region to form a photoresist pattern (not shown).

Next, an ion implantation process is performed using the photoresist pattern as a mask to form a cell and a channel ion implantation region (not shown). After removing the photoresist pattern, the hard mask layer 324 is formed on the semiconductor substrate 310 including the device isolation structure 320. In this case, the hard mask layer 324 may be formed of any one selected from the group consisting of an amorphous carbon film, a polysilicon layer, a nitride film, and a combination thereof.

Referring to FIG. 3C, after forming a photoresist film (not shown) on the hard mask layer 324, the photoresist film is exposed and developed with a recess gate mask (not shown) to expose the recess gate region 103 of FIG. 1. A photosensitive film pattern 326 is defined. Thereafter, the hard mask layer 324 is etched using the photoresist pattern 326 as an etch mask to expose the first oxide layer 322 below. Next, a portion of the device isolation structure 320 is selectively etched to form a recess 332 that exposes the fin active region 330 protruding above the device isolation structure 320. In this case, it is preferable to expose the fin type active region 330 by simultaneously removing the exposed first oxide layer 322 when the device isolation structure 320 is etched.

Referring to FIG. 3D, a soft etching process is performed on the semiconductor substrate 310 exposed to the recess 332 to round the surfaces of the semiconductor substrate 310 and the fin active region 330 exposed in the recess 332. Make. In this case, the soft etching process is preferably performed by an isotropic etching method. Next, after the impurity ions are implanted into the semiconductor substrate 310 having the rounded surface and the fin type active region 330 to form a threshold voltage ion implantation region (not shown), the photoresist pattern 326 and the hard mask layer ( 324). Thereafter, the first oxide film 322 is removed to expose the semiconductor substrate 310. In addition, the removal process for the first oxide film 322 is preferably performed by a wet etching method.

Referring to FIG. 3E, a gate insulating layer 340 is formed on an upper surface of the exposed semiconductor substrate 310 including the fin type active region 330. Next, a first lower gate conductive layer 342 is formed on the gate insulating layer 340. In this case, the first lower gate conductive layer 342 is preferably a p + polycrystalline silicon layer. In addition, the thickness of the first lower gate conductive layer 342 is preferably 1 to 50 nm. Thereafter, the second lower gate conductive layer 344 is formed on the first lower gate conductive layer 342 to fill the fin type active region 330, and then, until the first lower gate conductive layer 342 is exposed. The second lower gate conductive layer 344 is planarized etched. In this case, the planarization etching process of the second lower gate conductive layer 344 may be performed by a CMP method or an etch-back method.

In this case, the second lower gate conductive layer 344 remains only on the side surfaces 330a and the upper portion 330b of the fin type active region among the active regions. In addition, the second lower gate conductive layer 344 may be formed of a silicon layer including germanium (Ge). In particular, the second lower gate conductive layer 344 is preferably formed of a p + polycrystalline silicon germanium (Si _{1 - x} Ge _x ) layer, provided that 0 <X <1. In this case, it is preferable that the p + polycrystalline silicon germanium (Si _{1 - x} Ge _x ) layer is formed by depositing silane (SiH ₄ ) and germanium (GeH ₄ ) as a source gas. Although the second lower gate conductive layer 344 of the present invention is implemented to be formed by the deposition process using the source gas as described above, it should be noted that this is not limited thereto.

In addition, the thickness of the second lower gate conductive layer 344 is preferably 5 to 100 nm. Meanwhile, germanium (Ge) ions of the second lower gate conductive layer 344 are diffused into the first lower gate conductive layer 342 and are uneven at the interface between the first gate lower conductive layer 342 and the gate insulating layer 340. It is distributed at one germanium (Ge) concentration. In addition, when the concentration coefficient X of Ge in the p + polycrystalline silicon germanium (Si _1-x Ge _x ) layer is constant, the first lower gate conductive layer 342 and the gate insulating layer 340 according to the thickness of the p + polycrystalline silicon germanium layer. The concentration distributed at the interface of is different. For example, the germanium concentration of the side surface 330a of the fin-shaped active region is greater than the top 330b of the fin-shaped active region. Meanwhile, although the first lower gate conductive layer 342 of the present invention is implemented with a p + polycrystalline silicon layer, it should be noted that this is only an example for description. Accordingly, the first lower gate conductive layer 342 may be a conductive layer used as a diffusion buffer layer of germanium (Ge) ions.

Referring to FIG. 3F, a third lower gate conductive layer 346 is formed on the second lower gate conductive layer 344 to include a lower gate including a stacked structure of a conductive layer and a silicon germanium layer (Si _{1 - x} Ge _x ). The conductive layer 350 is formed. In this case, the third lower gate conductive layer 346 is preferably a p + polycrystalline silicon layer. Meanwhile, although the present invention has been implemented as having the third lower gate conductive layer 346 positioned between the second lower gate conductive layer 346 and the upper gate conductive layer 360, the present disclosure is not limited thereto. Be careful. For example, according to another exemplary embodiment, the third lower gate conductive layer 346 may not be formed.

Next, an upper gate conductive layer 360 and a gate hard mask layer 370 are formed on the lower gate conductive layer 350. In this case, the upper gate conductive layer 360 may include a titanium nitride (TiN) layer, a tungsten nitride (WN) layer, a tungsten (W) layer, a titanium (Ti) layer, a cobalt (Co) layer, a titanium silicide (TiSi _x ) layer, It is preferable to form one selected from the group consisting of a tungsten silicide (WSi _x ) layer, a cobalt silicide (CoSi _x ) layer, and a combination thereof.

Referring to FIG. 3G, after the photoresist film (not shown) is applied on the gate hard mask layer 370, the photoresist film is exposed and developed with a mask defining the gate region 105 of FIG. 1 to expose the photoresist pattern (not shown). To form. Next, the gate hard mask layer 370, the upper gate conductive layer 360, and the lower gate conductive layer 350 are patterned using the photoresist pattern as an etch mask to form the gate structure 380, and then the photoresist pattern is removed. . Thereafter, an ion implantation process is performed to form a storage electrode junction region (not shown) and a bit line junction region (not shown) used as the LDD region and the source / drain region.

After the process, the gate sidewall insulating film forming process, the landing plug forming process, the bit line contact and the bit line forming process, the capacitor contact and the capacitor forming process, the metal wiring contact and the metal wiring forming process can be performed like the normal transistor forming process. have. In addition, although the present invention as described above is described according to a preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not limitation.

4A to 4C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with another embodiment of the present invention. In particular, FIGS. 4A to 4C are cross-sectional views illustrating a method of manufacturing a semiconductor device for forming FIGS. 3E to 3G. A gate insulating layer 440 is formed on the exposed upper surface of the semiconductor substrate 410 including the fin type active region 430. Next, a first lower gate conductive layer 442 is formed on the gate insulating layer 440. In this case, the first lower gate conductive layer 442 is preferably a p + polycrystalline silicon layer. In addition, the thickness of the first lower gate conductive layer 442 is preferably 1 to 50 nm.

Thereafter, the second lower gate conductive layer 444 is formed on the first lower gate conductive layer 442 to fill the fin type active region 430. In this case, the second lower gate conductive layer 444 may be formed of a silicon layer including germanium (Ge). In particular, the second lower gate conductive layer 444 is preferably formed of a p + polycrystalline silicon germanium (Si _{1 - x} Ge _x ) layer (where 0 <X <1). The thickness of the second lower gate conductive layer 444 is preferably 5 to 100 nm. The thickness of the first lower gate conductive layer 442 is relatively smaller than that of the second lower gate conductive layer 444, so that germanium (Ge) is uneven at an interface between the first lower gate conductive layer 442 and the gate insulating layer 440. Have a concentration distribution (see description of FIG. 3E).

Referring to FIG. 4B, after the third lower gate conductive layer 446 is formed on the second lower gate conductive layer 444, the third lower gate conductive layer 446 is flattened and etched. In this case, the planarization etching process of the third lower gate conductive layer 446 may be performed by a CMP method or an etch-back method. In addition, the third lower gate conductive layer 446 is formed to form the lower gate conductive layer 450 including a stacked structure of the conductive layer and the silicon germanium layer (Si _{1 - x} Ge _x ). Meanwhile, although the present invention has been implemented as having the third lower gate conductive layer 446 positioned between the second lower gate conductive layer 446 and the upper gate conductive layer 460, the present invention is not limited thereto. Be careful. For example, according to another exemplary embodiment, the third lower gate conductive layer 446 may not be formed.

Next, an upper gate conductive layer 460 and a gate hard mask layer 470 are formed on the lower gate conductive layer 450. In this case, the upper gate conductive layer 460 may include a titanium nitride (TiN) layer, a tungsten nitride (WN) layer, a tungsten (W) layer, a titanium (Ti) layer, a cobalt (Co) layer, a titanium silicide (TiSi _x ) layer, It is preferable to form one selected from the group consisting of a tungsten silicide (WSi _x ) layer, a cobalt silicide (CoSi _x ) layer, and a combination thereof.

Referring to FIG. 4C, after the photoresist film (not shown) is applied on the gate hard mask layer 470, the photoresist film is exposed and developed with a mask defining the gate region 105 of FIG. 1 to expose the photoresist pattern (not shown). To form. Next, the gate hard mask layer 470, the upper gate conductive layer 460, and the lower gate conductive layer 450 are patterned using the photoresist pattern as an etch mask to form the gate structure 480, and then the photoresist pattern is removed. . Thereafter, an ion implantation process is performed to form a storage electrode junction region (not shown) and a bit line junction region (not shown) used as the LDD region and the source / drain region. On the other hand, the present invention as described above is described in accordance with a preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not limitation.

FIG. 5 is an experimental diagram illustrating a work function difference between a p + polycrystalline silicon layer according to germanium concentration (X) in a p + polycrystalline silicon germanium (Si _{1 - x} Ge _x ) layer, and “IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol. 47, No. 4, April, 2000, pp 848-855 ". If the germanium (Ge) molecular concentration (X) is zero (i.e., X = 0), the p + polycrystalline silicon germanium (Si _{1 -x} Ge _x ) layer is a p + polycrystalline silicon layer and the work function difference from the p + polycrystalline silicon layer is different. No difference can be seen as the germanium concentration (X) increases.

In addition, the preferred embodiment of the present invention as described above is for the purpose of illustration, those skilled in the art will be possible to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are as follows It should be regarded as belonging to the claims.

1 is a layout of a semiconductor device in accordance with an embodiment of the present invention.

2 is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

3A to 3G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

4A to 4C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with another embodiment of the present invention.

5 is an experimental diagram showing the difference in work function with the p + polycrystalline silicon layer in accordance with the germanium concentration (X) in the p + polycrystalline silicon germanium (Si _{1 - x} Ge _x ) layer.

<Explanation of symbols for the main parts of the drawings>

101: active region 103: recess gate region

105: gate region 120: device isolation region

230: finned active region 230a: side of finned active region

230b: upper part 240 of a fin type active region 240: gate insulating film

242: first lower gate electrode 244: second lower gate electrode

246: third lower gate electrode 250: lower gate electrode

260: upper gate electrode 270: gate hard mask layer

280: gate structure 310: semiconductor substrate

312: pad oxide film 314: pad nitride film

320: device isolation structure 322: first oxide film

324: Hard mask layer 326: Photosensitive film pattern

330: finned active region 330a: side of finned active region

330b: upper portion 332 of the finned active region: recess

340: gate insulating film 342: first lower gate conductive layer

344: second lower gate conductive layer 346: third lower gate conductive layer

350: lower gate conductive layer 360: upper gate conductive layer

370: gate hard mask layer 380: gate structure

410: semiconductor substrate 430: fin type active region

440: gate insulating layer 442: first lower gate conductive layer

444: second lower gate conductive layer 446: third lower gate conductive layer

450: lower gate conductive layer 460: upper gate conductive layer

470: gate hard mask layer 480: gate structure

Claims (18)

A fin type active region defined in a semiconductor substrate including a device isolation structure; And A semiconductor device formed on the fin active region and including a gate electrode including a stacked structure of a conductive layer having a germanium (Ge) concentration difference and a silicon germanium layer (Si _{1 - x} Ge _x ), provided that 0 < X <1, X is germanium concentration). The method of claim 1, And a side surface of the fin type active region has a greater germanium concentration than an upper portion of the fin type active region. The method of claim 1, The gate electrode may include an upper gate electrode and a lower gate electrode, and the lower gate electrode may include a stacked structure of a p + polycrystalline silicon layer and a p + polycrystalline silicon germanium layer. The method of claim 3, The lower gate electrode may include a stacked structure of a first p + polycrystalline silicon layer, a p + polycrystalline silicon germanium layer (Si _{1 - x} Ge _x ), and a second p + polycrystalline silicon layer. The method of claim 4, wherein The thickness of the first p + polycrystalline silicon layer is a semiconductor device, characterized in that 1 to 50 nm. The method of claim 3, The first p + polycrystalline silicon germanium layer has a thickness of 5 to 100 nm, characterized in that the semiconductor device. The method of claim 1, And a recess formed in the fin type active region. Forming a device isolation structure defining a fin-shaped active region protruding from the semiconductor substrate; A method of manufacturing a semiconductor device, including forming a gate structure including a silicon germanium layer (Si _{1 - x} Ge _x ) to fill the fin-type active region and have a germanium (Ge) concentration difference. X <1, X is germanium concentration). The method of claim 8, The fin type active region forming step Forming an isolation region on the semiconductor substrate to form an active region; Forming a hard mask layer on the semiconductor substrate; Forming a photoresist pattern defining a recess gate region on the hard mask layer; Selectively etching the hard mask layer and a portion of the device isolation structure using the photoresist pattern as an etch mask to protrude the active region over the device isolation structure; And And removing the photoresist pattern and the hard mask layer to expose the active region including the fin type active region. The method of claim 9, The method of manufacturing a semiconductor device, characterized in that the depth of the etched device isolation structure is 50 to 300nm. The method of claim 9, And forming a recess by etching a portion of the fin-type active region during the selective etching process. The method of claim 11, And a depth of the etched fin-type active region is D (where 0 <D ≦ 200nm). The method of claim 9, And performing a soft etching process on the exposed active region. The method of claim 8, The gate structure forming step Forming a lower gate conductive layer including the silicon germanium layer (Si _{1 - x} Ge _x ) on the semiconductor substrate; Forming an upper gate conductive layer and a gate hard mask layer on the lower gate conductive layer; And Patterning the gate hard mask layer, the upper gate conductive layer, and the lower gate conductive layer. The method of claim 14, The lower gate conductive layer forming step Forming a p + polycrystalline silicon layer on the semiconductor substrate; And Forming a p + polycrystalline silicon germanium layer on the p + polycrystalline silicon layer to bury the fin-type active region. The method of claim 15, And planarizing etching the p + polycrystalline silicon layer until the fin-type active region is exposed. The method of claim 15, And forming a second p + polycrystalline silicon layer on the p + polycrystalline silicon germanium layer. The method of claim 8, And forming a gate insulating film over the active region including the fin type active region.

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