KR20090096878A - Method of forming metal line in semiconductor device - Google Patents

Method of forming metal line in semiconductor device Download PDF

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KR20090096878A
KR20090096878A KR1020080021954A KR20080021954A KR20090096878A KR 20090096878 A KR20090096878 A KR 20090096878A KR 1020080021954 A KR1020080021954 A KR 1020080021954A KR 20080021954 A KR20080021954 A KR 20080021954A KR 20090096878 A KR20090096878 A KR 20090096878A
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film
hard mask
metal wiring
metal
etching
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KR1020080021954A
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Korean (ko)
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길민철
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

A method of forming metal line in a semiconductor device is provided to increase the uniformity of a metal wire pattern and reduce a defect of the semiconductor device by etching a metal barrier film formed on the metal wire excessively. In a method of forming metal line in a semiconductor device, an interlayer insulating film(101), a metal wiring film(103), a barrier film(102), a hard mask film are laminated in successively on the semiconductor substrate(100). The hard mask film and the barrier film are etched and the metal wiring film is exposed to the outside, and an exposed metal wiring film is etched and the metal wiring is formed. The first, second, and third hard mask films(105,106) are laminated on the hard mask film.

Description

반도체 소자의 금속배선 형성 방법{Method of forming metal line in semiconductor device}Method of forming metal line in semiconductor device

본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 특히 금속 배선 물질의 거칠기에 상관없이 일정한 패턴으로 식각할 수 있는 반도체 소자의 금속배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices, and more particularly, to a method for forming metal wirings in semiconductor devices that can be etched in a predetermined pattern irrespective of the roughness of metal wiring materials.

반도체 소자를 이루는 단위 소자(예컨대, 트랜지스터, 캐패시터) 및 전도라인(예컨대, 비트라인, 워드라인) 등에 전원을 공급하기 위하여 금속배선을 사용하고 있다. 반도체 소자의 고집적화에 따라 금속배선의 선폭은 갈수록 축소되고 있다.Metal wiring is used to supply power to unit devices (eg, transistors, capacitors) and conduction lines (eg, bit lines and word lines) constituting semiconductor devices. As the semiconductor devices become more integrated, the line width of metal wirings is gradually decreasing.

또한 일반적으로 반도체 소자 중 플래시 메모리 소자의 비트라인 이루는 금속 배선은 알루미늄으로 형성하는데, 이때 형성되는 금속 배선의 두께는 1000Å 이하로 형성하게 되므로 알루미늄의 상부 거칠기에 심화되어 금속 배선의 두께가 일정치 않게 형성된다.In general, the metal wirings that make up the bit lines of the flash memory devices of the semiconductor devices are formed of aluminum. In this case, since the thickness of the metal wirings is formed to be 1000 Å or less, the thickness of the metal wirings is increased due to the roughness of the upper part of the aluminum. Is formed.

이는 후속 형성되는 베리어막, 하드 마스크막등에 영향을 주게 된다.This affects subsequent barrier films, hard mask films, and the like.

도 1은 종래 기술에 따른 금속 배선 식각 공정의 문제점을 보여주는 소자의 공정 사진이다.1 is a process picture of a device showing a problem of a metal wiring etching process according to the prior art.

도 1을 참조하게 되면, 알루미늄막의 거칠기로 인하여 알루미늄 상에 형성된 막들의 두께가 일정치 않아 하드 마스크 패터닝 공정시 식각 로스(loss)량 및 하드 마스크 패턴 측벽의 경사도가 서로 다르게 된다.Referring to FIG. 1, due to the roughness of the aluminum film, the thicknesses of the films formed on the aluminum are not constant, so that the amount of etch loss and the inclination of the sidewalls of the hard mask pattern are different during the hard mask patterning process.

이는 하드 마스크 패턴을 이용한 알루미늄막 식각 공정시 패턴의 불균일성을 초래하고 심각할 경우 인접한 금속 배선가 접촉되는 브릿지 현상을 유발할 수 있다.This may cause a non-uniformity of the pattern during the etching process of the aluminum film using the hard mask pattern, and in severe cases, may cause a bridge phenomenon in which adjacent metal wires contact each other.

본 발명이 이루고자 하는 기술적 과제는 금속 배선 형성 공정시, 하드 마스크막 패터닝을 위한 식각 공정을 금속 배선 상부에 형성된 금속 베리어막까지 과도 식각함으로써, 하드 마스크 패턴을 균일하게 형성하여 금속 배선 패턴의 균일성을 증가시켜 소자의 불량을 감소시킬 수 있는 반도체 소자의 금속 배선 형성 방법을 제공하는 데 있다.The technical problem to be achieved by the present invention is to over-etch the etching process for hard mask film patterning to the metal barrier film formed on the upper portion of the metal wiring during the metal wiring formation process, thereby uniformly forming the hard mask pattern to uniformity of the metal wiring pattern To provide a method for forming a metal wiring of the semiconductor device that can reduce the defect of the device by increasing the.

본 발명의 일실시 예에 따른 반도체 소자의 금속 배선 형성 방법은 반도체 기판 상에 층간 절연막, 금속 배선막, 베리어막, 하드 마스크막을 순차적으로 적층하여 형성하는 단계와, 상기 하드 마스크막 및 상기 베리어막을 식각하여 상기 금속 배선막을 노출시키는 단계, 및 노출되는 상기 금속 배선막을 식각하여 금속 배선을 형성하는 단계를 포함한다.According to an embodiment of the present invention, a method of forming a metal wiring of a semiconductor device may be performed by sequentially stacking an interlayer insulating film, a metal wiring film, a barrier film, and a hard mask film on a semiconductor substrate, and forming the hard mask film and the barrier film. Etching to expose the metal interconnection film, and etching the exposed metal interconnection film to form a metal interconnection.

상기 하드 마스크막은 제1 내지 제3 하드 마스크막이 적층된 구조로 형성한다. 상기 제1 및 제3 하드 마스크막은 산화질화막(SiON)으로 형성하며, 상기 제2 하드 마스크막은 비정질 카본막으로 형성한다.The hard mask layer may have a structure in which first to third hard mask layers are stacked. The first and third hard mask films are formed of an oxynitride film (SiON), and the second hard mask films are formed of an amorphous carbon film.

상기 금속 배선막은 알루미늄으로 형성한다.The metal wiring film is made of aluminum.

상기 하드 마스크막 및 상기 베리어막을 식각하는 단계는 식각 공정은 Cl2 가스와 CHF3 가스를 이용하여 실시하며, 상기 Cl2 가스와 상기 CHF3 가스의 유량비는 10: 1 내지 20: 1로 제어하는 것이 바람직하다.Etching the hard mask layer and the barrier film is an etching process is Cl 2 gas and and carried out using a CHF 3 gas flow rate of the Cl 2 gas and the CHF 3 gas is 10: controlled to 1: 1 to 20 It is preferable.

상기 하드 마스크막 및 상기 베리어막을 식각하는 단계와 상기 금속 배선을 형성하는 단계는 동일한 식각 장비를 이용하여 인 시튜(in-situ) 방식을 이용하여 실시한는 것이 바람직하다.Etching the hard mask layer and the barrier layer and forming the metal line may be performed using an in-situ method using the same etching equipment.

본 발명의 일실시 예에 따르면, 금속 배선 형성 공정시, 하드 마스크막 패터닝을 위한 식각 공정을 금속 배선 상부에 형성된 금속 베리어막까지 과도 식각함으로써, 하드 마스크 패턴을 균일하게 형성하여 금속 배선 패턴의 균일성을 증가시켜 소자의 불량을 감소시킬 수 있다.According to an embodiment of the present invention, during the metal wiring formation process, the etching process for hard mask film patterning is excessively etched to the metal barrier film formed on the metal wiring, thereby uniformly forming the hard mask pattern to uniform the metal wiring pattern. Increasing the properties can reduce the defect of the device.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 설명하기로 한다. 그러나, 본 발명은 이하에서 개시되는 실시예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 수 있으며, 본 발명의 범위가 다음에 상술하는 실시예에 한정되는 것은 아니다. 단지 본 실시예는 본 발명의 개시가 완전하도록 하며 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이며, 본 발명의 범위는 본원의 특허청구범위에 의해서 이해되어야 한다.Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

도 2a 내지 도 2e는 본 발명의 일실시 예에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 소자의 단면도 및 공정 사진이다.2A to 2E are cross-sectional views and process pictures of devices for describing a method for forming metal wires of a semiconductor device according to an embodiment of the present invention.

도 2a를 참조하면, 하부 공정(소자 분리 공정, 게이트 형성 공정, 하부 콘택 형성 공정 등)이 완료된 반도체 기판(100) 상에 층간 절연막(101), 하부 베리어막(102), 금속 배선막(103), 상부 베리어막(104), 및 제1 내지 제3 하드 마스크막(105, 106, 107)을 형성한다. 이 후, 제3 하드 마스크막(107) 상에 반사 방지막(108) 및 포토 레지스트 패턴(109)을 형선한다.Referring to FIG. 2A, an interlayer insulating film 101, a lower barrier film 102, and a metal wiring film 103 are formed on a semiconductor substrate 100 on which lower processes (element isolation process, gate formation process, lower contact formation process, etc.) are completed. ), The upper barrier film 104, and the first to third hard mask films 105, 106, and 107 are formed. Thereafter, the antireflection film 108 and the photoresist pattern 109 are shaped on the third hard mask film 107.

층간 절연막(101)은 산화막으로 형성하는 것이 바람직하다. 금속 배선막(103)은 알루미늄막으로 형성하는 것이 바람직하다. 제1 내지 제3 하드 마스크막(105, 106, 107)은 각각 산화질화막(SiON), 비정질 카본막, 및 산화질화막을 이용하여 형성하는 것이 바람직하다.The interlayer insulating film 101 is preferably formed of an oxide film. The metal wiring film 103 is preferably formed of an aluminum film. The first to third hard mask films 105, 106, and 107 are preferably formed using an oxynitride film (SiON), an amorphous carbon film, and an oxynitride film, respectively.

도 2b를 참조하면, 포토 레지스트 패턴을 이용한 식각 공정을 실시하여 반사 방지막, 제3 하드 마스크막(107), 및 제2 하드 마스크막(106)을 식각하여 제1 하드 마스크막(105)을 노출시킨다.Referring to FIG. 2B, an anti-reflection film, a third hard mask film 107, and a second hard mask film 106 are etched by performing an etching process using a photoresist pattern to expose the first hard mask film 105. Let's do it.

이 후, 스트립 공정을 실시하여 포토 레지스트 패턴 및 반사 방지막을 제거한다.Thereafter, a strip process is performed to remove the photoresist pattern and the antireflection film.

도 2c를 참조하면, 제3 하드 마스크막, 및 제2 하드 마스크막(106)을 이용한 식각 공정을 실시하여 제1 하드 마스크막(105), 및 상부 베리어막(104)을 식각한다. 상술한 식각 공정시 제3 하드 마스크막은 제거되며, 제2 하드 마스크막(106)은 소정 두께 소실될 수 있다. 식각 공정은 Cl2 가스와 CHF3 가스를 이용하여 실시하며, Cl2 가스와 CHF3 가스의 유량비는 10: 1 내지 20: 1로 제어하는 것이 바람직하다. 이로 인하여 금속 배선(103)의 식각 손상을 최소화한다.Referring to FIG. 2C, an etching process using the third hard mask layer and the second hard mask layer 106 is performed to etch the first hard mask layer 105 and the upper barrier layer 104. The third hard mask layer may be removed during the etching process, and the second hard mask layer 106 may be lost to a predetermined thickness. It is preferably controlled to 1: 1 to 20: etching process flow ratio of Cl 2 gas and 10 and carried out using CHF 3 gas, Cl 2 gas and CHF 3 gas. This minimizes the etching damage of the metal wiring 103.

상부 베리어막(104)을 식각하여 금속 배선막(103)을 노출함으로써, 후속 금속 배선을 형성하기 위한 식각 공정시 타겟 확보가 유리하며, 상대적으로 버티컬한 제2 하드 마스크막(106)의 측벽을 형성할 수 있다.By etching the upper barrier layer 104 to expose the metal interconnection layer 103, it is advantageous to secure a target during an etching process for forming a subsequent metal interconnection, and the sidewall of the second vertical hard mask layer 106 that is relatively vertical is formed. Can be formed.

도 2d는 도 2c에 도시된 공정을 실제 진행한 소자의 사진이다. 도 2d를 참조하면, 식각 공정시 상부 베리어막을 식각하여 금속 배선막을 노출시킴으로 종래에 상부 베리어막의 로스량의 변화에 따른 후속 식각 공정시의 패턴 변화를 억제할 수 있다. 즉, 금속 배선막부터 동일하게 식각하여 타겟 부족에 의해 금속 배선이 잔류하는 것을 방지하여 금속 배선들 사이의 공간에 도전 물질이 잔류하는 브릿지 현상을 방지할 수 있다.FIG. 2D is a photograph of a device in which the process shown in FIG. 2C is actually performed. Referring to FIG. 2D, the upper barrier layer is etched during the etching process to expose the metal wiring layer, thereby changing the pattern during the subsequent etching process according to the change of the loss amount of the upper barrier layer. That is, since the metal wiring film is etched in the same manner to prevent the metal wiring from remaining due to the lack of a target, the bridge phenomenon in which the conductive material remains in the space between the metal wirings can be prevented.

도 2e를 참조하면, 노출되는 금속 배선막(103) 및 하부 베리어막(102)을 식각하여 금속 배선을 형성한다. 이때, 금속 배선막(103)이 노출되어 있어 식각 타겟의 확보가 용이하며, 이로 인하여 식각 공정시 금속 배선막(103)의 패시베이션(passivation)을 위한 추가적인 가스 사용 제한을 받지 않게 된다. 상술한 식각 공정은 도 2c의 실시된 식각 공정(제1 하드 마스크막 및 상부 베리어막 식각 공정)과 동일한 식각 장비를 이용하여 인 시츄(in-situ) 방식으로 진행하는 것이 바람직하다.Referring to FIG. 2E, the exposed metal wiring film 103 and the lower barrier film 102 are etched to form metal wires. In this case, since the metal wiring layer 103 is exposed, it is easy to secure an etch target, and thus, the use of additional gas for passivation of the metal wiring layer 103 is not limited during the etching process. The etching process described above is preferably performed in-situ using the same etching equipment as the etching process (the first hard mask layer and the upper barrier layer etching process) of FIG. 2C.

이 후, 제2 및 제1 하드 마스크막(106, 105)을 제거하는 공정을 더 실시한다.Thereafter, a step of removing the second and first hard mask films 106 and 105 is further performed.

도 1은 종래 기술에 따른 금속 배선 식각 공정의 문제점을 보여주는 소자의 공정 사진이다.1 is a process picture of a device showing a problem of a metal wiring etching process according to the prior art.

도 2a 내지 도 2e는 본 발명의 일실시 예에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 소자의 단면도 및 공정 사진이다.2A to 2E are cross-sectional views and process pictures of devices for describing a method for forming metal wires of a semiconductor device according to an embodiment of the present invention.

<도면의 주요 부분에 대한 부호 설명><Description of Signs for Main Parts of Drawings>

100 : 반도체 기판 101 : 층간 절연막100 semiconductor substrate 101 interlayer insulating film

102 : 하부 베리어막 103 : 금속 배선막102: lower barrier film 103: metal wiring film

104 : 상부 베리어막 105 : 제1 하드 마스크막104: upper barrier film 105: first hard mask film

106 : 제2 하드 마스크막 107 : 제3 하드 마스크막106: second hard mask film 107: third hard mask film

108 : 반사 방지막 109 : 포토 레지스트 패턴108: antireflection film 109: photoresist pattern

Claims (7)

반도체 기판 상에 층간 절연막, 금속 배선막, 베리어막, 하드 마스크막을 순차적으로 적층하여 형성하는 단계;Sequentially forming an interlayer insulating film, a metal wiring film, a barrier film, and a hard mask film on the semiconductor substrate; 상기 하드 마스크막 및 상기 베리어막을 식각하여 상기 금속 배선막을 노출시키는 단계; 및Etching the hard mask layer and the barrier layer to expose the metal wiring layer; And 노출되는 상기 금속 배선막을 식각하여 금속 배선을 형성하는 단계를 포함하는 반도체 소자의 금속 배선 형성 방법.And forming a metal wiring by etching the exposed metal wiring film. 제 1 항에 있어서,The method of claim 1, 상기 하드 마스크막은 제1 내지 제3 하드 마스크막이 적층된 반도체 소자의 금속 배선 형성 방법.The hard mask film is a metal wiring forming method of a semiconductor device in which the first to third hard mask film is laminated. 제 2 항에 있어서,The method of claim 2, 상기 제1 및 제3 하드 마스크막은 산화질화막(SiON)으로 형성하는 반도체 소자의 금속 배선 형성 방법.And the first and third hard mask layers are formed of an oxynitride layer (SiON). 제 2 항에 있어서,The method of claim 2, 상기 제2 하드 마스크막은 비정질 카본막으로 형성하는 반도체 소자의 금속 배선 형성 방법.And the second hard mask film is formed of an amorphous carbon film. 제 1 항에 있어서,The method of claim 1, 상기 금속 배선막은 알루미늄으로 형성하는 반도체 소자의 금속 배선 형성 방법.And the metal wiring film is formed of aluminum. 제 1 항에 있어서,The method of claim 1, 상기 하드 마스크막 및 상기 베리어막을 식각하는 단계는 식각 공정은 Cl2 가스와 CHF3 가스를 이용하여 실시하며, 상기 Cl2 가스와 상기 CHF3 가스의 유량비는 10: 1 내지 20: 1로 제어하는 반도체 소자의 금속 배선 형성 방법.Etching the hard mask layer and the barrier film is an etching process is Cl 2 gas and and carried out using a CHF 3 gas flow rate of the Cl 2 gas and the CHF 3 gas is 10: controlled to 1: 1 to 20 Metal wiring formation method of a semiconductor element. 제 1 항에 있어서,The method of claim 1, 상기 하드 마스크막 및 상기 베리어막을 식각하는 단계와 상기 금속 배선을 형성하는 단계는 동일한 식각 장비를 이용하여 인 시튜(in-situ) 방식을 이용하여 실시하는 반도체 소자의 금속 배선 형성 방법.And etching the hard mask layer and the barrier layer and forming the metal lines using an in-situ method using the same etching equipment.
KR1020080021954A 2008-03-10 2008-03-10 Method of forming metal line in semiconductor device KR20090096878A (en)

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