KR20090096801A - Method for fabricating contact hole in semiconductor device - Google Patents

Abstract

A method for fabricating a contact hole in a semiconductor device is provided to prevent damage to a side protection barrier by selectively etching a substrate without etching a side protection barrier. In a method for fabricating a contact hole in a semiconductor device, an insulating layer(32) is formed on a substrate(31). A contact hole which selectively etches the insulating layer and exposes the substrate is formed, and a sidewall protection barrier(35) is formed in the side wall of the contact hole. The post etch is performed after etching the substrate selectively without etching the sidewall protection barrier, and the sidewall protection layer comprises a nitride film.

Description

Method for manufacturing contact hole of semiconductor device {METHOD FOR FABRICATING CONTACT HOLE IN SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly to a method for manufacturing a contact hole in a semiconductor device.

Spacing between gate patterns is also narrowed due to the high integration of semiconductor devices, leading to a failure in opening of landing plug contacts or self-aligned contact fail. There is a problem.

1A and 1B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

As shown in FIG. 1A, a gate pattern 12 is formed on the substrate 11. The gate pattern 12 may be a stacked structure of the polysilicon electrode 12A, the tungsten electrode 12B, and the gate hard mask 12C.

Subsequently, the gate spacer 13 and the cell spacer 14 are stacked on the entire structure including the gate pattern 12. The gate spacer 13 serves as a spacer for protecting the gate pattern 12 and forming a lightly doped drain (LDD) of the peripheral region, and the cell spacer 14 may serve as a spacer for forming a subsequent landing plug contact hole. This is to prevent impurities from penetrating into the substrate 11 during the protection and subsequent interlayer insulating film formation.

Subsequently, an interlayer insulating film 15 is formed on the cell spacer 14 to fill the gaps between the gate patterns 12.

Subsequently, a hard mask pattern 16 having a landing plug contact region open is formed on the interlayer insulating layer 15.

Subsequently, the interlayer insulating layer 15, the cell spacer 14, and the gate spacer 13 are etched using the hard mask pattern 16 as an etch barrier to form a landing plug contact hole 17 between the gate patterns 12.

As shown in FIG. 1B, a nitride film is formed on the entire structure including the landing plug contact hole 17 and an etch back is performed to form the sidewall protective film 18.

Subsequently, a light etching process is performed.

As described above, according to the related art, the gate spacer 13 and the cell spacer 14 are formed after the gate pattern 12 is formed, and the sidewall protective layer 18 is further formed after the landing plug contact hole 17 is formed.

However, the prior art has a problem in that not open of the landing plug contact hole 17 occurs as the space between the gate patterns 12 is narrowed. In addition, in order to prevent this, when the gate spacer 13 or the cell spacer 14 is formed to a thin thickness, there is a problem in that a self-aligned contact fail occurs.

In addition, as the space between the gate patterns 12 is narrowed, the substrate 11 is not exposed during the etch back process for forming the sidewall protection layer 18, thereby causing a problem of not opening. In addition, in order to prevent this, when the nitride film is formed to a thin thickness, the sidewall protective film 18 is lost during the post-etching process, thereby causing a self-aligned contact fail.

2A and 2B are TEM photographs showing contact holes of a semiconductor device according to the related art.

Referring to FIG. 2A, it can be seen that not open (100) has occurred in the landing plug contact hole.

As shown in FIG. 2B, it can be seen that a self-aligned contact fail 200 occurs between the landing plug contact hole and the gate pattern.

The present invention has been proposed to solve the above problems of the prior art, and an object of the present invention is to provide a method for manufacturing a contact hole of a semiconductor device which can prevent the sidewall protective film from being lost during the post etching process.

Another object of the present invention is to provide a method for manufacturing a contact hole in a semiconductor device capable of preventing a self-aligned contact failing between a contact hole and a gate pattern.

Contact hole manufacturing method of a semiconductor device of the present invention for achieving the above object comprises the steps of forming an insulating film on the substrate; Selectively etching the insulating film to form a contact hole exposing the substrate; Forming a sidewall protective layer on sidewalls of the contact holes; The sidewall protective layer may include a step of performing a post etching process using a gas capable of selectively etching the substrate without etching the sidewall protective layer.

In particular, the sidewall protective film is characterized in that it comprises a nitride film.

In addition, the post etching process may be performed by dry etching, and the mixed gas of Cl ₂ / He, the mixed gas of SF ₆ / O ₂ / He and the mixed gas of Cl ₂ / SF ₆ / O ₂ / He It characterized in that to proceed using any one of the mixed gas selected from the group consisting of.

In addition, the post etching process may include a planar type, a reactive ion beam etching (RIE), a magnetically enhanced RIE (MERIE), a split power type, a transformer coupled plasma (TCP), and the like. It is characterized in that it proceeds in any one device selected from the group consisting of Inductively Coupled Plasma (ICP).

The contact hole may be any one contact hole selected from the group consisting of a landing plug contact hole, a storage node contact hole, a storage node hole, and a metal contact hole.

In addition, the insulating film is any one selected from the group consisting of BPSG (Boron Phosphorus Silicate Glass), HDP (High Density Plasma), TEOS (Tetra Ethyle Ortho Silicate), HTO (High Temperature Oxide) and SOD (Spin On Dielectric) It characterized in that it comprises an oxide film formed.

In another aspect of the present invention, there is provided a method of manufacturing a contact hole in a semiconductor device, the method including: forming a gate pattern on a substrate; Forming a spacer on the entire structure including the gate pattern; Forming an insulating layer filling the gap between the gate patterns on the spacer; Etching the insulating layer and the spacer to form a contact hole exposing the substrate between the gate patterns; Forming a sidewall protective layer on sidewalls of the contact holes; The sidewall protective layer may include a step of performing a post etching process using a gas capable of selectively etching the substrate without etching the sidewall protective layer.

In particular, the spacer and the sidewall protective film is characterized in that it comprises a nitride film.

In addition, the post etching process may be performed by dry etching, and the mixed gas of Cl ₂ / He, the mixed gas of SF ₆ / O ₂ / He and the mixed gas of Cl ₂ / SF ₆ / O ₂ / He It characterized in that to proceed using any one of the mixed gas selected from the group consisting of.

In addition, the post etching process may include a planar type, a reactive ion beam etching (RIE), a magnetically enhanced RIE (MERIE), a split power type, a transformer coupled plasma (TCP), and the like. It is characterized in that it proceeds in any one device selected from the group consisting of Inductively Coupled Plasma (ICP).

In addition, the insulating film is any one selected from the group consisting of BPSG (Boron Phosphorus Silicate Glass), HDP (High Density Plasma), TEOS (Tetra Ethyle Ortho Silicate), HTO (High Temperature Oxide) and SOD (Spin On Dielectric) It characterized in that it comprises an oxide film formed.

The method for manufacturing a contact hole of the semiconductor device of the present invention described above has the effect of preventing the loss of the sidewall protective film by performing a post-etching process using a gas capable of selectively etching the substrate without etching the sidewall protective film. .

In addition, since the loss of the sidewall protective layer is prevented, there is an effect of preventing the self-aligned contact fail between the landing plug contact hole and the gate pattern.

In addition, since the sidewall protective film is formed to a thin thickness so as not to be lost, it is possible to prevent contact failure of the contact hole.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

3A to 3D are cross-sectional views illustrating a method of manufacturing a contact hole in a semiconductor device according to an embodiment of the present invention.

As shown in FIG. 3A, an insulating film 32 is formed on the substrate 31. The substrate 31 may be a silicon substrate to which a DRAM process is applied. The insulating film 32 is used as an insulating role between patterns, an insulating role between layers, or a sacrificial film role for forming a contact hole, and the like. For example, the insulating layer 32 is any one selected from the group consisting of Boron Phosphorus Silicate Glass (BPSG), High Density Plasma (HDP), Tetra Ethyle Ortho Silicate (TEOS), High Temperature Oxide (HTO), and Spin On Dielectric (SOD). It can be formed into an oxide film formed by the method of.

Next, a hard mask pattern 33 is formed on the insulating film 32. The hard mask pattern 33 forms a hard mask layer on the insulating film 32, coats the photoresist film on the hard mask layer, and opens the contact hole forming region by exposure and development. After patterning to form the photoresist pattern, the photoresist pattern may be formed by etching the hard mask layer as an etch barrier. After the hard mask pattern 33 is formed, only the hard mask pattern 33 may remain on the insulating layer 32 by removing the photoresist pattern.

Subsequently, the insulating layer 32 is etched using the hard mask pattern 33 as an etch barrier to form a contact hole 34 exposing the substrate 31. The contact hole 34 may be any one contact hole 34 selected from the group consisting of a landing plug contact hole, a storage node contact hole, a storage node hole, and a metal contact hole.

As shown in FIG. 3B, an insulating film 35 is formed on the entire structure including the contact hole 34. The insulating layer 35 serves to protect the sidewalls of the contact hole 34 and may include, for example, a nitride layer.

As shown in FIG. 3C, an etch back is performed to leave the insulating layer 35 on the sidewall of the contact hole 34.

Hereinafter, the insulating film 35 on the sidewall of the contact hole 34 is referred to as 'side wall protective film 35A'.

As shown in FIG. 3D, a post etching process is performed. The post etching process is for interfacial treatment of the substrate 31 whose lattice is broken by the etch back, and may be performed by dry etching.

The post etching process may be performed using a gas capable of selectively etching the substrate 31 without etching the sidewall protective film 35A. This is to protect the contact hole 34 by preventing the sidewall protection layer 35A from being excessively etched during the post etching process.

In particular, when the sidewall protective layer 35A is a nitride film and the substrate 31 is silicon, the nitride film should be selectively etched without being etched. For this purpose, a gas for etching silicon, for example, a mixed gas of Cl ₂ / He After the mixed gas of SF ₆ / O ₂ / He and a mixed gas of Cl ₂ / SF ₆ / O ₂ / He, any one selected from the group may be used to perform post-treatment etching. Preferably, it can proceed using a mixed gas of Cl ₂ / SF ₆ / O ₂ / He to ensure the highest selectivity between the nitride film and silicon.

The post-etching process includes planar type, reactive ion beam etching (RIE), magnetically enhanced RIE (MERIE), split power type (TCP), transformer coupled plasma (TCP) and inductively coupled plasma (ICP). It can proceed in any one selected from the group consisting of.

In general, the mixed gas of CF ₄ / O ₂ used in post-treatment etching has a etch rate of 1: 1.8 of the nitride film: silicon, whereas the nitride film is formed by using a mixed gas of Cl ₂ / SF ₆ / O ₂ / He. : Silicon etching speed is 1:30, so high selection ratio can be secured.

A portion of the open substrate 31 may be etched during the post etching process, and loss of the sidewall protective layer 35A may be prevented.

Furthermore, by preventing the loss of the sidewall protective film 35A during the post etching process, the thickness of the sidewall protective film 35A can be reduced by the amount prevented.

4A to 4F are cross-sectional views illustrating a method for manufacturing a landing plug contact hole in a semiconductor device according to an embodiment of the present invention.

As shown in FIG. 4A, the device isolation layer 42 is formed on the substrate 41. The substrate 41 may be a silicon substrate on which a DRAM process is performed. The device isolation layer 42 is used to define an active region on the substrate 41. The device isolation layer 42 is a group consisting of LOCal (LOCal Oxidation of Silicon), NSLOCOS (Nitride Spacer LOCOS), Poly Buffered LOCOS (PBL), and Shallow Trench Isolation (STI). It can be formed by any one method selected from.

Subsequently, a gate insulating film 43 is formed on the substrate 41. The gate insulating film 43 is for insulating between the gate pattern and the substrate 41 and may be formed in an oxide film series.

Subsequently, a gate pattern 44 is formed on the gate insulating film 43. The gate pattern 44 may be formed as a stacked structure of the first gate electrode 44A, the second gate electrode 44B, and the gate hard mask 44C. The first gate electrode 44A may include polysilicon. The second gate electrode may include any one layer structure or a stacked structure selected from the group consisting of polysilicon, tungsten silicide, tungsten, tungsten silicide and polysilicon lamination, and tungsten and polysilicon lamination. The gate hard mask 44C is to protect the gate pattern 44 when forming subsequent self aligned contact holes and the like, and may be formed of a nitride film series. For example, the gate hard mask 44C may be formed of a silicon nitride film.

Subsequently, a gate spacer 45 is formed on the entire structure including the gate pattern 44. The gate spacer 45 serves as a spacer when protecting the gate pattern 44 and forming a lightly doped drain (LDD) of a peripheral region, and may be formed of a nitride film series. For example, the gate spacer 45 may be formed of a silicon nitride film.

Subsequently, the cell spacers 46 are formed on the gate spacers 45. The cell spacers 46 may be formed of a nitride layer to protect the gate pattern 44 during the subsequent landing plug contact hole and to prevent impurities from penetrating into the substrate 11 during the subsequent interlayer insulating layer formation. For example, the cell spacer 46 may be formed of a silicon nitride film.

The gate spacers 45 and the cell spacers 46 are formed to surround the gate patterns 44, so that the bridges with the gate patterns 44 may be formed during the etching of the insulating layer during the subsequent landing plug contact hole formation. It acts as a spacer to prevent.

Next, an insulating film 47 is formed on the cell spacers 46 to fill the gaps between the gate patterns 44. The insulating film 47 is for insulating between the gate patterns 44 and interlayer insulating with the upper layer, and may be formed of an oxide film series. For example, the insulating layer 47 is any one selected from the group consisting of boron phosphorus silicate glass (BPSG), high density plasma (HDP), tetra thyle ortho silicate (TEOS), high temperature oxide (HTO) and spin on dielectric (SOD). It may include an oxide film formed by the method.

Subsequently, a hard mask pattern 48 is formed on the insulating film 47. In order to form the hard mask pattern 48, first, a hard mask layer is formed on the insulating film 47, a photosensitive film is coated on the hard mask layer, and landing is performed by exposure and development. The photoresist pattern is formed by patterning the plug contact hole forming region to be opened. After the hard mask layer is etched using the photoresist pattern as an etch barrier to form the hard mask pattern 48, the photoresist pattern may be removed. In another embodiment, although the insulating layer 47 is etched using only the hard mask pattern 48, the insulating layer 47 may be etched using the photoresist pattern and the hard mask pattern 48 as an etch barrier without removing the photoresist pattern. Can be.

As shown in FIG. 4B, the insulating film 47, the cell spacer 46, the gate spacer 45, and the gate insulating film 43 are etched using the hard mask pattern 48 as an etch barrier to expose the substrate 41. A landing plug contact hole 49 is formed.

Self-aligned contact etching may be performed to form the landing plug contact hole 49. This is because patterning through exposure is limited as semiconductor devices are highly integrated, and therefore, self-aligned contact etching using the selectivity between the oxide film and the nitride film is performed.

In the process of self-aligned contact etching, the cell spacer 46 and the gate spacer 45 are etched on the gate pattern 44 and the substrate 41 opened by the landing plug contact hole 49 so that the gate pattern ( May remain on the sidewall of 44).

As shown in FIG. 4C, the hard mask pattern 48 is removed.

Subsequently, the nitride film 50 is formed on the entire structure including the landing plug contact hole 49. The nitride film 50 may include, for example, a silicon nitride film. The nitride film 50 is intended to compensate for the loss of the cell spacer 46 or the gate spacer 45 due to self-aligned contact etching when the landing plug contact hole 49 is formed.

As shown in FIG. 4D, the nitride film 50 is etched by performing etch back. Therefore, the sidewall protection film 50A is formed on the cell spacers 46 in the landing plug contact hole 49.

As shown in FIG. 4E, the post etching process (Lightly Etch Treatment) is performed. The post etching process may be performed for interfacial treatment of the substrate 41 whose lattice is broken due to the etch back process of FIG. 4D, and may proceed to dry etching.

The post etching process may be performed using a gas capable of selectively etching the substrate 41 without etching the sidewall protective film 50A. This is to prevent the bridge from being generated between the landing plug contact hole 49 and the gate pattern 44 by preventing the sidewall protection layer 45A from being excessively etched during the post etching process.

In particular, when the sidewall protective film 50A is a nitride film and the substrate 41 is silicon, only the silicon should be selectively etched without etching the nitride film, and a gas for etching silicon, for example, a mixture of Cl ₂ / He by gas, SF ₆ / O ₂ mixed gas / gas mixture of He and any one selected among Cl ₂ / SF ₆ / O the group consisting of a gas mixture of ₂ / He may proceed to the post-processing etching. Preferably, it can proceed using a mixed gas of Cl ₂ / SF ₆ / O ₂ / He to ensure the highest selectivity between the nitride film and silicon.

The post-etching process includes planar type, reactive ion beam etching (RIE), magnetically enhanced RIE (MERIE), split power type (TCP), transformer coupled plasma (TCP) and inductively coupled plasma (ICP). It can proceed in any one selected from the group consisting of.

In general, the mixed gas of CF ₄ / O ₂ used for post-treatment etching has an etching rate of 1: 1.8 of silicon nitride, whereas a mixed gas of Cl ₂ / SF ₆ / O ₂ / He is used. As it progresses, the etching rate of the nitride film: the etching rate of the silicon is 1:30, thereby ensuring a high selectivity.

A portion of the open substrate 41 may be etched during the post etching process, and the loss of the sidewall passivation layer 50A may be prevented.

In addition, by preventing the loss of the sidewall protective film 50A during the post etching process, the thickness of the sidewall protective film 50A or the thickness of the cell spacer 46 or the thickness of the gate spacer 45 can be reduced by the amount prevented. Therefore, an open area may be secured during the etchback process for forming the sidewall protective layer 50A, thereby reducing the not-open opening of the landing plug contact hole 49.

As shown in FIG. 4F, a conductive material is filled in the landing plug contact hole 49 to form a landing plug contact 51.

5A and 5B are TEM photographs for comparing the present invention with a comparative example.

Figure 5a is a photograph after the etching process after using a mixed gas of CF ₄ / O ₂ commonly used, Figure 5b is a formula after using a mixed gas of Cl ₂ / SF ₆ / O ₂ / He according to an embodiment of the present invention It is a photograph after each process. It can be seen that the thickness of the sidewall protective film B of FIG. 5B remains thicker than the thickness of the sidewall protective film A of FIG. 5A.

That is, when the post etching process is performed using a different gas under the same etching conditions, the thickness of the sidewall protective film B during the post etching process according to the exemplary embodiment of the present invention is 30 kPa higher than that of the sidewall protective film A of the comparative example. It remains thick and shows little loss in etching.

Accordingly, self-aligned contact fail between the landing plug contact hole and the gate pattern is prevented, and the etching margin increases as the sidewall protection layer B is not lost. In addition, since the sidewall protective film B can be formed to a thin thickness so as not to be lost, contact failure of the landing plug contact hole can be prevented.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1A and 1B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art;

2A and 2B are TEM photographs showing contact holes of a semiconductor device according to the prior art;

3A to 3D are cross-sectional views illustrating a method of manufacturing a contact hole in a semiconductor device according to an embodiment of the present invention;

4A to 4F are cross-sectional views illustrating a method for manufacturing a landing plug contact hole in a semiconductor device according to an embodiment of the present invention;

5A and 5B are TEM photographs for comparing the present invention with a comparative example.

* Explanation of symbols for the main parts of the drawings

31 substrate 32 insulating film

33: hard mask pattern 34: contact hole

35 sidewall protective film

Claims (13)

Forming an insulating film on the substrate; Selectively etching the insulating film to form a contact hole exposing the substrate; Forming a sidewall protective layer on sidewalls of the contact holes; And Performing a post-etching process on the sidewall protective layer using a gas capable of selectively etching the substrate without etching the sidewall protective layer Contact hole manufacturing method of a semiconductor device comprising a. The method of claim 1, The sidewall protection layer is a contact hole manufacturing method of a semiconductor device comprising a nitride film. The method of claim 2, After the etching process, Method for manufacturing a contact hole of a semiconductor device by dry etching. The method of claim 3, After the etching process, The semiconductor device proceeds by using any one selected from the group consisting of a mixture of Cl ₂ / He, a mixture of SF ₆ / O ₂ / He and a mixture of Cl ₂ / SF ₆ / O ₂ / He. Contact hole manufacturing method. The method of claim 1, After the etching process, Any one selected from the group consisting of Planar Type, Reactive Ion Beam Etching (RIE), Magnetically Enhanced RIE (MERIE), Split Power Type (TCP), Transformer Coupled Plasma (TCP) and Inductively Coupled Plasma (ICP) Method for manufacturing a contact hole of a semiconductor device in one device. The method of claim 1, And the contact hole is any one contact hole selected from the group consisting of a landing plug contact hole, a storage node contact hole, a storage node hole, and a metal contact hole. The method of claim 1, The insulating film is formed by any one method selected from the group consisting of BPSG (Boron Phosphorus Silicate Glass), HDP (High Density Plasma), TEOS (Tetra Ethyle Ortho Silicate), HTO (High Temperature Oxide) and SOD (Spin On Dielectric) A method of manufacturing a semiconductor device comprising an oxide film. Forming a gate pattern on the substrate; Forming a spacer on the entire structure including the gate pattern; Forming an insulating layer filling the gap between the gate patterns on the spacer; Etching the insulating layer and the spacer to form a contact hole exposing the substrate between the gate patterns; Forming a sidewall protective layer on sidewalls of the contact holes; And Performing a post-etching process on the sidewall protective layer using a gas capable of selectively etching the substrate without etching the sidewall protective layer Contact hole manufacturing method of a semiconductor device comprising a. According to claim 8, The spacer and the sidewall protective layer comprises a nitride film. The method of claim 9, After the etching process, Method for manufacturing a contact hole of a semiconductor device by dry etching. The method of claim 10, After the etching process, The semiconductor device proceeds by using any one selected from the group consisting of a mixture of Cl ₂ / He, a mixture of SF ₆ / O ₂ / He and a mixture of Cl ₂ / SF ₆ / O ₂ / He. Contact hole manufacturing method. The method of claim 8, After the etching process, Any one selected from the group consisting of Planar Type, Reactive Ion Beam Etching (RIE), Magnetically Enhanced RIE (MERIE), Split Power Type (TCP), Transformer Coupled Plasma (TCP) and Inductively Coupled Plasma (ICP) Method for manufacturing a contact hole of a semiconductor device in one device. The method of claim 8, The insulating film is formed by any one method selected from the group consisting of BPSG (Boron Phosphorus Silicate Glass), HDP (High Density Plasma), TEOS (Tetra Ethyle Ortho Silicate), HTO (High Temperature Oxide) and SOD (Spin On Dielectric) A contact hole manufacturing method of a semiconductor device comprising an oxide film.

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