KR20090077306A - Substrate for semiconductor device and method for manufacturing the same and semiconductor device - Google Patents

Abstract

A semiconductor substrate and a manufacturing method thereof are provided to prevent substrate deformation due to inter-layer stress by forming a stress reducing layer having a multi-layer structure on the semiconductor substrate. A semiconductor substrate includes a stress reducing layer having a multi-layer structure. The stress reducing layer is formed on the semiconductor substrate. The stress reducing layer has a thickness of 10um to 100um under a condition that the semiconductor substrate has a thickness of 400um to 500um. A nitride film seed layer is formed on the semiconductor substrate by performing a first HVPE process under a first pressure condition(S131). A first nitride film is formed on the nitride film seed layer by performing a second HVPE process under a second pressure condition(S132). A second nitride film is formed on the first nitride film by performing a third HVPE process under a third pressure condition(S133).

Description

SUBSTRATE FOR SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME AND SEMICONDUCTOR DEVICE

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor substrate, and more particularly, to a semiconductor substrate, a method of manufacturing the same, and a semiconductor device, in which a multilayer stress relaxation layer is formed so as to minimize interlayer stress.

A semiconductor device is one of electronic components that implements electronic devices such as a power device, a light emitting device, and a light receiving device on a predetermined substrate by using semiconductor processing technology. For example, a power device includes a transistor, a MOSFET, an Insulated Gate Bipolar Transistor (IGBT), a Schottky diode, and the like, and a light receiver is implemented with a solar cell, a photo sensor, and the like on a substrate.

On the other hand, the substrate used in the fabrication of semiconductor devices is made by thinly cutting an ingot formed of silicon or other compound single crystal into a disc shape, and at least one surface thereof is mirror-treated to bond to thin film deposition. However, since a fine surface defect exists in the mirror-treated substrate, the device layer is not formed directly on the substrate, but the epitaxial layer is grown to a predetermined thickness in the middle to form a desired device layer thereon. In addition, an epitaxial layer serving as an insulating layer is grown by a predetermined thickness to electrically isolate various electronic devices formed in the device layer. In this case, it is advantageous to grow the epitaxial layer to some extent to reduce the stress due to lattice mismatch with the subsequent layer, that is, the stress.

However, when the epitaxial layer is grown to a predetermined thickness or more, the epitaxial layer is easily broken. Therefore, the epitaxial layer needs to be grown in multiple layers. In this case, stress is generated at the interface between the upper and lower epitaxial layers, thereby causing deformation of the substrate, particularly warpage. As such, when substrate deformation occurs, substrate chucking, substrate alignment, and the like become difficult, so that subsequent semiconductor processes, such as a photo process, an etching process, and the like, may not be performed smoothly. do. Thus, the yield is lowered and the defect is increased.

The present invention has been proposed to solve the above problems, by forming a stress relaxation layer of a multi-layer structure to minimize the interlayer stress on the substrate, it is possible to prevent the substrate deformation due to the interlayer stress during the formation of the stress relaxation layer An object thereof is to provide a semiconductor substrate, a method of manufacturing the same, and a semiconductor device.

In addition, the present invention provides a semiconductor substrate, a method of manufacturing the same, and a semiconductor device capable of preventing substrate deformation due to interfacial stress by forming a substantially thick stress relaxation layer on the substrate so as to minimize interfacial stress with a subsequent grown device layer. There is another purpose to provide.

In addition, the present invention provides a semiconductor substrate, a method for manufacturing the same, and a semiconductor substrate in which the stress relaxation layer can be formed considerably thicker without a significant increase in manufacturing time by forming the stress relaxation layer using the HVPE method, which has the advantage of fast deposition rate. Another object is to provide a device.

According to an aspect of the present invention, there is provided a semiconductor substrate comprising: a substrate; And a multilayer stress relaxation layer formed on the substrate. It includes, wherein the stress relaxation layer is formed in a thickness of 10μm to 100μm, under the condition that the thickness of the substrate is 400μm to 500μm.

It is preferable to further include a buffer layer formed on at least one of the interfaces formed between the substrate and the stress relaxation layer and between the multilayer semiconductor layer.

The buffer layer preferably includes at least one of a nitride film, an oxide film, and an oxynitride film.

The stress relieving layer may include a nitride film seed layer formed on the substrate through an HVPE process under a first pressure (p1) condition; A first nitride film formed on the nitride seed layer through an HVPE process at a second pressure (p2) condition; And a second nitride film formed on the first nitride film through an HVPE process at a third pressure (p3) condition. And p1, p2, and p3 preferably have a relationship of p1 <p2 <p3.

Preferably, the nitride film seed layer, the first nitride film, and the second nitride film are repeatedly stacked at least once.

The stress relaxation layer is preferably one of a gallium nitride film, an aluminum nitride film and a silicon film.

According to an aspect of the present invention, a method of manufacturing a semiconductor substrate includes: providing a substrate; Performing a first HVPE process at a first pressure p1 to form a nitride film seed layer on the substrate; Performing a second HVPE process at a second pressure (p2) condition to form a first nitride film on the nitride film seed layer; And performing a third HVPE process at a third pressure (p3) condition to form a second nitride film on the first nitride film. Wherein the first and second pressures are lower than atmospheric pressure, and p1, p2, and p3 have a relationship of p1 <p2 <p3.

The nitride seed layer forming step and the second nitride film forming step may be repeated at least once or more to form a multilayer stress relaxation layer on the substrate, and the third pressure may be atmospheric pressure.

The nitride film seed layer, the first nitride film, and the second nitride film contain metal and nitrogen, and are preferably the same material layer.

In the first, second, and third HVPE processes, the metal-containing gas generated by providing HCl gas to a container in which metal raw materials are stored is preferably supplied to the substrate.

Cleaning the surface of the substrate after at least one of the substrate preparing step, the nitride film seed layer forming step, the first nitride film forming step, and the second nitride film forming step; Treating the surface of the substrate using a processing gas; It is preferable to further comprise at least one step of.

In the substrate cleaning step, the substrate surface is preferably etched using a mixed gas of HCl and N ₂ .

In the surface treatment step, at least one of a nitride film, an oxide film, and an oxynitride film is formed on the surface of the substrate by supplying a nitrogen-containing gas and / or an oxygen-containing gas to the substrate.

It is preferable to carry out purging by supplying N ₂ gas into the chamber after the surface cleaning step or the surface treatment step.

Each of these steps is preferably carried out in a single chamber.

According to still another aspect of the present invention, a semiconductor device includes: a substrate; And a multilayer stress relaxation layer formed on the substrate. And an electronic device layer formed on the stress relaxation layer. It includes, wherein the stress relaxation layer is preferably formed in a thickness of 10μm to 100μm under the condition that the thickness of the substrate is 400μm to 500μm.

At least one of a transistor, a solar cell, a light emitting device, a MOSFET, a Schottky diode, and a photo sensor may be formed in the electronic device layer.

In the present invention, a buffer layer is formed between multilayer nitride films formed on a substrate to form a stress relaxation layer. Therefore, since the interlayer stress of the nitride films can be minimized by the buffer layer, even if the stress relaxation layer is formed thicker than the general case, the deformation of the substrate due to the interlayer stress can be prevented.

In addition, the present invention can minimize the interface stress between the substrate and the device layer formed on the stress relief layer formed thicker than the general case, the substrate according to the interface stress even if the device layer is formed through a subsequent process on the substrate Deformation is prevented. Therefore, since substrate handling such as substrate chucking and substrate alignment is easy, subsequent semiconductor processes, such as a photo process and an etching process, for forming a device layer may be performed smoothly.

In addition, the present invention by forming a stress relaxation layer on the substrate by using the HVPE method, which has the advantage of fast deposition rate, it is possible to form a stress relaxation layer thicker than usual without significant increase in manufacturing time, thereby reducing manufacturing costs can do.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention; However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information. Like reference numerals in the drawings refer to like elements.

In the drawings, the thickness of layers, films, panels, regions, etc., may be exaggerated for clarity, and like reference numerals designate like elements. In addition, when a part such as a layer, a film, an area, or a plate is expressed as “above” or “above” another part, each part is not only when the part is “right above” or “just above” the other part, This includes the case where there is another part between other parts.

1 is a flowchart illustrating a method of manufacturing a semiconductor substrate according to an embodiment of the present invention.

Referring to FIG. 1, a method of manufacturing a semiconductor substrate according to an embodiment of the present invention includes a substrate loading step (S110); Surface cleaning step (S121); Surface treatment step (S122); Forming a stress relaxation layer (S130) and unloading the substrate (S140); The stress relief layer forming step (S130) includes a nitride film seed layer forming step (S131); A first nitride film forming step (S132) and a second nitride film forming step (S133); Including the stress relief layer of a multi-layer structure on a predetermined substrate can be formed significantly thicker than the general case.

In the stress relaxation layer forming step (S130), each process step (S131, S132, S133) may be repeatedly performed one or more times, and the entire process steps (S131 to S133) may be repeatedly performed one or more times. In addition, at least one of the surface cleaning step S121 and the surface treatment step S122 may be selectively performed between the steps S131, S132, and S133 in the stress relaxation layer forming step S130. . For example, the surface cleaning step S121 and the previous surface treatment step S122 may be carried out before each of the steps S131, S132, and S133, or the surface cleaning step ( S121) or the surface treatment step S122 may be performed alone.

In the substrate loading step (S110), first, the internal temperature of the prepared chamber is maintained at a temperature range of 300 ° C. to 800 ° C., and the substrate is introduced into the chamber while purging using N ₂ gas, thereby introducing the chamber. The substrate inserted into the substrate holder provided therein is mounted. The substrate holder may be any means as long as the substrate can be stably fixed to a predetermined deposition position. For example, the substrate holder may be a holder type for holding the substrate surface vertically, or a stage type for placing the substrate surface horizontally may be used. The substrate may be a silicon on insulation (SOI) substrate or a single crystal semiconductor wafer having a single crystal semiconductor layer. The single crystal semiconductor layer may be any one of a single crystal silicon layer, a single crystal sapphire layer, a single crystal germanium layer, a single crystal silicon germanium layer or a single crystal silicon carbide layer, and the single crystal semiconductor wafer is a single crystal silicon wafer, a single crystal sapphire wafer, a single crystal germanium wafer It may be one of a single crystal silicon germanium wafer, a single crystal silicon carbide wafer, a single crystal sapphire wafer. In this embodiment, a case of using a single crystal sapphire wafer (hereinafter referred to as a sapphire substrate) will be described.

In the surface cleaning step S121, impurities remaining on a surface, for example, a substrate surface, are removed using a cleaning gas. At this time, the surface cleaning is performed for 5 minutes to 30 minutes using a mixed gas of HCl and N _{2 in} a mixing ratio of 1: 5 to 1:10 under a process pressure of 0.30 Torr to 0.76 Torr and a process temperature of 1000 ° C to 1100 ° C. It is preferable to perform a degree surface etching. On the other hand, in the surface cleaning step (S121), the roughness (surfaceness) of the surface may be slightly increased by etching with HCl gas, but is not increased any more than a certain time, the surface roughening step (S122) And the stress relaxation layer forming step (S130).

In the surface treatment step (S122), a nitrogen (N) -containing gas and / or an oxygen (O) -containing gas are supplied to the surface of the substrate to form a nitride layer, an oxide layer, or an oxynitride layer. At least one thin film layer is formed to form a buffer layer. In the case of using a sapphire substrate, if a reactive gas containing nitrogen, for example, N ₂ , NH ₃ , NH ₃ / N _2, etc. is supplied, a nitride film buffer layer will be formed, and a reactive gas containing nitrogen and oxygen For example, NH ₃ Supplying a mixed gas of and O ₂ will form an oxynitride buffer layer. In addition, supplying a reaction gas containing nitrogen, oxygen, and silicon, such as a mixed gas of N ₂ O and Si, will form a silicon oxide nitride layer buffer layer. On the other hand, the buffer layer is preferably formed to be considerably thinner than the subsequent layer to be formed later, that is, the first nitride film. For example, in the surface treatment step (S122), by performing a surface treatment for about 1 to 5 minutes using the LPCVD process under the conditions of the process pressure is 0.6 Torr to 0.8 Torr, the process temperature is 1000 ℃ to 1100 ℃, 100 ~ 500 Pa It is preferable to form a buffer layer having a thickness of about. This buffer layer serves to minimize interlayer stress by reducing lattice defects between the underlying layer, for example, the substrate, and the subsequent layer to be formed, for example, the first nitride layer.

Before or after the surface treatment step S120 including at least one of the surface cleaning step S121 and the surface treatment step S122 is started, purging with N ₂ gas is performed to process the interior of the chamber. It is desirable to change the atmosphere.

In the stress relaxation layer forming step (S130), a nitride film seed layer is formed to grow a nitride film on the substrate (S131), and the first nitride film and the second nitride film are stacked and formed on the substrate on which the nitride film seed layer is formed. (S132, S133).

The stress relaxation layer is preferably carried out using a HVPE (Hydride Vapor Phase Epitaxy) process. The HVPE process is connected to the inside of the chamber and supplies a reaction gas and a transfer gas to a container in which a raw material is added, for example, a metal raw material feed tube, so that raw material particles decomposed from the raw material are heated in the chamber. By allowing the surface to be supplied, the desired crystal thin film is grown on the substrate while the raw material particles are deposited on the surface of the substrate by the gas phase reaction. At this time, HCl gas may be used as the reaction gas, and inert gas such as N ₂ or Ar may be used as the transfer gas. In the present embodiment, a seed having a thickness of about 100 kPa to about 500 kPa is performed by performing an HVPE process for about 1 to 3 minutes using a source gas at a process pressure of 0.30 Torr to 0.80 Torr and a process temperature of 1000 to 1100 ° C. It is preferable to form a layer. In addition, the first pressure having a thickness of about 0.5μm to 1μm by performing the HVPE process for about 1 minute to 10 minutes using the source gas under the conditions of the process pressure is 0.6Torr to 1.0Torr, the process temperature is 1000 ℃ to 1100 ℃. It is preferable to form a nitride film. In addition, the second pressure having a thickness of about 6μm to 30μm by performing the HVPE process for about 2 to 20 minutes using the raw material gas under the condition that the process pressure is at least atmospheric pressure, that is, 760 Torr or more and the process temperature is 1000 ℃ to 1100 ℃ It is preferable to form a nitride film.

On the other hand, the stress relaxation layer is preferably to form a stress relaxation layer at a slow deposition rate initially to increase the deposition rate step by step to minimize the generation of stress due to lattice mismatch. To this end, the HVPE process for the formation of the stress relief layer is preferably carried out by increasing the process pressure step by step from low pressure to less than atmospheric pressure to or near atmospheric pressure. For example, when the process pressure at the time of forming the nitride film seed layer is represented by p1, the process pressure at the time of forming the second nitride film is represented by p2, and the process pressure at the time of forming the third nitride film is represented by p3, p1, p2, and p3 are represented by p1 <p2 < It has a relationship of p3. Where p3 is at atmospheric pressure, ie 760 Torr or near atmospheric pressure. Accordingly, when the deposition rate at the time of forming the nitride film seed layer is represented by d1, the deposition rate at the time of forming the second nitride film is represented by d2, and the deposition rate at the time of forming the third nitride film is represented by d3, d1, d2, and d3 denote d1 < d2 <d3. As such, in the present embodiment, in forming the stress relaxation layer through the HVPE process, the HVPE process is performed while increasing the process pressure step by step from low pressure to atmospheric pressure. Therefore, the deposition rate is kept low at the initial stage of the deposition due to the lattice mismatch, but the deposition rate is increased step by step after the deposition stage where the stress is reduced. As a result, a thin film of a thick thickness can be formed without a significant decrease in the deposition rate, and the cracking phenomenon of the thin film can be prevented.

In the substrate unloading step (S107), first, after the above process is completed, purging using N ₂ gas is performed. Subsequently, while purging with N ₂ gas, the chamber is gradually lowered until the internal temperature of the chamber reaches a temperature range of 300 ° C. to 800 ° C. or room temperature. Through this, it is possible to minimize the thermal shock of the substrate. Thereafter, the substrate is detached from the substrate holder, and the detached substrate is taken out of the chamber. In this case, the substrate drawn out of the chamber may be introduced into a subsequent process for forming an electronic device such as a power layer, a light emitting device, a light receiving device, and the like on top thereof.

On the other hand, all of the above processes can be performed in a single chamber. For example, a single or multiple gas lines supplying various gases to a single chamber and HVPE raw material injection means can be connected to continuously perform substrate cleaning, LPCVD and HVPE processes within a single chamber. Therefore, the problem of increase in manufacturing time and contamination of the substrate that occur in the process of moving the substrate to the plurality of chambers does not occur.

A method of manufacturing a semiconductor substrate according to an embodiment of the present invention having such a process step will be described in more detail with reference to the accompanying drawings. In the following, a sapphire substrate is used as a substrate, and a case where a stress relaxation layer is formed by forming a gallium nitride film (GaN) on the substrate will be described. Of course, the present invention is not limited thereto, and the stress relaxation layer may be formed of various semiconductor films, for example, silicon film Si and aluminum nitride film AlN.

2 to 7 are cross-sectional views illustrating a method of manufacturing a semiconductor substrate in accordance with an embodiment of the present invention.

First, as shown in FIG. 2, when the substrate 100 is provided, the surface of the substrate 100 is cleaned using a cleaning gas. In this case, the surface cleaning may be performed by etching the surface of the substrate 100 for about 20 minutes using a mixed gas of a mixture ratio of HCl and N ₂ 1: 5 at a process pressure of 0.75 Torr, a process temperature of 1000 ℃. .

Subsequently, as shown in FIG. 3, when the surface cleaning of the substrate 100 is completed, the surface of the substrate 100 is nitrided to form a first buffer layer 210 having a predetermined thickness on the substrate 100. At this time, the surface treatment was performed at a surface pressure of 0.75 Torr and a process temperature of 1000 ° C. for 1 minute by using a mixed gas having a mixing ratio of NH ₃ and N ₂ of 2: 3 to obtain a thickness of about 100 kPa. The nitride film which has is formed. Subsequently, purging with N ₂ gas is used to change the process atmosphere inside the chamber, and a mixed gas having a mixing ratio of NH ₃ and N ₂ is 2: 3 under a condition of 0.70 Torr and a process temperature of 1000 ° C. Surface treatment is performed for about 5 minutes to form a nitride film having a thickness of about 500 GPa to form a first buffer layer 210 having a total thickness of about 600 GPa. Of course, the first buffer layer 210 is not limited to the nitride film, but may be formed of an oxide film, an oxynitride film, or the like.

Subsequently, as shown in FIG. 4, the process atmosphere inside the chamber is changed by purging with N ₂ gas, the process pressure p1 is lowered to 0.55 Torr, and the first HVPE process is performed on the first buffer layer 210. The gallium nitride film seed layer 220 is formed on the substrate. At this time, the gallium nitride film seed layer 220 having a thickness of about 1000 kPa is formed by performing the first HVPE process for about 3 minutes under the condition that the process temperature is 1000 ° C. Thereafter, the gallium nitride film seed layer 220 is cleaned on the surface of the gallium nitride film seed layer 220 for about 1 minute using a cleaning gas having a mixing ratio of HCl and N ₂ of 1: 5 at a process temperature of 1000 ° C. and a process pressure of 0.75 Torr. Purging with N ₂ gas changes the process atmosphere inside the chamber. The surface of the gallium nitride film seed layer 220 is nitrided for about 10 minutes using a reaction gas having a mixing ratio of NH ₃ and N ₂ of 2: 3 at a process temperature of 1000 ° C. and a process pressure of 0.75 Torr. In this case, a second buffer layer 230 is formed on the gallium nitride film seed layer 220.

Subsequently, as shown in FIG. 5, the first gallium nitride layer 240 is formed on the second buffer layer 230 by maintaining the process pressure p2 at 0.75 Torr and performing a second HVPE process. At this time, the second HVPE process is performed by the HVPE process for about 7 minutes at a process temperature of 1000 ° C to 1100 ° C, thereby forming the first gallium nitride film 240 having a thickness of about 0.9 μm. Subsequently, surface cleaning of the first gallium nitride layer 240 is omitted, using a reaction gas having a mixing ratio of NH ₃ and N ₂ of 2: 3, at a process temperature of 1000 ° C. and a process pressure of 0.75 Torr, for about 10 minutes. The surface of the first gallium nitride film 240 is nitrided. In this case, a third buffer layer 250 is formed on the first gallium nitride layer 240.

6, the second gallium nitride layer 260 is formed on the third buffer layer 250 by increasing the process pressure p3 to atmospheric pressure, that is, 760 Torr or more and performing a third HVPE process. At this time, the second gallium nitride film 260 having a thickness of about 20 μm is formed by performing the third HVPE process for about 10 minutes under the condition that the process temperature is 1100 ° C.

Thereafter, as shown in FIG. 7, the process of FIGS. 2 to 6 is repeated once to form a multi-layer stress relaxation layer 200 on the substrate 100. At this time, the second secondary HVPE process is repeatedly performed for about 7 minutes under the condition of 0.75 Torr and 1000 ° C., and the secondary first gallium nitride film 240-has a thickness of 9000 kPa on the substrate 100. 2) is formed, and the repeated second tertiary HVPE process is carried out for about 30 minutes under a process pressure of 760 Torr and a process temperature of 1100 ° C., thereby forming a secondary secondary gallium nitride film having a thickness of 60 μm on the substrate 100. 260-2 is formed. Accordingly, in the final step, a multi-layer stress relaxation layer 200 having a total thickness of about 82 μm is formed on the substrate 110.

As such, in the present embodiment, in forming the multi-layer stress relief layer 200 through the HVPE process, the HVPE process is performed while gradually increasing the process pressure from low pressure to atmospheric pressure. Therefore, the thin film deposition rate is kept low at the initial stage of the deposition due to the lattice mismatch, and the thin film deposition rate is gradually increased after the initial deposition stage where the magnitude of the stress is reduced. As a result, a thin film of a thick thickness can be formed without a significant decrease in the deposition rate, and the cracking phenomenon of the thin film can be prevented. In addition, since the present embodiment first performs a surface treatment on the preceding layer when forming the gallium nitride films 240, 260, 240-2, and 260-2, the buffer layers 210, 230, 250, 210-2, 230 are formed at the interface between the multi-layer gallium nitride films 240, 260, 240-2, 260-2. -2,250-2) is formed. Since the buffer layers 210, 230, 250, 210-2, 230-2, and 250-2 relieve interlayer stresses, a considerably thick stress relaxation layer 200 can be formed without breaking the thin film. On the other hand, the thickened stress relief layer 200 serves to minimize the interfacial stress with the device layer to be subsequently formed. Therefore, even if the device layer is subsequently formed on the stress relaxation layer 200, the substrate 100 has a significantly lower bending characteristic. For example, it can be seen that the warpage of the substrate is measured within 40 μm when the stress relaxation layer having a thickness of 82 inches is formed on a substrate having a diameter of 2 inches and a thickness of 430 μm through the above process.

Meanwhile, the semiconductor substrate according to the present invention may be used as a substrate for manufacturing various semiconductor devices. Hereinafter, a semiconductor device in which various electronic devices are formed on the semiconductor substrate described above will be described as an example of such a possibility. In this case, a description overlapping with the above-described embodiment will be omitted or briefly described.

8 is a cross-sectional view of a semiconductor device having a semiconductor substrate according to an embodiment of the present invention.

Referring to FIG. 8, the semiconductor device may include a substrate 410, a stress relaxation layer 420 formed in multiple layers on the substrate 410 to relieve interlayer stress, and a device formed on the stress relaxation layer 420. Layer 430. Such a semiconductor device may be used in a switching power supply circuit of a power module such as an inverter such that at least one transistor T is provided in the device layer 430 to perform a power switching function.

As described above, the substrate 410 may be an SOI substrate or a single crystal semiconductor wafer having a single crystal semiconductor layer. For example, this embodiment uses a sapphire substrate.

As described above, the stress relaxation layer 420 forms a multi-layer nitride film 421 or 422 by performing an HVPE process while gradually increasing the process pressure from low pressure to atmospheric pressure to minimize interlayer stress due to lattice mismatch. A buffer layer (not shown) may be formed between the multilayer nitride films 421 and 422 through a treatment process. The stress relaxation layer 520 is formed to a thickness of 10 μm to 100 μm or less under the condition that the size of the substrate 510 is 1.5 to 2.5 inches and the thickness of the substrate 510 is 400 μm to 500 μm, thereby preventing warpage of the substrate 510. Can be controlled within 70μm.

At least one transistor T is provided in the device layer 430. The transistor T includes a gate electrode 431 formed on the stress relaxation layer 420 of the substrate 410, a gate insulating layer 432 formed on the entire structure including the gate electrode 431, and the gate electrode ( An active layer 433 formed in an island shape isolated on the gate insulating film 432 and an ohmic contact layer 434 formed on the active layer 433 and a source formed on the ohmic contact 434 layer corresponding to 431. An electrode 435, a drain electrode 436, and a protective film 437 are included. Of course, if low power, low heat and high speed switching operation is required, a metal-oxide semiconductor field effect transistor (MOSEFT) may be formed instead of the above-described transistor.

In the semiconductor device, a device layer 430 including a thin film transistor T is formed on the stress relaxation layer 420, and the stress relaxation layer 430 is formed between the substrate 410 and the device layer 430. Since the stress is relieved, deformation of the substrate 410, in particular, warpage does not occur in the process of forming the device layer 430 on the substrate 410. Therefore, since the substrate is easily handled, such as substrate chucking and substrate alignment in a subsequent process, there is no problem in yield reduction and defect increase as in the prior art.

9 is a cross-sectional view of another semiconductor device including a semiconductor substrate according to an embodiment of the present invention.

Referring to FIG. 9, the semiconductor device may include a substrate 510, a stress relaxation layer 520 formed in multiple layers on the substrate 510, and a stress relaxation layer 520 for relaxing interlayer stress, and a device formed on the stress relaxation layer 520. Layer 530. In the semiconductor device, at least one solar cell S for converting light energy into electrical energy may be provided in the device layer 530 to be used in a power module.

As described above, the substrate 510 may be an SOI substrate or a single crystal semiconductor wafer having a single crystal semiconductor layer. For example, this embodiment uses a sapphire substrate.

As described above, the stress relaxation layer 520 is formed by increasing the process pressure from low pressure to atmospheric pressure step by step to minimize the interlayer stress due to lattice mismatch, and forming multi-layer nitride films 521 and 522 by surface treatment process. A buffer layer (not shown) may be formed between the multilayer nitride films 521 and 522.

At least one solar cell S is provided in the device layer 530. The solar cell S includes a first electrode 531 formed on the stress relaxation layer 520 of the substrate 510, a charge transport layer 532 formed on the first electrode 531, an n-type layer and a p-type layer. The stacked active layer 533, the hole transport layer 534 formed on the active layer 533, and the second electrode 535 formed in a portion of the hole transport layer 534. Here, the first electrode 531 is preferably formed of a transparent conductive film. For example, indium tin oxide (ITO) or indium zinc oxide (IZO) may be used. In addition, the second electrode 535 may be a conductive film having a low work function, for example, a single layer of calcium (Ca), an aluminum (Al) -lithium (Li) alloy film, and a magnesium (Mg) -silver (Ag) alloy film. It is preferable to use etc. These metals have a small work function, which enables power generation in an environment with less sunlight than other metals.

In the semiconductor device having such a configuration, the device layer 530 including the solar cell S is formed on the stress relaxation layer 520, and the stress relaxation layer 530 includes the substrate 510 and the device layer 530. Since the interlayer stress of () is relaxed, deformation of the substrate 510, in particular, warpage does not occur in the process of forming the device layer 530 on the substrate 510. Therefore, since the substrate 510 is easily handled in a subsequent process, such as substrate chucking and substrate alignment, there is no problem of a decrease in yield and an increase in defect as in the prior art.

10 is a cross-sectional view of another semiconductor device including a semiconductor substrate according to an embodiment of the present invention.

Referring to FIG. 10, the semiconductor device may include a substrate 610, a stress relaxation layer 620 formed in multiple layers on the substrate 610 to relieve interlayer stress, and a device formed on the stress relaxation layer 620. Layer 630. In the semiconductor device, at least one light emitting device L may be provided in the device layer 630 to convert electrical energy into light energy.

As described above, the substrate 610 may use an SOI substrate or a single crystal semiconductor wafer having a single crystal semiconductor layer. For example, this embodiment uses a sapphire substrate.

As described above, the stress relaxation layer 620 forms a multilayer nitride film 621 or 622 by increasing the process pressure from low pressure to atmospheric pressure in a step-by-step manner to minimize interlayer stress due to lattice mismatch. A buffer layer (not shown) may be formed between the multilayer nitride films 621 and 622 through a treatment process.

At least one light emitting device L is provided in the electronic device layer 630. The light emitting device L is a semiconductor layer including an n-type layer 631, an active layer 632, and a p-type layer 633 stacked on a stress relaxation layer 620 of a substrate 610, and the n-type layer 631. A first electrode 634 formed in a portion of the () and a second electrode 635 formed in a portion of the p-type layer 633. The n-type layer 631, the active layer 632, and the p-type layer 633 may be formed of a semiconductor thin film including at least one of Si, GaN, AlN, InGaN, AlGaN, and AlInGaN. On the other hand, for example, in this embodiment, the n-type layer 631 and the p-type layer 633 are formed of a GaN thin film, and the active layer 632 is formed of an InGaN thin film. The n-type layer 631 is a layer providing electrons, and may be formed by injecting an n-type dopant, for example, Si, Ge, Se, Te, or C, into the semiconductor thin film. The p-type layer 633 is a layer for providing holes, and may be formed by implanting a p-type dopant, for example, Mg, Zn, Be, Ca, Sr, or Ba into the semiconductor thin film. The active layer 632 is a layer that outputs light having a predetermined wavelength while the electrons provided in the n-type layer 631 and the holes provided in the p-type layer 633 are recombined to form a well layer and a barrier layer. By alternately stacking may be formed as a multi-layered semiconductor thin film having a single quantum well structure or multiple quantum well structure. Since the wavelength of light to be output varies depending on the semiconductor material constituting the active layer 632, it is preferable to select an appropriate semiconductor material according to the target output wavelength.

In the semiconductor device, the device layer 630 including the light emitting device L is formed on the stress relaxation layer 620, and the stress relaxation layer 630 is formed between the substrate 510 and the device layer 630. Since the stress is relaxed, deformation of the substrate 610, in particular, warpage does not occur in the process of forming the device layer 630 on the substrate 610. Therefore, since the substrate is easily handled, such as substrate chucking and substrate alignment in a subsequent process, there is no problem in yield reduction and defect increase as in the prior art.

Meanwhile, the above-described semiconductor device has a transistor, a solar cell, or a light emitting device formed on a substrate on which a stress relaxation layer is formed. However, the present invention is not limited thereto, and various electronic devices such as MOSFETs, Schottky diodes, photosensors, and the like may be formed.

As mentioned above, although this invention was demonstrated with reference to the above-mentioned Example and an accompanying drawing, this invention is not limited to this, It is limited by the following claims. Therefore, it will be apparent to those skilled in the art that the present invention may be variously modified and modified without departing from the technical spirit of the following claims.

1 is a process flowchart illustrating a method of manufacturing a semiconductor substrate according to an embodiment of the present invention.

2 to 7 are cross-sectional views illustrating a method of manufacturing a semiconductor substrate in accordance with an embodiment of the present invention.

8 is a cross-sectional view of a semiconductor device having a semiconductor substrate according to an embodiment of the present invention.

9 is a cross-sectional view of another semiconductor device including a semiconductor substrate according to the embodiment of the present invention.

10 is a cross-sectional view of another semiconductor device including a semiconductor substrate in accordance with an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100: substrate 200: stress relaxation layer

210: first buffer layer 220: nitride film seed layer

230: second buffer layer 240: first nitride film

250: third buffer layer 260: second nitride film

T: transistor S: solar cell

L: light emitting element

Claims (16)

Board; And A multilayer stress relaxation layer formed on the substrate; Including, The stress relaxation layer is a semiconductor substrate formed in a thickness of less than 10μm to 100μm under the condition that the thickness of the substrate is 400μm to 500μm. The method according to claim 1, And a buffer layer formed on at least one of the interfaces formed between the substrate and the stress relaxation layer and between the multilayer semiconductor layers. The method according to claim 2, The buffer layer includes at least one of a nitride film, an oxide film, and an oxynitride film. The method according to claim 2, The stress relaxation layer, A nitride film seed layer formed on the substrate through an HVPE process at a first pressure p1; A first nitride film formed on the nitride seed layer through an HVPE process at a second pressure (p2) condition; And A second nitride film formed on the first nitride film through an HVPE process at a third pressure (p3) condition; Including, P1, p2, and p3 have a relationship of p1 <p2 <p3. The method according to claim 4, And the nitride film seed layer, the first nitride film, and the second nitride film are repeatedly stacked at least one or more times. The method according to claim 1, The stress relaxation layer is one of a gallium nitride film, an aluminum nitride film and a silicon film. Preparing a substrate; Performing a first HVPE process at a first pressure p1 to form a nitride film seed layer on the substrate; Performing a second HVPE process at a second pressure (p2) condition to form a first nitride film on the nitride film seed layer; Performing a third HVPE process under a third pressure (p3) condition to form a second nitride film on the first nitride film; The first and second pressures are pressures lower than atmospheric pressure, and the p1, p2, and p3 have a relationship of p1 <p2 <p3. The method according to claim 7, And repeating the nitride film seed layer forming step and the second nitride film forming step at least one or more times to form a multilayer stress relaxation layer on the substrate, wherein the third pressure is atmospheric pressure. The method according to claim 7, The nitride film seed layer, the first nitride film and the second nitride film contain a metal and nitrogen and are a same material layer. The method according to claim 7, After at least one of the substrate preparing step, the nitride film seed layer forming step, the first nitride film forming step, and the second nitride film forming step, Cleaning the surface of the substrate; And Treating the surface of the substrate using a processing gas; The method of manufacturing a semiconductor substrate further comprising at least one step. The method according to claim 10, The substrate cleaning step, A method of manufacturing a semiconductor substrate using a mixed gas of HCl and N ₂ to etch the substrate surface. The method according to claim 10, The surface treatment step, Supplying a nitrogen-containing gas and / or an oxygen-containing gas to the substrate to form at least one of a nitride film, an oxide film, and an oxynitride film on the substrate surface. The method according to claim 10, And purging by supplying N ₂ gas into the chamber after the surface cleaning step or the surface treatment step. The method according to claim 7, claim 10 or 13, Wherein each of the steps is performed in a single chamber. Board; And A multilayer stress relaxation layer formed on the substrate; And An electronic device layer formed on the stress relaxation layer; Including, The stress relaxation layer is a semiconductor device formed to a thickness of less than 10μm to 100μm under the condition that the thickness of the substrate is 400μm to 500μm. The method according to claim 15, At least one of a transistor, a solar cell, a light emitting device, a MOSFET, a Schottky diode, and a photo sensor is formed in the electronic device layer.

Images