KR20090074533A - Method for manufacturing a nonvolatile memory device - Google Patents

Abstract

A method for manufacturing a non-volatile memory device is provided to form a wing spacer between neighboring floating gates in order to improve the cycling property of the device. A tunnel insulating layer(101A) and a first conductive layer(102B) are formed on a substrate(100A). The first conductive layer, the tunnel insulating layer and the substrate are partially etched to form trenches. Some of the trenches are padded to form a device isolation film. A spacer(105A) consisting of a second conductive layer is formed on the both sides of the first conductive layer. The device isolation film is partially recessed by the spacer serving as an etching barrier and therefore a wing spacer is formed. A dielectric film(106) is formed on the top. A third conductive film(107) is formed on the dielectric film.

Description

Manufacturing method of nonvolatile memory device {METHOD FOR MANUFACTURING A NONVOLATILE MEMORY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing technology, and more particularly, to a nonvolatile memory device and a method for manufacturing the same, and more particularly, to a nonvolatile memory device and a manufacturing method thereof, in which a plurality of memory cells are connected in series to form a unit string. It is about a method.

NAND type flash memory device, which is a nonvolatile memory device, is composed of a plurality of cells connected in series to form a unit string for high integration. A memory stick and a USB driver (Universal Serial Bus) are mainly used. Drivers and hard disk (hard disk) to replace the device is expanding the field of application.

In general, NAND flash memory devices implement a self-aligned-shallow trench isolation (SA-STI) process to implement device isolation (device isolation layer formation) and to form floating gates. The SA-STI process has the advantage that the surface area of the floating gate can be freely controlled by forming the floating gate in a laminated structure, but the alignment margin during the etching process is formed by additionally performing the etching process to form the floating gate. ), It is difficult to control the process.

Accordingly, an ASA-STI (Advanced Self Aligned-STI) process has recently been proposed. In the ASA-STI process, the write speed and the interference effect can be improved while ensuring the effective field oxide height (hereinafter referred to as EFH)-the distance from the surface of the active region to the dielectric film between neighboring floating gates. The solution is important.

Due to its characteristics, securing of EFH, improvement of writing speed and interference effect are in a trade off relationship. In other words, the higher the EFH, the lower the write operation speed, while improving the interference effect. The reason for this is that when the EFH is high, the contact area and the coupling ratio between the dielectric film and the floating gate are reduced accordingly, and the writing operation speed is reduced.

Therefore, in recent years, a technique called 'wing spacer' has been proposed to improve the interference effect in the manufacturing process of the device applying the ASA-STI process. This technique shields between neighboring floating gates with a control gate. This technology improves one of the key characteristics of NAND flash memory devices-cycling characteristics-reducing threshold voltage fluctuations during program / erase operations.

However, as the higher integration increases, the gap between neighboring floating gates-the width of the device isolation layer-decreases, thereby making it difficult to apply the wing spacer technique. Accordingly, a problem arises in that the cycling characteristics of the NAND flash memory device are deteriorated.

Accordingly, the present invention has been proposed to solve the problems according to the prior art, and provides a method of manufacturing a nonvolatile memory device that can improve the cycling characteristics of the device by providing a wing spacer technology while simplifying a process. The purpose is.

According to an aspect of the present invention, a tunnel insulating film and a first conductive film are formed on a substrate, and the first conductive film, the tunnel insulating film, and the substrate are partially etched to form trenches. Forming a device isolation layer to partially fill the trench, forming a spacer including a second conductive film on both sidewalls of the first conductive film, and partially forming the device isolation layer as an etch barrier layer. Forming a wing spacer by recessing, forming a dielectric film along an upper surface of the structure including the wing spacer, and forming a third conductive film on the dielectric film. Provide a method.

According to the present invention including the above-described configuration, the following effects can be obtained.

First, according to the present invention, the first conductive film, which is part of the floating gate, is formed to have a negative slope (a structure having an upper width smaller than a lower width), the width of which is increased toward the bottom, in comparison with the vertical structure. It is possible to improve the membrane embedding characteristics.

Second, according to the present invention, the coupling ratio can be improved by increasing the surface area of the floating gate by forming the second conductive film in the form of a spacer on both side walls of the first conductive film.

Third, according to the present invention, by forming wing spacers between neighboring floating gates, inter-cell interference effects can be prevented, thereby improving cycling characteristics of the device.

Hereinafter, with reference to the accompanying drawings, the most preferred embodiment of the present invention will be described. In addition, in the drawings, the thicknesses and spacings of layers and regions are exaggerated for ease of explanation and clarity, and where layers are referred to as being on or above other layers, regions or substrates. It may be formed directly on another layer, region or substrate, or a third layer may be interposed therebetween. In addition, the parts denoted by the same reference numerals throughout the specification represent the same layer, and when the reference numerals include the English, it means that the same layer is partially modified through an etching or polishing process.

Example

1A to 1G are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with an embodiment of the present invention. Here, a method of manufacturing a NAND flash memory device is shown as an example.

First, as shown in FIG. 1A, triple n-type wells (not shown) and p-type wells (not shown) in a semiconductor substrate 100, such as a p-type substrate, are shown. To form.

Subsequently, an ion implantation step for adjusting the threshold voltage is performed.

Subsequently, a tunnel insulating film 101 is formed on the substrate 100. In this case, the tunnel insulating film 101 is formed of an oxide film, for example, silicon oxide film (SiO ₂ ), or after the silicon oxide film is formed, a heat treatment process using nitrogen (N ₂ ) gas is performed to nitride the silicon oxide film and the substrate 100 at an interface. Further layers may be formed. In addition, the metal oxide layer may be formed of, for example, an aluminum oxide film (Al ₂ O ₃ ), a zirconium oxide film (ZrO ₂ ), a hafnium oxide film (HfO ₂ ), or a mixture (or lamination) film having a dielectric constant of 3.9 or more. The manufacturing method may be a dry oxidation, a wet oxidation process or an oxidation process using radical ions. However, in terms of characteristics, the dry oxidation and wet oxidation process may be performed instead of the oxidation process using radical ions. desirable. In addition, the tunnel insulating film 101 can be formed to a thickness of about 50 ~ 100Å.

Subsequently, a floating gate conductive film 102 (hereinafter referred to as a first conductive film) is formed on the tunnel insulating film 101. In this case, the first conductive film 102 is formed of a conductive material. For example, the polysilicon film may be formed of any one material selected from a polysilicon film, a transition metal, and a rare earth metal, but is preferably formed of a polysilicon film that is easily etched. The polysilicon film is formed by a low pressure chemical vapor deposition (LPCVD) method, and at this time, a silane (SiH ₄ ) gas is used as the source gas. In addition, phosphine (PH ₃ ) is used as the doping gas for doping impurities. As the transition metal, iron (Fe), cobalt (Co), tungsten (W), nickel (Ni), palladium (Pd), platinum (Pt), molybdenum (Mo) or titanium (Ti) and the like are used. Erbium (Er), Ytterium (Yb), Samarium (Sm), Yttrium (Y), Lanthanum (La), Cerium (Ce), Terbium (Tb), Dysprosium (Dy), Holmium (Ho), and Tolium ( Tm), lutetium (Lu) and the like.

Subsequently, a hard mask (not shown) may be formed on the first conductive film 102. In this case, the hard mask is formed of a material having a high etching selectivity with the first conductive layer 102. For example, when the first conductive film 102 is formed of a polycrystalline silicon film, the first conductive film 102 is formed of a nitride film such as silicon nitride film (Si ₃ N ₄ ). In addition, the hard mask may be formed in a laminated structure in which a nitride film (silicon nitride film), an oxide film (silicon oxide film), and an oxynitride film (silicon oxynitride film, SiON) are stacked.

Meanwhile, a buffer film (not shown) may be further formed on the first conductive film 102 before the hard mask is formed. In this case, the buffer film is formed of a silicon oxide film.

Subsequently, as shown in FIG. 1B, the hard mask (if formed), the buffer film (if formed), the first conductive film 102A, the tunnel insulating film 101A, and the substrate 100A are partially etched. The trench 103 is formed. At this time, in the etching process, the first conductive layer 102A is etched to have a negative slope that increases in width toward the bottom (substrate direction), so that an interval between adjacent first conductive layers 102A is greater than the lower portion. It is preferable to etch to be wider. To this end, the etching process proceeds under conditions in which a large amount of polymer is generated. For example, a gas containing fluorine, that is, a mixed gas (CF ₄ / O ₂ ) or sulfur hexafluoride (SF ₆ ) gas of carbon tetrafluorocarbon (CF ₄ ) and oxygen (O ₂ ) is used. In the case of using CF ₄ / O ₂ , oxygen combines with carbon to increase the concentration of active species of fluorine. Therefore, by adjusting the amount of oxygen appropriately, the etching rate can be controlled, and the polymer is generated. The time that can be controlled can be controlled to form a profile with a negative slope. In addition, it is preferable to control the pressure during the process to about 155 ~ 160mTorr.

Subsequently, as shown in FIG. 1C, an insulating film (not shown) for an isolation layer is formed over the entire structure such that the trench 103 (see FIG. 1B) is embedded. In this case, the insulating film for the isolation layer is formed of a USG (Un-doped Silicate Glass) film (hereinafter referred to as HDP film) using the HDP-CVD (High Density Plasma-Chemical Vapor Deposition) method having excellent embedding characteristics even at a high aspect ratio In addition, the HDP film and the SOD (Spin On Dielectric) film may be formed in a stacked structure. In this case, the SOD film may be a PSZ (polisilazane) film.

Subsequently, the insulating film for device isolation film is planarized. In this case, the planarization process may be performed by an etching process using a plasma etch apparatus, for example, an etch back process, or a chemical mechanical polishing (CMP) process. For example, during the planarization process, the hard mask is used as an etch stop film (or a polishing stop film).

Subsequently, the device isolation film 104 is formed by recessing the insulating film for the device isolation film to a predetermined depth to control the EFH. In this case, the etching process may be performed only on the cell region in which the memory cell is formed, and the photoresist pattern in which only the cell region is opened except for the peripheral circuit region—the region in which the driver circuits such as a decoder and page buffer are formed. Is performed by a wet etching process or a dry etching process using the etching mask so that the top surface of the device isolation layer 104 is positioned at a height of 350 to 400 占 으로부터 from the top surface of the substrate (ie, the active region) 100A.

Subsequently, a cleaning process may be performed using an etching solution capable of etching the insulating film for device isolation films. In this case, the washing process may be performed using a BOE (Buffered Oxide Etchant) solution-a solution in which HF and NH ₄ F are mixed-or a diluted HF (DHF) solution-HF solution diluted in deionized water. The device isolation film 104 is partially etched so that the upper surface is located at a height of 200 to 250 microns from the upper surface of the substrate (ie, the active region) 100A, and at the same time, the conductive film 102B is also partially wet-etched so that It is rounded together.

Subsequently, as illustrated in FIG. 1D, a conductive film 105 (hereinafter referred to as a second conductive film) is formed in a liner form along the upper surface of the structure including the device isolation film 104. In this case, the second conductive layer 105 may be formed of any one material selected from conductive materials. Preferably, the substrate is formed of the same material as the first conductive film 102B in consideration of the contact resistance characteristic of the first conductive film 102B. More preferably, it is formed of a polycrystalline silicon film having excellent coating properties. At this time, the thickness of the second conductive film 105 may be formed to 100 ~ 150Å.

For example, when the second conductive film 105 is formed of a polysilicon film, the polysilicon film may be formed by LPCVD, or after the amorphous silicon film is deposited, a temperature range in which the amorphous silicon film may be polycrystalline, for example, 600 ° C. or more. It may be formed by polycrystallization through a heat treatment process performed at a temperature. Specifically, in the case of the LPCVD method is carried out at a temperature of 625 ~ 630 ℃. Amorphous silicon film is formed at a temperature of 520 ~ 530 ℃, heat treatment process using a furnace (furnace) equipment or RTP (Rapid Temperature Process) equipment.

Subsequently, as illustrated in FIG. 1E, an anisotropic dry etching process using plasma etching equipment, such as an etch back process, may be performed on the second conductive layer 105 (see FIG. 1D). Spacers 105A are formed on both side walls of the conductive film 102B. In this case, the etch back process may be performed such that the etching is stopped when the device isolation layer 104 is exposed as the etch barrier layer, or when the device isolation layer 104 is exposed, the thickness and the etching conditions of the etching time-second conductive layer 105 are preset. May be implemented based on a predetermined time.

Subsequently, as shown in FIG. 1F, the spacer 105A is etched using the etching barrier layer to recess the exposed device isolation layer 104A to a predetermined depth. As a result, the wing spacers A are formed. At this time, the recessed depth of the device isolation film 104A may be determined according to the characteristics of the device, but is preferably formed to a depth of 100 ~ 150Å. In addition, the etching process for the recess is performed by a dry etching process, for example, a blanket process.

Subsequently, as illustrated in FIG. 1G, a cleaning process may be performed before the subsequent dielectric film forming process to remove foreign substances such as etching residues generated in the previous process. In this case, the washing process may be performed using a BOE (Buffered Oxide Etchant) solution-a solution of HF and NH ₄ F mixed-or a diluted HF (DHF) solution-HF solution diluted in deionized water, this cleaning process Through the wing spacer (A, see FIG. 1F) is formed so that the upper corner portion is rounded to have a 'U' shape at the same time based on the height (H) of the wing spacer (A)-recess bottom of the device isolation film 104B The height to the top surface is 200 ~ 250Å.

Subsequently, a dielectric film 106 is formed along the upper surface of the structure including the wing spacers A (see FIG. 1F). At this time, the dielectric film 106 is formed in a stacked structure in which an oxide film-nitride film-oxide film is sequentially stacked. In addition, the dielectric constant of the silicon oxide film, that is, the metal oxide higher than 3.9, for example, aluminum oxide film (Al ₂ O ₃ ), zirconium oxide film (ZrO ₂ ), hafnium oxide film (HfO ₂ ), a laminated film or a mixture thereof Can be formed into a mixed film

Next, a control gate conductive film 107 (hereinafter referred to as a third conductive film) is formed on the dielectric film 106. In this case, the third conductive film 107 may be formed of any one material selected from conductive materials, and is preferably formed of the same material as the first conductive film 102B.

Subsequently, a metal nitride film, a metal silicide layer or a laminated film thereof, and a hard mask may be further formed on the third conductive film 107. For example, a tungsten nitride film WN is formed as a metal nitride film, and a tungsten silicide layer Wsi is formed as a metal silicide layer.

Since the process is the same as the general process, a description thereof will be omitted.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In particular, in the embodiment of the present invention, the manufacturing method of the NAND flash memory device has been described as an example, but it can be applied to the manufacturing method of all nonvolatile memory devices including the NOR flash memory device. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1A to 1G are cross-sectional views illustrating a method of manufacturing the nonvolatile memory device of the present invention.

<Explanation of symbols for main parts of drawing>

100, 100A: semiconductor substrate

101, 101A: tunnel insulation film

102, 102A, 102B: first conductive film

103: trench

105, 105A: second conductive film

106: dielectric film

107: third conductive film

A: Wing spacer

Claims (15)

Forming a tunnel insulating film and a first conductive film on the substrate; Forming a trench by partially etching the first conductive layer, the tunnel insulating layer, and the substrate; Forming an isolation layer to partially fill the trench; Forming a spacer including a second conductive film on both sidewalls of the first conductive film; Forming a wing spacer by partially recessing the device isolation layer using the spacer as an etch barrier layer; Forming a dielectric film along an upper surface of the structure including the wing spacers; And Forming a third conductive film on the dielectric film Method of manufacturing a nonvolatile memory device comprising a. The method of claim 1, The forming of the trench may be performed such that a lower width of the first conductive layer has a negative slope larger than an upper width. The method of claim 1, Forming the device isolation layer, Forming an insulating film for a device isolation layer to fill the trench; Planarizing the insulating film for the device isolation film; And Recessing the insulating film for the device isolation layer so that both sidewalls of the first conductive film are partially exposed Method of manufacturing a nonvolatile memory device comprising a. The method of claim 3, wherein And recessing the insulating film for the device isolation layer is performed by a wet etching process or a dry etching process. The method of claim 3, wherein And recessing the insulating film for the device isolation layer so that an upper surface of the insulating film for the device isolation film is positioned higher than an upper surface of the substrate. The method of claim 1, After forming the device isolation layer, A method of manufacturing a nonvolatile memory device further comprising the step of performing a cleaning process. The method of claim 6, The cleaning process is a method of manufacturing a non-volatile memory device so that the upper surface of the device isolation layer is positioned higher than the upper surface of the substrate. The method of claim 1, Forming the spacers, Forming the second conductive film along an upper surface of the structure including the device isolation film; And Etching back the second conductive layer Method of manufacturing a nonvolatile memory device comprising a. The method of claim 1, And the second conductive film is formed of the same material as the first conductive film. The method of claim 1, And the second conductive film is formed of a polysilicon film. The method of claim 10, The polycrystalline silicon film is formed by a low pressure chemical vapor deposition (LPCVD) method or a method of manufacturing a non-volatile memory device by forming an amorphous silicon film and then performing a heat treatment process to polycrystalline. The method of claim 11, The heat treatment process is a manufacturing method of a nonvolatile memory device using a furnace equipment or RTP (Rapid Temperature Process) equipment. The method of claim 1, After forming the wing spacers, A method of manufacturing a nonvolatile memory device further comprising the step of performing a cleaning process. The method of claim 1, The forming of the trench may be performed by a dry etching process using a mixed gas of fluorine-containing gas and oxygen. The method of claim 1, After forming the first conductive film, The method of claim 1, further comprising forming a hard mask on the first conductive layer.

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