KR20090073456A - Apparatus of flat panel display device and driving method thereof - Google Patents

Abstract

A flat panel display device and a driving method thereof are provided to decrease the electro-magnetic interference by reducing the number of synchronizing signal related transmit lines. A flat panel display(100) comprises a display panel, a video card(110), a timing controller(120), a gate driver integrated circuit and a data driver integrated circuit(130). The display panel indicates the video signal in pixel regions. The pixel regions are defined into the gate lines and the data lines. The video card supplies the source video data, and the synchronizing signal and system synchronous signal of source video data. The system synchronous signal is inserted into the blank time of the synchronizing signal. The timing controller arranges the control signal and the source video data of the video card with conversion. The timing controller outputs the system synchronous signal in the blank time of video data with insertion. The gate driver integrated circuit supplies the gate drive signal to the gate line. The data driver integrated circuit supplies the video data to the data lines. The driving method of the flat panel display is performed to reduce the electro-magnetic interference.

Description

Flat panel display and driving method {APPARATUS OF FLAT PANEL DISPLAY DEVICE AND DRIVING METHOD THEREOF}

The present invention relates to an interface device for synchronizing a system between a master and a slave, and a driving method thereof. In particular, a flat panel display device inserts and transmits a sync signal in a blank section of a data signal, thereby transmitting a sync signal. The present invention relates to an interface device of a flat panel display device and a method of driving the same, which can reduce the number of devices and thereby improve the performance of the flat panel display device.

As a flat panel display that displays an image using digital data, a liquid crystal display (LCD) using liquid crystal, a plasma display panel (PDP) using an inert gas discharge, and an organic light emitting diode Organic light emitting diode (OLED) display devices are typical.

In order to display high quality images, such flat panel displays are increasing in data transmission volume as they become larger and larger in size.

In order to express high resolution images using such a large amount of data

The master system transmitting data and the slave system receiving data from the master must be synchronized exactly. To this end, a high frequency synchronization signal is transmitted and received through a separate transmission line.

1 is a diagram illustrating a flat panel display including an interface device for system synchronization between a master and a slave according to the prior art. 1 illustrates a liquid crystal display among various flat panel displays.

Referring to FIG. 1, a flat panel display device 1 according to the related art includes a pixel area formed for each area defined by a plurality of gate lines GL1 to GLm and a plurality of data lines DL1 to DLn. A display panel (not shown) representing an image signal to be displayed; and a video card for supplying source image data of an image represented by the display panel, synchronization signals (Hsync, Vsync, DE) of the source image data, and system synchronization signal (DCLK). 10, the control signals (Hsync, Vsync, DE) and the source image data input from the video card 10 are converted and aligned, and supplied to the data driver 30, and the gate driver 40 and the data driver 30. Timing controller 20 for controlling driving of the < RTI ID = 0.0 >), gate driver IC 40 for sequentially supplying gate driving signals to a plurality of gate lines GL1 to GLm < / RTI > And a data driver IC 30 for supplying the image data input from the plurality of controllers 20 to the plurality of data lines DL1 to DLn in synchronization with the gate driving signal.

Here, the timing controller 20 aligns the system synchronization signal DCLK, the control signals Hsync, Vsync, DE, and the source image data input from a master system such as the video card 10 in units of frames. The video data of the aligned frame unit is supplied to the data driver IC 30.

In addition, the timing controller 20 uses the dot clock DLCK, the data enable signal DE, and the horizontal and vertical synchronization signals Hsync and Vsync input from the master system 10 and the data control signal DCS. The gate control signal GCS is generated to control driving timing of each of the data driver IC 30 and the gate driver IC 40.

Here, the data control signal DCS includes a source shift clock (SSC), a source start pulse (SSP), a polarity control signal (Polarity: POL), and a source output signal (Source Output Enable: SOE). And the like.

In addition, the gate control signal GCS includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable GOE, and the like.

The gate driver IC 40 sequentially applies the gate driving signal to the gate lines GL1 to GLm in response to the gate control signal GCS input from the timing controller 20, thereby providing the respective gate lines GL1 to GLm. The TFT connected to) is turned on. In this case, the gate driver IC 40 determines the high level voltage and the low level voltage of the gate driving signal according to the input gate high voltage VGH and the gate low voltage VGL.

In response to the data control signal DCS supplied from the timing controller 20, the data driver IC 30 outputs an analog image data signal corresponding to a line corresponding to the data line DL1 through the cycle in which the gate driving signal is supplied. DLn). At this time, the data driver IC 30 inverts the polarity of the analog image data signal supplied to the data lines DL1 to DLn in response to the polarity control signal POL.

As shown in FIG. 1, when the timing controller 20 is used as a reference, various control signals for representing source image data of an image represented by a display panel, such as a video card, and source image data on the display panel, as image data; The apparatus for generating and transmitting the system synchronization signal is the master system 10, and the timing controller 20 receiving the source image data, the synchronization signal of the image data, and the synchronization signal of the system from the master system 10 becomes a slave system. .

Meanwhile, since the timing controller 20 supplies the image data, the control signal, and the system synchronization signal to the data drive IC 30 and the gate drive IC 40, the timing controller 20 becomes a master system at this time, and the data drive IC 30 and the gate drive IC 40 becomes a slave system.

Such a master system and a slave system must be accurately synchronized in order to express high quality images on the display panel. When the synchronization is not achieved between the master system and the slave system, since the source image data input from the video card 10 cannot be represented as an image on the display panel, the synchronization between the master system and the slave system is the performance of the flat panel display device. Will have a profound effect on

To this end, a synchronization signal for synchronizing the system is transmitted and received using a separate transmission line between the master system and the slave system. However, the system synchronization signal has a different frequency depending on the flat panel display, but usually 10 MHz to 300 MHz.

Since the high frequency system synchronization signal is always output at the same frequency through separate transmission pins and lines, there is a problem that a lot of electromagnetic interference (hereinafter referred to as EMI) is generated inside the system. In particular, the EMI problem is mainly generated at the digital interface between the timing controller 20 and the data drive IC 30 of the flat panel display, causing unstable driving of the flat panel display, thereby degrading the performance of the flat panel display.

The flat panel display according to the related art transmits and receives a high frequency system synchronization signal through a separate transmission pin and a transmission line for synchronization between a master system and a slave system. The high frequency system synchronization signal has a problem in that a lot of electromagnetic interference (hereinafter referred to as EMI) is generated inside the system because the high frequency signal is always output at the same frequency. In particular, the EMI problem is mainly generated at the digital interface between the timing controller of the flat panel display and the data drive IC, causing unstable driving of the flat panel display, thereby degrading the performance of the flat panel display.

To this end, the flat panel display according to an exemplary embodiment of the present invention includes an image signal input including a pixel area formed for each area defined by a plurality of gate lines GL1 to GLm and a plurality of data lines DL1 to DLn. And a video card for supplying a source image data of the image represented by the display panel and a synchronization signal of the source image data and a system synchronization signal inserted in a blank section of the synchronization signal, from the video card. A timing controller for converting and aligning input control signals and source image data, inserting and outputting a system synchronization signal in a blank section of the image data, and a plurality of gate lines formed in the display panel according to control of the timing controller ( A gate driver IC for sequentially supplying a gate driving signal to GL1 to GLm), and And a data driver IC configured to supply the image data input based on the system synchronization signal input from the timing controller to the plurality of data lines DL1 to DLn to be synchronized with the gate driving signal.

According to an aspect of the present invention, there is provided a method of driving a flat panel display device, the method comprising: detecting an error of a system clock between a master system and a slave system; Generating a voltage value corresponding to an error value of a system clock, generating a new system clock corresponding to the voltage value, and placing the new system clock in a blank period of a signal for which no valid signal is generated for a predetermined time period. And inserting the new system clock into the slave system through a transmission line of a signal in which the valid signal is not generated.

The flat panel display according to the embodiment of the present invention can reduce the generation of EMI generated by the high-frequency system synchronization signal by synchronizing the master system and the slave system without a separate line. Through this, the digital interface between the timing controller of the flat panel display and the data drive IC is mainly generated, thereby preventing the unstable driving of the flat panel display, thereby improving the performance of the flat panel display.

Other features and advantages of the present invention in addition to the above features will be apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

FIG. 2 is a diagram illustrating a flat panel display including an interface device for system synchronization between a master and a slave according to an exemplary embodiment of the present invention. 2 illustrates an example of a liquid crystal display among various flat panel displays.

Referring to FIG. 2, the flat panel display device 100 according to an exemplary embodiment may include a pixel area formed for each area defined by a plurality of gate lines GL1 to GLm and a plurality of data lines DL1 to DLn. A display panel (not shown) representing an input image signal, and a video card supplying source image data of an image represented by the display panel, synchronization signals (Hsync, Vsync, DE) of the source image data, and a system synchronization signal ( 110, the control signals (Hsync, Vsync, DE) and source image data input from the video card 110 are converted and aligned and supplied to the data driver 130, and the gate driver 140 and the data driver 130. Timing controller 120 for controlling the driving of the?), Gate driver IC 140 sequentially supplying the gate driving signal to the plurality of gate lines GL1 to GLm formed on the display panel, and the other To synchronize the image data input from the Ming controller 120 to the gate drive signal is configured to include a data driver IC (130) for supplying a plurality of data lines (DL1 to DLn).

Here, the timing controller 120 arranges control signals (Hsync, Vsync, DE) and source image data input from a master system such as the video card 110 in units of frames, and arranges images in units of frames. The data is supplied to the data driver IC 130.

The flat panel display apparatus 100 according to an exemplary embodiment of the present invention applies a system synchronization signal SP to a blank period of a data enable signal DE input from a video card 110 to a timing controller 120. Insert and send

In addition, the timing controller 120 is inserted into a blank period of the data enable signal DE, the horizontal / vertical synchronization signals Hsync and Vsync, and the data enable signal DE input from the master system 110 and input. The data control signal DCS and the gate control signal GCS are generated using the system synchronization signal SP to control driving timing of each of the data driver IC 130 and the gate driver IC 140.

Here, the data control signal DCS includes a source shift clock (SSC), a source start pulse (SSP), a polarity control signal (Polarity: POL), and a source output signal (Source Output Enable: SOE). And the like.

In addition, the gate control signal GCS includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable GOE, and the like.

The gate driver IC 140 sequentially applies the gate driving signal to the gate lines GL1 to GLm in response to the gate control signal GCS input from the timing controller 120, thereby providing the respective gate lines GL1 to GLm. The TFT connected to) is turned on. In this case, the gate driver IC 140 determines the high level voltage and the low level voltage of the gate driving signal according to the input gate high voltage VGH and the gate low voltage VGL.

The data driver IC 130 receives a gate driving signal in response to a system synchronization signal SP inserted into a blank period of the data control signal DCS and the image data RGB DATA supplied from the timing controller 120. The analog image data signal corresponding to the line is supplied to the data lines DL1 to DLn every supplied period. In this case, the data driver IC 130 inverts the polarity of the analog image data signal supplied to the data lines DL1 to DLn in response to the polarity control signal POL.

The flat panel display device 100 according to an exemplary embodiment of the present invention is a line for transmitting a system synchronization signal provided for system synchronization between a master system and a slave system in the flat panel display device 1 according to the related art shown in FIG. 1. It does not have.

The flat panel display 100 according to an exemplary embodiment uses a transmission line of the data enable signal DE input from the video card 110 to the timing controller 120, and transmits the data enable signal DE. By inserting and transmitting the system synchronization signal SP in a blank time in which no valid signal is generated among the signals, the system between the video card 110 and the timing controller 120 is synchronized.

In addition, the system synchronization signal SP between the timing controller 120 and the data drive IC 130 uses an image data signal line input from the timing controller 120 to the data drive IC 130, and the data drive IC 130. The system synchronizes the system between the timing controller 120 and the data drive IC 130 by inserting and transmitting a system synchronization signal SP in a blank period in which valid image data is not generated.

To this end, the video card 110 and the timing controller 120 are provided with a system synchronizer 200, as shown in FIG.

The system synchronizer 200 inputs from a sync signal generator 210 and a sync signal generator 210 which generates a source sync signal as a reference for system sync between a master system and a slave system and supplies the same to the detector 220. A detection unit 220 which detects a synchronization error between the source synchronization signal and the system synchronization signal fed back from the slave system, generates a detection signal corresponding to a match or a mismatch between the two signals, and supplies the detection signal to the conversion unit 230; A system synchronization signal using the conversion unit 230 for converting the source synchronization signal according to the detection signal input from the detection unit 220 to the clock generator 240 and the source synchronization signal input from the conversion unit 230. And a clock generator 240 for generating the SSP and transmitting the generated new system synchronization signal SP to the slave 250.

As shown in FIG. 4, the flat panel display may cause an error in the system clock between the master system and the slave system due to various factors.

The flat panel display 100 according to an exemplary embodiment of the present invention detects an error of a system clock between a master system and a slave system by using the system synchronizer 200 illustrated in FIG. 3, and corrects an error of the detected system clock. By generating a new system synchronization signal (SP) to synchronize the master system and the slave system.

In more detail, as shown in FIG. 3, the synchronization signal generator 210 of the system synchronizer 200 generates a source synchronization signal as a reference for system synchronization between the master system and the slave system. The source synchronization signal is transmitted to the detector 220.

The detector 220 compares the phase of the source synchronization signal input from the synchronization signal generator 210 with the system synchronization signal SP fed back from the slave system.

The detector 220 first detects whether there is an error in the phases of the two signals, as shown in FIG. 4. If there is no error between the phases of the two signals, the detector 220 retransmits the system synchronization signal SP fed back from the slave system to the slave system.

On the other hand, as shown in Figure 4 between the phase of the two signals input to the detector 220, if there is an error (error) generates an error signal corresponding to the error value of the two signals, and generates the generated error signal Transmission to the conversion unit 230.

The converter 230 converts an error value between two signal phases input from the detector 220 to a voltage V corresponding thereto, and transmits the converted voltage to the clock generator 240.

Here, for example, when the fed back system synchronization signal is delayed than the source synchronization signal, a positive voltage V value corresponding to the delayed time is generated, and vice versa. When the system synchronization signal becomes faster than the source synchronization signal, a negative voltage V value corresponding to the faster time is generated.

The clock generator 240 generates a new system synchronization signal SP and supplies it to the slave system according to the magnitude of the positive (+) voltage (V) value input from the converter 230. do.

In this case, the system synchronization signal SP supplied to the slave system uses a line through which a data enable signal DE is transmitted when the master system is a video card and the slave system is a timing controller. Likewise, a newly generated system synchronization signal is inserted and transmitted to the timing controller in a period where the data enable signal DE is blank for a predetermined time.

Since the flat panel display device according to an embodiment of the present invention does not use a separate transmission line for system synchronization, a new system synchronization protocol (protocal) is used for accurate synchronization between the master system and the slave system by using the existing transmission line. Must be provided.

Such a system synchronization protocol can be freely designed, for example, the data enable signal DE corresponding to the third Vsync period among the data enable signals DE in which blanks are generated during five Vsync periods. It is possible to synchronize the master system and the slave system through the protocol to insert the system synchronization signal (SP) in the blank period of the transmission.

On the other hand, when the master system is a timing controller and the slave system is a data drive IC, as shown in the description of FIG. 5, the system synchronization signal SP is inserted into the blank period of the data enable signal DE, the RGB image data. The system synchronization signal may be inserted and transmitted in a section in which any one image data is blank for a predetermined time. In this case, a new protocol is provided between the timing controller and the data drive IC to synchronize the system according to the provided protocol.

Through such a configuration and driving method, the flat panel display device according to an exemplary embodiment of the present invention can reduce the generation of EMI generated by the high frequency system synchronization signal by synchronizing the master system and the slave system without a separate line. Through this, the digital interface between the timing controller of the flat panel display and the data drive IC is mainly generated, thereby preventing the unstable driving of the flat panel display, thereby improving the performance of the flat panel display.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 illustrates a flat panel display including an interface device for system synchronization between a master and a slave according to the prior art.

2 is a diagram illustrating a flat panel display including an interface device for system synchronization between a master and a slave according to an embodiment of the present invention.

3 is a diagram illustrating a system synchronizer for system synchronization between a master and a slave.

4 illustrates a method of performing system synchronization between a master and a slave.

5 shows the synchronization of the system using the data enable signal DE input from the video card to the timing controller.

<Brief description of symbols for the main parts of the drawings>

100: flat panel display 110: video card

120: timing controller 130: data drive IC

140: gate drive IC 200: system synchronization unit

210: sync signal generator 220: detector

230: converter 240: clock generator

Claims (8)

A display panel representing an input image signal including a pixel area formed for each of the areas defined by the plurality of gate lines GL1 to GLm and the plurality of data lines DL1 to DLn; A video card for supplying a source image data of the image represented by the display panel and a synchronization signal of the source image data together with a system synchronization signal inserted into a blank section of the synchronization signal; A timing controller for converting and aligning control signals and source image data input from the video card, and inserting and outputting a system synchronization signal in a blank section of the image data; A gate driver IC sequentially supplying a gate driving signal to the plurality of gate lines GL1 to GLm formed on the display panel under the control of the timing controller; And a data driver IC for supplying image data input based on the system synchronization signal input from the timing controller to the plurality of data lines DL1 to DLn to be synchronized with the gate driving signal. Device. The method of claim 1, The video card and the timing controller may include a synchronization signal generation unit configured to generate and supply a source synchronization signal as a reference for system synchronization between a master system and a slave system; A detector for detecting a synchronization error between the source synchronization signal input from the synchronization signal generator and a system synchronization signal fed back from a slave system, and generating a detection signal corresponding to a match or a mismatch between the two signals; A converting unit converting the source synchronizing signal into a predetermined voltage (V) value according to the detection signal input from the detecting unit; And a system synchronizer configured to generate a signal clock corresponding to a voltage value input from the converter and supply the signal clock to the slave system. The method of claim 2, And the detection unit compares a phase of a source synchronization signal input from the synchronization signal generator and a system synchronization signal SP fed back from the slave system. The method of claim 3, wherein The detector generates an error signal corresponding to an error value of two signals when an error occurs between a source sync signal input from the sync signal generator and a phase of a system sync signal SP fed back from the slave system. Flat panel display device. The method of claim 4, wherein And the system synchronization signal is inserted in a blank period of the data enable signal (DE) and transmitted to the slave system through a line through which the data enable signal (DE) is transmitted. The method of claim 4, wherein And the system synchronization signal is inserted in a blank period of the image data signal and transmitted to the slave system through a line through which the image data is transmitted. In a driving method of a flat panel display for synchronizing a master system and a slave system, Detecting an error in the system clock between the master system and the slave system; Generating a voltage value corresponding to an error value of the detected system clock; Generating a new system clock corresponding to the voltage value; Inserting the new system clock into a blank period of a signal for which no valid signal is generated for a predetermined time; And transmitting the new system clock to the slave system through a transmission line of a signal for which the valid signal has not been generated. The method of claim 7, wherein And the signal generating the blank period is a data enable signal or an image data signal.

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