KR20090072872A - Liquid crystal display and driving method thereof - Google Patents

Abstract

A liquid crystal display and a driving method thereof are provided to minimize the irregular smudge by suppressing the direct current mobilization of the liquid crystal cell. A liquid crystal display comprises an LCD panel, a data driving circuit(12), a gate driving circuit(13) and a timing controller(11). The LCD panel has liquid crystal cells. The liquid crystal cell has a data line(14) and a gate line(15) intersecting the data line. The data driving circuit responds to the polarity control signal. The data driving circuit transforms the digital video data(RGB) and the black data into the positive polarity and the negative polarity gamma compensation voltage. The gate driving circuit responds to the gate timing control signal. The gate driving circuit supplies the gate pulse to the gate line. The timing controller controls data driving circuit by generating the data timing control signal including the polarity control signal(POL). The timing controller controls the gate driving circuit.

Description

Liquid Crystal Display and Driving Method

The present invention relates to a liquid crystal display device and a driving method thereof which can be driven by an impulse method and prevent irregular irregularities.

The liquid crystal display of the active matrix driving method displays a moving image using a thin film transistor (hereinafter referred to as TFT) as a switching element. The liquid crystal display device can be miniaturized compared to a cathode ray tube (CRT), which is applied to a display device in portable information equipment, office equipment, computer, etc., and is also rapidly replaced by a cathode ray tube.

As shown in FIG. 1, a liquid crystal display device actively controls data by switching data voltages supplied to liquid crystal cells using thin film transistors (TFTs) formed in each liquid crystal cell (Clc), thereby improving display quality of moving images. Can be. In FIG. 1, reference numeral “Cst” denotes a storage capacitor Cst for maintaining a data voltage charged in a liquid crystal cell Clc, “DL” denotes a data line to which a data voltage is supplied, and “GL”. Denotes a gate line to which a scan voltage is supplied.

Irregular spots may appear in the display image of the liquid crystal display. When a DC voltage of the same polarity is applied to the liquid crystal layer for a long time, impurity ions in the liquid crystal layer are divided along the polarity of the liquid crystal, and ions having different polarities are accumulated in the pixel electrode and the common electrode in the liquid crystal cell. When a direct current voltage is applied to the liquid crystal layer for a long time, the alignment film deteriorates while the accumulation amount of ions increases, and as a result, the alignment characteristic of the liquid crystal deteriorates. For this reason, when the DC voltage is applied to the liquid crystal display for a long time, irregular irregularities occur. In order to improve the problem of irregular irregularities, a method of developing a liquid crystal material having a low dielectric constant or improving an alignment material or an alignment method has been devised. However, this method requires a lot of time and cost to develop the material, and lowering the dielectric constant of the liquid crystal may cause another problem that the driving characteristics of the liquid crystal deteriorate. Experimentally found that the appearance time of the irregular stain is faster the more impurities ionized in the liquid crystal layer and the larger the acceleration factor. Acceleration factors include temperature, time, and direct drive of liquid crystals. Therefore, the irregular spots appear faster as the temperature is applied or the longer the DC voltage of the same polarity is applied to the liquid crystal layer, the worse it becomes. Since irregular smears appear irregularly even among panels manufactured through the same manufacturing line, a method of suppressing direct current driving of liquid crystals is most effective because it cannot be solved only by new material development or process improvement method.

In the liquid crystal display, a blurring phenomenon in which a screen is not clear and blurry appears in a moving image due to the retention characteristics of the liquid crystal. The CRT emits phosphor for only a very short time to display data in a cell, and then displays an image by impulse driving without emitting light in the cell. In contrast, the liquid crystal display displays an image by a hold driving in which data is supplied to the liquid crystal cell during the scanning period and then the data charged in the liquid crystal cell is maintained for the remaining field period (or frame period).

Since the video displayed on the CRT is displayed by impulse driving, the perceived image felt by the viewer is clear. On the other hand, in the LCD, the contrast of the perceptual image felt by the viewer due to the retention characteristics of the liquid crystal in the moving image is not clearly seen but blurred. This difference in perceptual image is due to the integration effect of the image which persists temporarily in the eye following the movement. Therefore, even though the response speed of the liquid crystal display is fast, the viewer sees a blurred screen due to a mismatch between the eye movement and the static image of each frame. In order to improve such a motion blur phenomenon in the liquid crystal display, it is necessary to apply an impulse driving method to the liquid crystal display.

Accordingly, an object of the present invention is to provide a liquid crystal display device and a method of driving the same, which can be driven in an impulse manner and prevents irregular irregularities.

In order to achieve the above object, a liquid crystal display device according to an embodiment of the present invention includes a liquid crystal display panel including a plurality of data lines and a plurality of gate lines intersecting the liquid crystal cells arranged in a matrix form; Data driving circuit for converting digital video data and black data into positive / negative gamma compensation voltage in response to the polarity control signal to supply positive / negative data voltage and positive / negative black gray voltage to the data lines. in; A gate driving circuit supplying a gate pulse to the gate lines in response to the gate timing control signal; And a timing controller generating a data timing control signal including the polarity control signal to control the data driving circuit and generating a gate timing control signal to control the gate driving circuit.

And the liquid crystal cells charge the black gray voltage of the negative polarity during the N + 1th frame period after the black gray voltage of the negative polarity is charged during the N (N is an integer) frame period. .

The polarity control signal is generated in low logic for every black data after being latched in the data driving circuit for the Nth frame period, and high for every black data after being latched in the data driving circuit for the N + 1th frame period. It is generated by logic.

The polarity control signal is inverted by approximately one horizontal period during the digital video data during the Nth frame period and remains the same low logic for approximately two horizontal periods synchronized with the black data and the digital video data preceding it. The phase of the N + 1th frame period is generated in an inverse phase with the phase of the Nth frame period.

A method of driving a liquid crystal display according to an exemplary embodiment of the present invention includes generating a data timing control signal including a gate timing control signal and a polarity control signal; Converting the digital video data and the black data into a positive / negative gamma compensation voltage in response to the polarity control signal to supply a positive / negative data voltage and a positive / negative black gray voltage to the data lines. ; And supplying a gate pulse to the gate lines in response to the gate timing control signal.

The liquid crystal cells charge the negative black gray voltage during the N (N is an integer) frame period, and then charge the negative black gray voltage during the N + 1 th frame period.

According to an exemplary embodiment of the present invention, a liquid crystal display device and a driving method thereof perform impulse driving by charging black data, and modulate the polarity control signal from the black data to invert the polarity of the black data every frame to drive the direct current of the liquid crystal cell. It can be suppressed to minimize irregular stains.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 1 to 9.

Referring to FIG. 8, the liquid crystal display according to the exemplary embodiment of the present invention includes a liquid crystal display panel, a timing controller 11, a data driving circuit 12, and a gate driving circuit 13. The data driver circuit 12 includes a plurality of source drive ICs. The gate driving circuit 13 includes a plurality of gate drive ICs 131 to 135.

In a liquid crystal display panel, a liquid crystal layer is formed between two glass substrates. The liquid crystal display panel includes m × n liquid crystal cells Clc arranged in a matrix by a cross structure of m data lines 14 and n gate lines 15.

Data lines 14, gate lines 15, TFTs, and a storage capacitor Cst are formed on the lower glass substrate of the liquid crystal display panel. The liquid crystal cells Clc are connected to the TFT and are driven by an electric field between the pixel electrodes 1 and the common electrode 2. The black matrix, the color filter, and the common electrode 2 are formed on the upper glass substrate of the liquid crystal display panel. Meanwhile, the common electrode 2 is formed on the upper glass substrate in a vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, in plane switching (IPS) mode, and fringe field switching (FFS). In the horizontal electric field driving method as in the mode, the pixel electrode 1 is formed on the lower glass substrate. Polarizing plates having optical axes orthogonal to each other are attached on the upper glass substrate and the lower glass substrate of the liquid crystal display panel, and an alignment layer for setting a pre-tilt angle of the liquid crystal is formed at an interface in contact with the liquid crystal.

The display screen of the liquid crystal display panel is divided into a plurality of blocks BL1 to BL5 according to gate timing control signals applied to the gate drive ICs 131 to 135. These blocks BL1 to BL5 are sequentially driven in order of data display, data retention, and black insertion when the black data insertion ratio BDI% is less than 20%. Also, the blocks BL1 to BL5 are sequentially driven in the order of data display, data retention, black insertion and black retention when the black data insertion ratio BDI% is 20% or more.

The timing controller 11 receives a timing signal such as a vertical / horizontal synchronization signal (Vsync, Hsync), a data enable signal (Data Enable), a dot clock signal (DCLK), and a fixed clock signal (FCLK). 12) and control signals for controlling the operation timing of the gate driving circuit 13. These control signals include a gate timing control signal and a data timing control signal. The timing controller 11 also supplies digital video data RGB and black data to the data driving circuit 12. In the data stream transmitted from the timing controller 11 to the data driving circuit 12, one black data is inserted between k (k is an integer of 2 or more) digital video data RGB. To this end, the timing controller 11 uses the memory to delay the digital video data RGB and generates "00000000", that is, black data and inserts the black data between the digital video data.

The gate timing control signal includes a gate start pulse (GSP), a gate shift clock signal (GSC), a gate output enable signal (Gate Output Enable, GOE), and the like.

The gate start pulse GSP is applied to the first gate drive IC 131 to indicate a start line at which the scan starts so that the first gate pulse is generated from the first gate drive IC 131. The gate shift clock signal GSC is a clock signal for shifting the gate start pulse GSP. The shift registers of the gate drive ICs 131 to 135 shift the gate start pulse GSP and the gate pulse to the next stage at the rising edge of the gate shift clock signal GSC. The second to fifth gate drive ICs 132 to 135 receive the final output of the previous gate drive IC as the gate start pulse GSP to generate the first gate pulse. The gate output enable signal GOE is separately applied to the gate drive ICs 131 to 135. The gate drive ICs 131 to 135 output the gate pulse for the low logic period of the gate output enable signal GOE, that is, immediately after the polling time of the previous pulse to just before the rising time of the next pulse. The gate drive ICs 131 to 135 do not generate gate pulses during the high logic period of the gate output enable signal GOE.

The data timing control signal includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (POL), and a source output enable signal (SOE). It includes. The source start pulse SSP indicates a start pixel on one horizontal line in which data is to be displayed. The source sampling clock SSC instructs the latch operation of data in the data driving circuit 12 based on the rising or falling edge. The polarity control signal POL controls the polarity of the analog video data voltage output from the data driving circuit 12. Pulses of the polarity control signal POL are synchronized with the digital video data RGB and the black data after the latch in the data driving circuit 12. The pulse of the polarity control signal POL synchronized with the black data has the same logic value for one frame period, while the logic value is inverted every frame. The source output enable signal SOE controls the output of the source drive IC.

Each of the data drive ICs of the data driver circuit 12 includes a shift register, a latch, a digital-to-analog converter, an output buffer, and the like. The data driving circuit 12 latches the digital video data RGB and the black data under the control of the timing controller 11. The data driving circuit 12 supplies the charge share voltage to the data lines 14 in response to the source output enable signal SOE, and then the digital video data RGB and the black in response to the polarity control signal POL. The data is converted into an analog positive / negative gamma compensation voltage to generate a positive / negative analog data voltage and a black gray voltage, and the voltages are supplied to the data lines 14. Here, the data driving circuit 12 converts the digital video data RGB or the black data into the positive gamma compensation voltage during the high logic period of the polarity control signal POL, while the low logic period of the polarity control signal POL is used. While converting digital video data (RGB) or black data into negative gamma compensation voltage. The data driving circuit 12 supplies a data voltage to the data lines 14 during the scan time of the blocks BL1 to BL5 driven by the data display block, and supplies the data voltages to the data lines 14 and the blocks BL1 to BL5 driven by the black insertion block. The black gray voltage is supplied to the data lines 14 during the scan time.

The data driving circuit 12 converts the black data into a gamma compensation voltage of one polarity during the odd frame period and the black data into a gamma compensation voltage of the opposite polarity during the even frame period in response to the polarity control signal POL. . Therefore, since the direct current is suppressed by the black gray voltage in which all the liquid crystal cells of one screen are reversed in polarity every frame, the appearance of irregular irregularities can be minimized.

Each of the gate drive ICs 131 to 135 has a shift register, a level shifter for converting an output signal of the shift register into a swing width suitable for TFT driving of a liquid crystal cell, and an output buffer connected between the level shifter and the gate line 15. Each includes. The gate drive ICs 131 to 135 sequentially supply gate pulses to the gate lines 15 in response to gate timing control signals. The gate drive ICs 131 to 135 data the blocks BL1 to BL5 by the gate start pulse GSP of the gate timing control signal and the gate output enable signals GOE1 to GOE5 that vary according to the frame frequency. It is driven by the display block, the data holding block, the black insertion block and the black holding block.

FIG. 2 is a waveform diagram illustrating a gate timing control signal shown in FIG. 1. 3 shows a gate timing control signal for controlling the gate drive ICs 131 to 135 in charge of the data display block, and a gate timing control signal for controlling the gate drive ICs 131 to 135 in charge of the black display block. It is a waveform diagram.

2 and 3, the gate start pulse GSP may include a first pulse P1 for controlling a scanning start point of a block in which a video data voltage is charged, and a scanning start point of a block in which a black gray voltage is charged. It includes a second pulse (P2) for controlling the.

The pulse width of the first pulse P1 is approximately one horizontal period, and the pulse width of the second pulse P2 is approximately k horizontal periods. The gate drive ICs 131 to 135 sequentially shift the first pulse P1 according to the gate shift clock GSC. The blocks BL1 to BL5 at which scanning is started by the gate drive ICs 131 to 135 which start to operate in response to the first pulse P1 are driven to the data display blocks. In blocks BL1 to BL5 driven by the data display block, gate pulses are sequentially applied to the gate lines line by line.

In addition, the gate drive ICs 131 to 135 sequentially shift the second pulse P2 according to the gate shift clock GSC. The blocks BL1 to BL5 that charge the black gray voltage by the gate drive ICs 131 to 135 that start to operate in response to the second pulse P2 are driven by black insertion blocks. In the blocks BL1 to BL5 driven by the black insertion block, the gate pulses partially overlap with each other according to a correlation between the second pulse P2 having a wide pulse width and the gate shift clock GSC generated in a period of approximately one horizontal period. For example, in blocks BL1 to BL5 driven by the black insertion block, the gate pulse applied to the i (i is an integer) th gate line and the gate pulse applied to the i + 1 th gate line partially overlap each other. N gate pulses sequentially applied to the data display blocks BL1 to BL5 by the gate output enable signals GOE1 to GOE5 separately applied to the gate drive ICs 131 to 135, and then black. N gate pulses are simultaneously applied to the insertion blocks BL1 to BL5, and then N gate pulses are sequentially applied to the data display blocks BL1 to B5 again. By repeating this operation, the gate drive ICs 131 to 135 in charge of the data display block and the gate drive ICs 131 to 135 in charge of the black insertion block alternately apply gate pulses.

The gate output enable signals GOE1 to GOE5 are sequentially shifted. The gate output enable signals GOE1 to GOE5 are in charge of the first section T1 for controlling the output of the gate drive ICs 131 to 135 that are in charge of the data display block, on / off, and the data retention block. A second section T2 that blocks the output of the gate drive ICs 131 to 135 and a gate output of the gate drive ICs 131 to 135 that are in charge of the black insertion block. It includes a third section (T3).

During the first period T1 of the gate output enable signals GOE1 to GOE5, the timing controller 11 generates pulses of the gate output enable signals GOE1 to GOE5 at every rising time of the gate start pulse GSC. . The gate tribe ICs 131 to 135 in charge of the data display block generate gate pulses during the low logic period between the pulses. Accordingly, during the first period T1, the gate drive ICs 131 to 135 in charge of the data display block shift the gate start pulse GSP at every rising time of the gate shift clock GSC to gate pulses on the gate lines. Are applied sequentially. The data drive ICs 131 to 135 supply analog data voltages to the data lines in synchronization with gate pulses applied to the data display block. Thus, the liquid crystal cells of the data display block charge the analog data voltage.

During the second period T2 of the gate output enable signals GOE1 to GOE5, the timing controller 11 generates the gate output enable signals GOE1 to GOE5 as high logic DC voltages. Therefore, the gate drive ICs 131 to 135 in charge of the data display block do not generate gate pulses. During this second period T2, the data drive ICs output an analog data voltage to be displayed on another data display block and a black gray voltage to be charged in the liquid crystal cells of the black display block.

During the third period T3 of the gate output enable signals GOE1 to GOE5, the timing controller 11 performs a gate in charge of the black display block while gate pulses are sequentially applied to four gate lines in the data display block. The pulses of the gate output enable signals GOE1 to GOE5 are generated in the drive ICs 131 to 135 with a pulse width of approximately N horizontal periods. In the example of FIG. 3, the pulse widths of the gate output enable signals GOE1 to GOE5 that control the output of the gate drive ICs 131 to 135 that are in charge of the black display block are four horizontal periods. As a result, the gate drive ICs 131 to 135 that are in charge of the black display block during the third period T3 do not output the gate pulse, and the gate pulses are sequentially applied to the gate lines of the data display block during the period. do. On the other hand, the gate drive ICs 131 to 135 in charge of the black display block do not output the gate pulse during this period, but the shift register therein follows the gate start pulse GSP and the gate start pulse for approximately four horizontal periods. I shift to the stage. Following a pulse having a pulse width of four horizontal periods, the timing controller 11 maintains the gate output enable signals GOE1 to GOE5 at a low logic voltage for approximately one horizontal period. At this time, the gate drive ICs 131 to 135 in charge of the black display block simultaneously output shifted gate pulses on four lines while partially overlapping in the internal shift registers, and the data drive ICs output the gate pulses to the gate pulses. Simultaneously outputs the synchronized black gradation voltage.

4 and 5 are waveform diagrams showing the data timing control signal for controlling the data driving circuit 12 and the output waveform of the data driving circuit 12 in the odd frame period and the even frame period. Fig. 6 is a waveform diagram showing the polarity control signal divided into odd frame period and even frame period. FIG. 7 is a waveform diagram illustrating a data voltage and a black gray voltage charged in one liquid crystal cell during multiple frame periods.

4 to 7, the timing controller 11 generates pulses of the source output enable signal SOE at approximately one horizontal period interval, and is approximately one horizontal period relative to the source output enable signal SOE. The polarity control signal POL is generated later. The data driving circuit 12 latches the digital video data RGB and the black data from the timing controller 11 for one horizontal period, and then stores the latched data in response to the polarity control signal POL. Convert to polar analog gamma compensation voltage.

As shown in FIGS. 4 and 6, the polarity control signal POL is inverted in units of one horizontal period in synchronization with the data voltages during the Nth frame period, and is fixed at low logic at the black gray voltage. Subsequently, as shown in FIGS. 5 and 6, the polarity control signal POL is generated while the phase is inverted from the N th frame period during the N + 1 th frame period so that the logic is performed in units of one horizontal period in synchronization with the data voltages. Inverted and fixed to high logic at the black gradation voltage. The polarity control signal POL has the same logic value for approximately two horizontal periods synchronized with the black data and the preceding digital video data while the logic is reversed in units of approximately one horizontal period while the digital video data is continuous.

In the Nth frame period, the digital video data RGB to be charged in the data display block has a positive analog gamma compensation voltage and a negative analog gamma such that its polarity is reversed in units of one horizontal period in response to the polarity control signal POL. The black gradation voltage to be charged to the black display block is alternately converted into the negative analog gamma compensation voltage in response to the polarity control signal POL. In the N + 1th frame period, the digital video data RGB to be charged in the data display block is converted into an analog gamma compensation voltage having a polarity opposite to that of the data voltage charged in the Nth frame period. The black gray voltage to be charged is converted only to the positive analog gamma compensation voltage in response to the polarity control signal POL. Therefore, the liquid crystal cells charge the negative black gray voltage after charging the positive or negative data voltage during the Nth frame period as shown in FIG. 7, and then apply the positive or negative data voltage during the N + 1 th frame period. After charging, the positive black gray voltage is charged.

4 to 7, the liquid crystal display according to the exemplary embodiment of the present invention charges all liquid crystal cells with a black gray voltage whose polarity is reversed in units of one frame period. As a result, the liquid crystal display of the present invention is driven in an impulse manner and does not cause a motion blur phenomenon, and direct current driving is suppressed so that irregular irregularities do not appear.

FIG. 8 shows voltages charged in five blocks BL1 to BL5 which are dividedly driven by the gate drive ICs 131 to 135 during the odd frame period.

Referring to FIG. 8, if the screen is driven to be divided into five blocks BL1 to BL5 by the five gate drive ICs 131 to 135, the blocks BL1 to BL5 are divided into five subframes during one frame period. Time division driving is performed in the frame periods SF1 to SF5.

The timing controller 11 applies a first of the gate start pulse GSP to the first gate drive IC 131 that is in charge of the first block BL1 at the same time as the start of the first sub frame period SF1 of the Nth frame period. The first interval signal T1 of the pulse P1 and the first gate output enable signal GOE1 is supplied. At this time, the time difference between the first pulse P1 and the second pulse P2 of the gate start pulse GSP is approximately 4 sub frame periods. The gate start pulse GSP generated during the N−1 th frame period is shifted to the second gate drive IC 132 via the first gate drive IC 131. Therefore, at the same time as the start of the first subframe SF1 of the Nth frame period, the second gate drive IC 132 transmits the second pulse P2 and the second gate output enable signal GOE2 of the gate start pulse GSP. Is supplied with the third section signal T3.

During the first sub frame period SF1 of the N-th frame period, the first block BL1 may have a first period between the first pulse P1 of the gate start pulse GSP and the first gate output enable signal GOE. Scanning is performed by the gate pulses sequentially generated line by line in accordance with the signal T1 to charge the positive / negative analog data voltages from the data drive ICs. The second block BL2 is applied to the gate pulses overlapped by N lines according to the second pulse P2 of the gate start pulse GSP and the third interval signal T3 of the second gate output enable signal GOE2. Being scanned to charge the negative black gradation voltage from the data drive ICs. The third block BL3 is in the third sub frame period SF3 of the N-1 th frame period according to the second period signal T2 of the third gate output enable signal GOE, which blocks the output of the gate pulse. The charged positive / negative analog data voltage is maintained. The fourth block BL4 is disposed in the fourth sub frame period SF4 of the N-1 th frame period according to the second interval signal T2 of the third gate output enable signal GOE, which blocks the output of the gate pulse. The charged positive / negative analog data voltage is maintained. The fifth block BL5 is disposed in the fifth sub frame period SF5 of the N-1 th frame period according to the second interval signal T2 of the fifth gate output enable signal GOE5 that blocks the output of the gate pulse. The charged positive / negative analog data voltage is maintained. Accordingly, during the first sub frame period SF1, the first, third to fifth blocks BL1, BL3, BL4, and BL5 are driven by data display blocks that charge or maintain the positive / negative data voltages. The two blocks BL2 are driven by a black display block that charges the negative black gray voltage.

During the second sub-frame period SF2 of the N-th frame period, the first block BL1 may be formed in accordance with the second period signal T2 of the first gate output enable signal GOE1 that blocks the output of the gate pulse. The positive / negative analog data voltage charged in one sub frame period SF1 is maintained. The second block B1 is a gate pulse sequentially generated by one line according to the first pulse P1 of the gate start pulse GSP and the first interval signal T1 of the second gate output enable signal GOE2. Scans the data and charges the positive / negative analog data voltages from the data drive ICs. The third block B3 is applied to the gate pulses overlapped by N lines according to the second pulse P2 of the gate start pulse GSP and the third interval signal T3 of the third gate output enable signal GOE. Being scanned to charge the negative black gradation voltage from the data drive ICs. The fourth block BL4 is applied to the fourth sub frame period SF4 of the N-1 th frame period according to the second period signal T2 of the fourth gate output enable signal GOE4 that blocks the output of the gate pulse. The charged positive / negative analog data voltage is maintained. The fifth block BL3 is in the fifth sub frame period SF5 of the N-1 th frame period according to the second interval signal T2 of the fifth gate output enable signal GOE5 that blocks the output of the gate pulse. The charged positive / negative analog data voltage is maintained. Accordingly, the first, second, fourth, and fifth blocks BL1, BL2, BL4, and BL5 are driven by data display blocks that charge or maintain the positive / negative data voltages during the second sub frame period SF2. The third block BL3 is driven by a black display block that charges the negative black gray voltage.

During the third sub-frame period SF3 of the N-th frame period, the first block BL1 may be formed in accordance with the second interval signal T2 of the first gate output enable signal GOE1 that blocks the output of the gate pulse. The positive / negative analog data voltage charged in one sub frame period SF1 is maintained. The second block BL2 is charged in the second sub frame period SF2 according to the second period signal T2 of the second gate output enable signal GOE2 that blocks the output of the gate pulse. Maintain analog data voltage. The third block B3 is a gate pulse sequentially generated by one line according to the first pulse P1 of the gate start pulse GSP and the first interval signal T1 of the third gate output enable signal GOE. Are scanned by the device and charge the positive / negative analog data voltages from the data drive ICs. The fourth block B4 is disposed on the gate pulses overlapped by N lines according to the second pulse P2 of the gate start pulse GSP and the third interval signal T3 of the fourth gate output enable signal GOE. Being scanned to charge the negative black gradation voltage from the data drive ICs. The fifth block BL5 is disposed in the fifth sub frame period SF5 of the N-1 th frame period according to the second interval signal T2 of the fifth gate output enable signal GOE, which blocks the output of the gate pulse. The charged positive / negative analog data voltage is maintained. Accordingly, during the third sub frame period SF3, the first to third and fifth blocks BL1, BL2, BL3, and BL5 are driven by data display blocks that charge or maintain the positive / negative data voltages. The four blocks BL4 are driven by black display blocks that charge the negative black gray voltage.

During the fourth sub-frame period SF4 of the N-th frame period, the first block BL1 may be formed according to the second interval signal T2 of the first gate output enable signal GOE1 that blocks the output of the gate pulse. The positive / negative analog data voltage charged in one sub frame period SF1 is maintained. The second block BL2 is charged in the second sub frame period SF2 according to the second period signal T2 of the second gate output enable signal GOE2 that blocks the output of the gate pulse. Maintain analog data voltage. The third block BL3 is charged in the third sub frame period SF3 according to the second period signal T2 of the third gate output enable signal GOE, which blocks the output of the gate pulse. Maintain analog data voltage. The fourth block B4 is a gate pulse sequentially generated by one line according to the first pulse P1 of the gate start pulse GSP and the first interval signal T1 of the fourth gate output enable signal GOE4. Scans the data and charges the positive / negative analog data voltages from the data drive ICs. The fifth block B5 is connected to the gate pulses overlapped by N lines according to the second pulse P2 of the gate start pulse GSP and the third interval signal T3 of the fifth gate output enable signal GOE5. Being scanned to charge the negative black gradation voltage from the data drive ICs. Accordingly, the first to fourth blocks BL1 to BL4 are driven as data display blocks that charge or maintain the positive / negative data voltages during the fourth sub frame period SF4, and the fifth block BL5 is negative. It is driven by a black display block that charges the polarity black gradation voltage.

During the fifth sub frame period SF5 of the N-th frame period, the first block BL1 may include a third period of the second pulse P2 of the gate start pulse GSP and the first gate output enable signal GOE1. In response to the signal T3, the negative voltage is charged from the data drive ICs by scanning by gate pulses overlapping by N lines. The second block BL2 is charged in the second sub frame period SF2 according to the second period signal T2 of the second gate output enable signal GOE, which blocks the output of the gate pulse. Maintain analog data voltage. The third block BL3 is charged in the third sub frame period SF3 according to the second period signal T2 of the third gate output enable signal GOE, which blocks the output of the gate pulse. Maintain analog data voltage. The fourth block BL3 is charged in the fourth sub frame period SF4 according to the second period signal T2 of the fourth gate output enable signal GOE, which blocks the output of the gate pulse. Maintain analog data voltage. The fifth block B5 is a gate pulse sequentially generated by one line according to the first pulse P1 of the gate start pulse GSP and the first interval signal T1 of the fifth gate output enable signal GOE5. Scans the data and charges the positive / negative analog data voltages from the data drive ICs. Accordingly, the second to fifth blocks BL2 to BL5 are driven as data display blocks which charge or maintain the positive / negative data voltages during the fifth sub frame period SF5, and the first block BL1 is negative. It is driven by a black display block that charges the polarity black gradation voltage.

All of the liquid crystal cells of the liquid crystal display during the N + 1th frame period charge the positive black gray voltage after charging the data voltage of the opposite polarity to the data voltage charged in the Nth frame period.

9 shows voltages charged in the five blocks BL1 to BL5 that are dividedly driven by the gate drive ICs 131 to 135 during the even frame period.

Referring to FIG. 9, during the first sub frame period SF1 of the N + 1 th frame period, the first block BL1 may enable the first pulse P1 and the first gate output of the gate start pulse GSP. The positive / negative analog data voltages from the data drive ICs are charged while being scanned by gate pulses sequentially generated line by line according to the first interval signal T1 of the signal GOE. The second block BL2 is connected to the gate pulses overlapped by N lines according to the second pulse P2 of the gate start pulse GSP and the third interval signal T3 of the second gate output enable signal GOE2. Being scanned to charge the positive black gradation voltage from the data drive ICs. The third block BL3 is in the third sub frame period SF3 of the N-1 th frame period according to the second period signal T2 of the third gate output enable signal GOE, which blocks the output of the gate pulse. The charged positive / negative analog data voltage is maintained. The fourth block BL4 is disposed in the fourth sub frame period SF4 of the N-1 th frame period according to the second interval signal T2 of the third gate output enable signal GOE, which blocks the output of the gate pulse. The charged positive / negative analog data voltage is maintained. The fifth block BL5 is disposed in the fifth sub frame period SF5 of the N-1 th frame period according to the second interval signal T2 of the fifth gate output enable signal GOE5 that blocks the output of the gate pulse. The charged positive / negative analog data voltage is maintained. Accordingly, during the first sub frame period SF1, the first, third to fifth blocks BL1, BL3, BL4, and BL5 are driven by data display blocks that charge or maintain the positive / negative data voltages. The two blocks BL2 are driven by a black display block that charges the positive black gray voltage.

During the second sub frame period SF2 of the N + 1 th frame period, the first block BL1 is applied to the second interval signal T2 of the first gate output enable signal GOE1 that blocks the output of the gate pulse. Accordingly, the positive / negative analog data voltage charged in the first sub frame period SF1 is maintained. The second block B1 is a gate pulse sequentially generated by one line according to the first pulse P1 of the gate start pulse GSP and the first interval signal T1 of the second gate output enable signal GOE2. Scans the data and charges the positive / negative analog data voltages from the data drive ICs. The third block B3 is applied to the gate pulses overlapped by N lines according to the second pulse P2 of the gate start pulse GSP and the third interval signal T3 of the third gate output enable signal GOE. Scanned by to charge the positive black gradation voltage from the data drive ICs. The fourth block BL4 is applied to the fourth sub frame period SF4 of the N-1 th frame period according to the second period signal T2 of the fourth gate output enable signal GOE4 that blocks the output of the gate pulse. The charged positive / negative analog data voltage is maintained. The fifth block BL3 is in the fifth sub frame period SF5 of the N-1 th frame period according to the second interval signal T2 of the fifth gate output enable signal GOE5 that blocks the output of the gate pulse. The charged positive / negative analog data voltage is maintained. Accordingly, the first, second, fourth, and fifth blocks BL1, BL2, BL4, and BL5 are driven by data display blocks that charge or maintain the positive / negative data voltages during the second sub frame period SF2. The third block BL3 is driven by a black display block that charges the positive black gray voltage.

During the third sub frame period SF3 of the N + 1 th frame period, the first block BL1 is connected to the second interval signal T2 of the first gate output enable signal GOE1 that blocks the output of the gate pulse. Accordingly, the positive / negative analog data voltage charged in the first sub frame period SF1 is maintained. The second block BL2 is charged in the second sub frame period SF2 according to the second period signal T2 of the second gate output enable signal GOE2 that blocks the output of the gate pulse. Maintain analog data voltage. The third block B3 is a gate pulse sequentially generated by one line according to the first pulse P1 of the gate start pulse GSP and the first interval signal T1 of the third gate output enable signal GOE. Scans the data and charges the positive / negative analog data voltages from the data drive ICs. The fourth block B4 includes gate pulses overlapped by N lines according to the second pulse P2 of the gate start pulse GSP and the third interval signal T3 of the fourth gate output enable signal GOE. Is scanned by to charge the positive black gradation voltage from the data drive ICs. The fifth block BL5 is disposed in the fifth sub frame period SF5 of the N-1 th frame period according to the second interval signal T2 of the fifth gate output enable signal GOE, which blocks the output of the gate pulse. The charged positive / negative analog data voltage is maintained. Accordingly, during the third sub frame period SF3, the first to third and fifth blocks BL1, BL2, BL3, and BL5 are driven by data display blocks that charge or maintain the positive / negative data voltages. The four blocks BL4 are driven by black display blocks that charge the positive black gradation voltages.

During the fourth sub frame period SF4 of the N + 1 th frame period, the first block BL1 is connected to the second interval signal T2 of the first gate output enable signal GOE1 that blocks the output of the gate pulse. Accordingly, the positive / negative analog data voltage charged in the first sub frame period SF1 is maintained. The second block BL2 is charged in the second sub frame period SF2 according to the second period signal T2 of the second gate output enable signal GOE2 that blocks the output of the gate pulse. Maintain analog data voltage. The third block BL3 is charged in the third sub frame period SF3 according to the second period signal T2 of the third gate output enable signal GOE, which blocks the output of the gate pulse. Maintain analog data voltage. The fourth block B4 is a gate pulse sequentially generated by one line according to the first pulse P1 of the gate start pulse GSP and the first interval signal T1 of the fourth gate output enable signal GOE4. Scans the data and charges the positive / negative analog data voltages from the data drive ICs. The fifth block B5 is connected to the gate pulses overlapped by N lines according to the second pulse P2 of the gate start pulse GSP and the third interval signal T3 of the fifth gate output enable signal GOE5. Being scanned to charge the positive black gradation voltage from the data drive ICs. Accordingly, during the fourth sub frame period SF4, the first to fourth blocks BL1 to BL4 are driven as data display blocks which charge or maintain the positive / negative data voltages, and the fifth block BL5 is positive. It is driven by a black display block that charges the polarity black gradation voltage.

During the fifth sub frame period SF5 of the N + 1 th frame period, the first block BL1 is configured to include the second pulse P2 of the gate start pulse GSP and the first gate output enable signal GOE1. In response to the three-section signal T3, the gate pulses are overlapped by N lines to charge the positive black gray voltages from the data drive ICs. The second block BL2 is charged in the second sub frame period SF2 according to the second period signal T2 of the second gate output enable signal GOE, which blocks the output of the gate pulse. Maintain analog data voltage. The third block BL3 is charged in the third sub frame period SF3 according to the second period signal T2 of the third gate output enable signal GOE, which blocks the output of the gate pulse. Maintain analog data voltage. The fourth block BL3 is charged in the fourth sub frame period SF4 according to the second period signal T2 of the fourth gate output enable signal GOE, which blocks the output of the gate pulse. Maintain analog data voltage. The fifth block B5 is a gate pulse sequentially generated by one line according to the first pulse P1 of the gate start pulse GSP and the first interval signal T1 of the fifth gate output enable signal GOE5. Scans the data and charges the positive / negative analog data voltages from the data drive ICs. Accordingly, the second to fifth blocks BL2 to BL5 are driven to the data display block for charging or maintaining the positive / negative data voltage during the fifth sub frame period SF5, and the first block BL1 is positive. It is driven by a black display block that charges the polarity black gradation voltage.

According to another exemplary embodiment of the present invention, a liquid crystal display and a driving method thereof invert the polarity control signal POL in units of approximately two horizontal periods while digital video data are continuously driven to drive the liquid crystal cells in a vertical two dot inversion manner. And generate the polarity control signal with the same logic value for approximately three horizontal periods synchronized with the black data and the two preceding digital video data.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a block diagram illustrating a liquid crystal display device according to an exemplary embodiment of the present invention.

FIG. 2 is a waveform diagram illustrating a gate timing control signal shown in FIG. 1.

3 is a waveform diagram showing in detail a gate timing control signal shown in FIG. 8 in a data display block and a black display block;

4 and 5 are waveform diagrams showing data timing control signals for controlling the data driving circuit 12 and output waveforms of the data driving circuit in odd frame periods and even frame periods;

Fig. 6 is a waveform diagram showing the polarity control signal divided into odd frame period and even frame period.

7 is a waveform diagram illustrating a data voltage and a black gray voltage charged in one liquid crystal cell during multiple frame periods.

8 and 9 illustrate voltages charged in liquid crystal cells for each block in odd frame periods and even frame periods.

<Explanation of symbols for main parts of drawing>

11: Timing Controller 12: Data Driving Circuit

13 gate driving circuit

Claims (6)

A liquid crystal display panel including liquid crystal cells intersecting a plurality of data lines and a plurality of gate lines and arranged in a matrix form; Data driving circuit for converting digital video data and black data into positive / negative gamma compensation voltage in response to the polarity control signal to supply positive / negative data voltage and positive / negative black gray voltage to the data lines. in; A gate driving circuit supplying a gate pulse to the gate lines in response to the gate timing control signal; And A timing controller generating a data timing control signal including the polarity control signal to control the data driving circuit and generating a gate timing control signal to control the gate driving circuit; And the liquid crystal cells charge the negative black gray voltage during the N (N is an integer) frame period, and then charge the negative black gray voltage during the N + 1 th frame period. . The method of claim 1, The polarity control signal, Low logic is generated for each black data after being latched in the data driving circuit for the Nth frame period, And high logic for each black data after being latched in the data driving circuit during the N + 1th frame period. The method of claim 2, The polarity control signal, During the Nth frame period, the digital video data is inverted in approximately one horizontal period unit while being continuous, and maintained at the same low logic for approximately two horizontal periods synchronized with the black data and digital video data preceding it. And a phase inverted from a phase during the Nth frame period during the N + 1th frame period. A driving method of a liquid crystal display device comprising a liquid crystal display panel including liquid crystal cells in which a plurality of data lines and a plurality of gate lines intersect and are arranged in a matrix form. Generating a data timing control signal including a gate timing control signal and a polarity control signal; Converting the digital video data and the black data into a positive / negative gamma compensation voltage in response to the polarity control signal to supply a positive / negative data voltage and a positive / negative black gray voltage to the data lines. ; And Supplying a gate pulse to the gate lines in response to the gate timing control signal, And the liquid crystal cells charge the negative black gray voltage during the N (N is an integer) frame period, and then charge the negative black gray voltage during the N + 1 th frame period. Driving method. The method of claim 4, wherein The polarity control signal, Low logic is generated for every black data after being latched in the data driving circuit for the Nth frame period, And a high logic for each black data after being latched in the data driving circuit during the N + 1th frame period. The method of claim 5, wherein The polarity control signal, During the Nth frame period, the digital video data is inverted in approximately one horizontal period unit while being continuous, and maintained at the same low logic for approximately two horizontal periods synchronized with the black data and digital video data preceding it. And a phase inverted from a phase during the Nth frame period during the N + 1th frame period.

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