KR101446349B1 - Liquid Crystal Display and Driving Method thereof - Google Patents

Abstract

The present invention relates to a liquid crystal display device driven by an impulse method and a driving method thereof.

This liquid crystal display device includes a liquid crystal display panel in which a plurality of data lines and a plurality of gate lines are intersected and divided into k (k is a natural number of 2 or more) blocks; A gate driving circuit having k gate drive ICs formed on the liquid crystal display panel and supplying gate pulses to the gate lines of the k blocks independently; A data driving circuit for supplying an analog data voltage and a black gradation voltage to the data lines; And a timing controller for generating a data timing control signal for controlling the operation timing of the data driving circuit and generating a gate timing control signal for controlling the operation timing of the gate drive ICs driven independently of each other .

Impulse, Motion Blur, Gate Start Pulse, Independent, Split

Description

[0001] The present invention relates to a liquid crystal display and a driving method thereof,

The present invention relates to a liquid crystal display device driven by an impulse method and a driving method thereof.

A liquid crystal display device of an active matrix driving type displays a moving picture by using a thin film transistor (hereinafter referred to as "TFT") as a switching element. This liquid crystal display device can be downsized as compared with a cathode ray tube (CRT), and is applied to a display device in a portable information device, an office machine, a computer, etc., and is rapidly applied to a television, thereby rapidly replacing a cathode ray tube.

In the liquid crystal display device, a blurring phenomenon appears in which blurring appears in the moving image due to the retention characteristics of the liquid crystal. The CRT emits phosphors only for a very short time as shown in FIG. 1 to display data on a cell, and then displays an image in impulse driving without light emission in the cell. On the other hand, the liquid crystal display displays an image in a hold drive in which data charged in the liquid crystal cell is held for the remaining field period (or frame period) after data is supplied to the liquid crystal cell during the scanning period as shown in FIG.

Since the moving picture displayed on the CRT is displayed by impulse driving, the perceived image of the viewer is sharpened as shown in FIG. On the other hand, in the liquid crystal display device, due to the retention characteristic of the liquid crystal in the moving image, the contrast of the perception image felt by the spectator is blurred as shown in Fig. The difference of these perceptual images is due to the integration effect of the images which are temporally continuous in the eye following the movement. Therefore, even if the response speed of the liquid crystal display device is fast, the viewer will see a blurred image due to mismatch between the eye movement and the static image of each frame. In order to improve the motion blur phenomenon, a black data insertion method (Black Data Insertion) (BDI) is used to impulse drive a liquid crystal display device by displaying video data on a screen and then supplying black data to the screen. Has been proposed.

The display screen is divided into a plurality of blocks and is divided and driven, and each block is operated in the order of data voltage charging (write), data voltage holding (hold), and black data inserting. The black data insertion method uses a gate output enable signal independently applied to each block in order to divide and drive the display screen into a plurality of blocks. In other words, the black data insertion method independently applies the first gate output enable signal to the data voltage charging block to generate the gate pulse supplied to the block to which the data voltage is to be charged, and supplies the block to be inserted with the black data Independently applies a second gate output enable signal to the black data insertion block to generate a gate pulse.

On the other hand, in order to simplify the module process, a GIP (Gate In Panel) method in which a gate drive integrated circuit (IC) is directly mounted on a lower glass substrate of a liquid crystal display panel using an A-Si TFT Have recently been proposed. In this GIP type liquid crystal display device, there is no gate output enable signal for controlling the output of the gate pulse.

Therefore, in order to impulse drive through inserting the black data, the gate pulse must be individually controlled by the gate output enable signal independently applied to each display block. In the liquid crystal display of the GIP system, It is not suitable for impulse driving through inserting black data because an abble signal is not used.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a liquid crystal display device and a method of driving the same that enable impulse driving through a black data insertion method in a liquid crystal display of a GIP system.

According to an aspect of the present invention, there is provided a liquid crystal display device including: a liquid crystal display panel in which a plurality of data lines and a plurality of gate lines are intersected and divided into k blocks (k is a natural number of 2 or more) blocks; A gate driving circuit having k gate drive ICs formed on the liquid crystal display panel and supplying gate pulses to the gate lines of the k blocks independently; A data driving circuit for supplying an analog data voltage and a black gradation voltage to the data lines; And a timing controller for generating a data timing control signal for controlling the operation timing of the data driving circuit and generating a gate timing control signal for controlling the operation timing of the gate drive ICs driven independently of each other .

And k is 4.

The gate timing control signal includes: a first gate start pulse indicating a start line from which a scan is started so that a first gate pulse is generated from a first one of the gate drive ICs; A second gate start pulse indicating a start line from which a scan is started so that a first gate pulse is generated from the second gate drive IC; A third gate start pulse indicating a start line from which a scan is started so that a first gate pulse is generated from the third gate drive IC; A fourth gate start pulse indicating a start line from which a scan is started so that a first gate pulse is generated from the fourth gate drive IC; And a gate shift clock signal for shifting the gate start pulses.

The first gate start pulse includes a 1-1 pulse (P1_black) and a 1-2 pulse (P1_black) generated after a period shorter than the 1/4 frame period (1V / 4) (P1_data); The second gate start pulse includes a second-first pulse P2_black and a second-second pulse (P2_black) generated after a period shorter than about a quarter frame period (1V / 4) P2_data); The third gate-start pulse includes a third-first pulse (P3_black) and a third-second pulse (P3_black) generated after a period shorter than the first-third pulse (P3_black) P3_data); The fourth gate start pulse includes a 4-1 pulse (P4_black) and a 4-2 pulse (P4_black) generated after a period shorter than the 1/4 frame period (1V / 4) P1_data).

The pulse width of the 1-1 pulse (P1_black) and the pulse width of the 1-2 pulse (P1_data) are approximately one horizontal period; The pulse width of the second-1 pulse (P2_black) and the pulse width of the second-second pulse (P2_data) are approximately one horizontal period, and the second-first pulse (P2_black) ) Is overlapped and is generated later than the first 1-2 pulse (P1_data); The pulse width of the 3-1 pulse (P3_black) and the pulse width of the 3-2 pulse (P3_data) are approximately one horizontal period, and the 3-1 pulse (P3_black) And the pulse width of the second-second pulse (P2_data) is approximately one horizontal (P2_data), and the pulse width of the fourth-first pulse (P4_black) Period, and the 4-1 pulse (P4_black) overlaps with the 3-2 pulse (P3_data) and is generated later than the 3-2 pulse (P3_data).

The first gate drive IC sequentially shifts the 1-1 pulse (P1_black) according to the gate shift clock signal to generate 1-1 gate pulses and sequentially supply the 1-1 gate pulses to the gate lines of the first block, Sequentially generates a 1-2 gate pulse by sequentially shifting the 1-2 pulse (P1_data) according to the gate shift clock signal, and sequentially supplies the 1-2 gate pulse to the gate lines of the first block; The second gate drive IC sequentially shifts the second-1 pulse (P2_black) according to the gate shift clock signal to sequentially generate 2-1 gate pulses to the gate lines of the second block, Sequentially generating 2-2 gate pulses by sequentially shifting the 2-2 pulses (P2_data) according to the gate shift clock signal, and sequentially supplying the 2-2 gate pulses to the gate lines of the second block; The third gate drive IC sequentially shifts the 3-1 pulse (P3_black) according to the gate shift clock signal to generate 3-1 gate pulses and sequentially supplies the 3-1 gate pulses to the gate lines of the third block, Sequentially generating a 3-2 gate pulse by sequentially shifting the 3-2 pulse (P3_data) according to the gate shift clock signal, and sequentially supplying the 3-2 gate pulse to the gate lines of the third block; The fourth gate drive IC sequentially shifts the 4-1 pulse (P4_black) according to the gate shift clock signal to generate 4-1 gate pulses and sequentially supplies the gate pulses to the gate lines of the fourth block, Sequentially shifts the 4-2 pulse (P4_data) according to the gate shift clock signal to generate a 4-2 gate pulse, and sequentially supplies the generated gate pulse to the gate lines of the fourth block.

The first and second gate pulses are synchronized with the analog data voltage supplied from the data driving circuit during a first sub frame period of one frame period, and the 2-1 gate pulse is synchronized with the black gradation voltage Lt; / RTI > The 2-2 gate pulse is synchronized with the analog data voltage supplied from the data driving circuit during the second sub frame period following the first sub frame period and the 3-1 gate pulse is synchronized with the analog data voltage supplied from the data driving circuit Synchronized with the black gradation voltage; The 3-2 gate pulse is synchronized with the analog data voltage supplied from the data driving circuit during the third sub frame period subsequent to the second sub frame period, and the 4-1 gate pulse is synchronized with the analog data voltage supplied from the data driving circuit Synchronized with the black gradation voltage; The 4-2 gate pulse is synchronized with the analog data voltage supplied from the data driving circuit during the fourth sub frame period subsequent to the third sub frame period, and the 1-1 gate pulse is synchronized with the analog data voltage supplied from the data driving circuit And is synchronized with the black gradation voltage.

During the first sub frame period, no gate start pulse is applied to the third gate drive IC and the fourth gate drive IC; During the second sub frame period, no gate start pulse is applied to the first gate drive IC and the fourth gate drive IC; During the third sub frame period, no gate start pulse is applied to the first gate drive IC and the second gate drive IC; During the fourth sub frame period, no gate start pulse is applied to the second gate drive IC and the third gate drive IC.

A liquid crystal display panel in which a plurality of data lines and a plurality of gate lines are intersected and divided into k blocks (k is a natural number of 2 or more) blocks according to an embodiment of the present invention, A gate driving circuit having k gate drive ICs for independently supplying gate pulses to the respective gate lines, and a driving circuit for driving the liquid crystal display having the data driving circuit for supplying the analog data voltage and the black gradation voltage to the data lines The method includes: generating a data timing control signal for controlling an operation timing of the data driving circuit; And generating gate timing control signals for controlling operation timings of the gate drive ICs driven independently of each other.

A liquid crystal display device and a driving method thereof according to the present invention independently supply gate start pulses to a plurality of gate drive ICs corresponding to each of a plurality of blocks of a liquid crystal display panel that is divided and driven, Data writing, data holding, and black insertion for each block can be performed independently to enable impulse driving.

Hereinafter, a preferred embodiment of the present invention will be described with reference to FIGS. 5 to 10D.

5 is a block diagram illustrating a liquid crystal display device according to an embodiment of the present invention. 6 is a detailed view of the gate drive circuit of FIG.

Referring to FIG. 5, a liquid crystal display device according to an embodiment of the present invention includes a liquid crystal display panel 80, a timing controller 81, a data driving circuit 82, and a gate driving circuit 83. The data driving circuit 82 includes a plurality of source drive ICs. The gate drive circuit 83 includes a plurality of gate drive ICs 831 to 834.

In the liquid crystal display panel, a liquid crystal layer is formed between two glass substrates. The liquid crystal display panel includes mxn liquid crystal cells Clc arranged in a matrix form by an intersection structure of m data lines 84 and n gate lines 85. [

Data lines 84, gate lines 85, TFTs, and a storage capacitor Cst are formed on the lower glass substrate of the liquid crystal display panel. The liquid crystal cells Clc are connected to the TFT and driven by the electric field between the pixel electrodes 1 and the common electrode 2. [ On the upper glass substrate of the liquid crystal display panel, a black matrix, a color filter, and a common electrode 2 are formed. The common electrode 2 is formed on an upper glass substrate in a vertical electric field driving method such as a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode. The IPS (In Plane Switching) mode and the FFS (Fringe Field Switching) Mode is formed on the lower glass substrate together with the pixel electrode 1 in the horizontal electric field driving method. On the upper glass substrate and the lower glass substrate of the liquid crystal display panel, a polarizing plate orthogonal to the optical axis is attached, and an alignment film is formed to set a pre-tilt angle of the liquid crystal at the interface with the liquid crystal.

The display screen of the liquid crystal display panel is dividedly driven into a plurality of blocks BL1 to BL4 according to a gate timing control signal applied to the gate drive ICs 831 to 834. [ The blocks BL1 to BL4 are sequentially driven in the order of data writing, data holding, and black insertion.

The timing controller 81 receives a timing signal such as a vertical / horizontal synchronizing signal (Vsync, Hsync), a data enable signal (Data Enable) and a dot clock signal (DCLK), and supplies the timing signal to the data driving circuit 82, Lt; RTI ID = 0.0 > 83 < / RTI > These control signals include a gate timing control signal and a data timing control signal. Further, the timing controller 81 supplies digital video data (RGB) to the data driving circuit 82.

The gate timing control signal includes a gate start pulse (GSP), a gate shift clock signal (GSC), and the like. The gate start pulse GSP includes the first gate start pulse to the fourth gate start pulse GSP1 to GSP4. On the other hand, the gate timing control signal does not include a gate output enable signal (GOE).

The first to fourth gate start pulses GSP1 to GSP4 are individually applied to the first to fourth gate drive ICs 831 to 834, respectively. The first gate start pulse GSP1 is applied to the first gate drive IC 831 to indicate the start line from which the scan is initiated so that the first gate pulse is generated from the first gate drive IC 831. The second gate start pulse GSP2 is applied to the second gate drive IC 832 to indicate the start line from which the scan is initiated so that the first gate pulse is generated from the second gate drive IC 832. The third gate start pulse GSP3 is applied to the third gate drive IC 833 to indicate the start line from which the scan starts so that the first gate pulse from the third gate drive IC 833 is generated. The fourth gate start pulse GSP4 is applied to the fourth gate drive IC 834 to indicate the start line from which the scan is started so that the first gate pulse is generated from the fourth gate drive IC 834.

The gate shift clock signal GSC is a clock signal for shifting the gate start pulses GSP1 to GSP4. The gate shift clock signal GSC is generated by a four-phase clock signal including four clocks Clk1 to Clk4 as shown in FIG. On the other hand, the gate shift clock signal GSC may be generated by a two-phase clock signal including two clocks or a three-phase clock signal including three clocks. The shift register of the gate drive ICs 831 to 834 generates a gate pulse during the high logic period of the gate shift clock signal GSC in synchronization with the rising edge of the gate shift clock signal GSC.

The data timing control signal includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (POL), and a BDI source output enable signal (SOEb) And the like. The source start pulse SSP indicates a starting pixel in one horizontal line where data is to be displayed. The source sampling clock SSC indicates the latching operation of data in the data driving circuit 82 based on the rising or falling edge. The polarity control signal POL controls the polarity of the analog video data voltage output from the data driving circuit 82. [ The BDI source output enable signal SOEb controls the output of the source drive IC.

Each of the data drive ICs of the data drive circuit 82 includes a shift register, a latch, a digital-analog converter, an output buffer, and the like. The data driving circuit 82 latches the digital video data RGB under the control of the timing controller 81. The data driving circuit 82 then supplies the black gradation voltage generated by the charge share voltage or the positive / negative precharge voltage to the data lines 84 and supplies the digital video data RGB to the polarity control signal POL ) To generate positive / negative polarity analog data voltages and supplies the data voltages to the data lines 84. The analog / The data driving circuit 82 supplies the data voltages to the data lines 84 during the scan time of the blocks BL1 to BL4 driven by the data writing block and supplies the data voltages to the data lines 84 of the blocks BL1 to BL4 And supplies black gradation voltages to the data lines 84 during the scan time.

Each of the gate drive ICs 831 to 834 is formed on the lower glass substrate of the liquid crystal display panel 80, including a shift register, and an output buffer connected between the shift register and the gate line 85, respectively.

The gate drive ICs 831 to 834 sequentially supply gate pulses to the gate lines 85 in response to gate timing control signals. These gate drive ICs 831 to 834 block the blocks BL1 to BL4 by the first to fourth gate start pulses GSP1 to GSP4 generated at approximately 1/4 frame intervals as a data write block, Block, and black insertion block.

The black gradation voltage supplied to the liquid crystal cells of the black insertion block may be generated in the timing controller 81 or the data driving circuit 82. [ The timing controller 81 inserts the digital black gradation data so as to synchronize with the scan time of the black insertion block between the digital video data RGB and the data driving circuit 82 converts the digital black gradation data into the analog black gradation voltage . ≪ / RTI >

7 is a waveform diagram showing the first to fourth gate-start pulses GSP1 to GSP4 shown in Fig. 8A to 8D show the gate timing control signals applied to the gate drive ICs for each block and the gate pulses generated from the gate drive ICs according to the subframe in FIG. 7, Timing control signals and analog data voltages and black gradation voltages alternately supplied to the data lines.

Referring to FIG. 7, the first gate start pulse GSP1 is generated after a period of less than about 1/4 frame period (1V / 4) than the first pulse P1_black and the first pulse P1_black (P1_data).

The pulse width of the 1-1 pulse (P1_black) is approximately one horizontal period, and the pulse width of the 1-2 pulse (P1_data) is also approximately one horizontal period. The first gate drive IC 831 sequentially shifts the first pulse P1_black according to the gate shift clock GSC to sequentially generate gate pulses as shown in FIG. 8D, and then supplies the gate pulses to the first block BL1 . During the fourth sub frame period SF4, the first block BL1 is scanned by the first gate drive IC 831, which starts to operate in response to the first pulse P1_black, .

The first gate drive IC 831 sequentially shifts the 1-2 pulse (P1_data) according to the gate shift clock GSC to sequentially generate gate pulses as shown in FIG. 8A, and then, in the first block BL1 Supply. During the first sub frame period SF1, the first block BL1 starts scanning in response to the first gate drive IC 831 starting to operate in response to the 1-2 pulse (P1_data) .

The second gate start pulse GSP2 is generated by applying the second-first pulse P2_black and the second-second pulse P2_black generated after a period shorter than the first-fourth pulse period (1V / 4) (P2_data).

The second-1 pulse P2_black has a pulse width of approximately one horizontal period, and one portion overlaps with the first pulse 1-2 (P1_data) and is generated later than the 1-2 pulse (P1_data). The pulse width of the second -2 pulse (P2_data) is approximately one horizontal period. The second gate drive IC 832 sequentially shifts the second-1 pulse P2_black in accordance with the gate shift clock GSC to sequentially generate gate pulses as shown in FIG. 8A, and then supplies the gate pulses to the second block BL2 . During the first sub frame period SF1, the second block BL2 is scanned by the second gate drive IC 832, which starts to operate in response to the second-1 pulse P2_black, .

The second gate drive IC 832 sequentially shifts the second -2 pulses P2_data according to the gate shift clock GSC to sequentially generate gate pulses as shown in FIG. 8B, Supply. During the second sub frame period SF2, the second block BL2 starts to scan by the second gate drive IC 832, which starts to operate in response to the second-second pulse P2_data, .

The third gate-start pulse GSP3 is generated by applying the third-1 pulse P3_black and the third-second pulse P3_black generated after a period shorter than the 1/4 frame period (1V / 4) And a pulse P3_data.

The 3-1 pulse (P3_black) has a pulse width of approximately one horizontal period, and one part overlaps with the 2-2 pulse (P2_data) to occur later than the 2-2 pulse (P2_data). The pulse width of the third-second pulse (P3_data) is approximately one horizontal period. The third gate drive IC 833 successively shifts the third-1 pulse P3_black according to the gate shift clock GSC to sequentially generate gate pulses as shown in FIG. 8B and then supply the gate pulses to the third block BL3 . During the second sub frame period SF2, the third block BL3 is scanned by the third gate drive IC 833, which starts to operate in response to the third-first pulse P3_black, .

The third gate drive IC 833 sequentially shifts the third-second pulse P3_data in accordance with the gate shift clock GSC to sequentially generate gate pulses as shown in FIG. 8C, and then, in the third block BL3 Supply. During the third sub frame period SF3, the third block BL3 starts to scan by the third gate drive IC 833, which starts to operate in response to the third-second pulse P3_data, .

The fourth gate start pulse GSP4 is generated by applying the fourth-1 pulse P4_black and the fourth-second pulse P4_black generated after a period shorter than the 1/4 frame period (1V / 4) (P4_data).

The 4-1 pulse (P4_black) has a pulse width of approximately one horizontal period, and a part overlaps with the 3-2 pulse (P3_data) and is generated later than the 3-2 pulse (P3_data). The pulse width of the fourth-second pulse (P4_data) is approximately one horizontal period. The fourth gate drive IC 834 sequentially shifts the 4-1 pulse P4_black according to the gate shift clock GSC to sequentially generate gate pulses as shown in FIG. 8C and then supply the gate pulses to the fourth block BL4 . During the third sub frame period SF3, the fourth block BL4 is scanned by the fourth gate drive IC 834, which starts to operate in response to the 4-1 pulse P4_black, .

The fourth gate drive IC 834 successively shifts the 4-2 pulses P4_data according to the gate shift clock GSC to sequentially generate gate pulses as shown in FIG. 8D, and then, in the fourth block BL4 Supply. During the fourth sub frame period SF4, the fourth block BL4 starts scanning in response to the fourth gate drive IC 834 starting to operate in response to the 4-2 pulse (P4_data) .

9 shows data write, data holding, and black insertion operations for each block when the liquid crystal display according to the embodiment of the present invention drives the impulse. FIGS. 10A to 10D show gate timing control signals and display states of a screen applied to gate drive ICs of respective blocks according to a sub-frame in FIG.

Referring to FIG. 9, the liquid crystal display according to the embodiment of the present invention divides the display screen of the liquid crystal display panel 80 into a plurality of blocks and performs data write- > data maintenance- > Blocks are controlled independently. In addition, the liquid crystal display according to the embodiment of the present invention drives one frame period by time division into as many subframes as the number of blocks, controls one block in each of the subframes SF1 to SF4 as a data write block , The other two blocks are controlled by the data holding block, and the other block is controlled by the black insertion block.

The gate drive circuit 83 is composed of four gate drive ICs 831 to 834 and the liquid crystal display panel 80 is divided into four blocks BL1 to BL4 ), And the one frame period is time-divisionally driven into four subframes, the operation of each of the blocks BL1 to BL4 and the corresponding data / gate drive ICs will be described as follows.

During the first sub frame period SF1, a first gate start pulse GSP1 and a gate shift clock GSC generated in the first 1-2 pulse (P1_data) are applied to the first gate drive IC 831 . Therefore, the first gate drive IC 831 has a pulse width of approximately one horizontal period in response to the first gate start pulse GSP1 and the gate shift clock GSC generated by the 1-2 pulse P1_data And sequentially supplies gate pulses to the gate lines of the first block BL1. While the first block BL1 is being scanned, the source drive IC alternately outputs the black gradation voltage and the analog video data voltage in response to the BDI source output enable signal SOEb as shown in FIG. 8A. At this time, the gate pulses sequentially supplied to the gate lines of the first block BL1 are synchronized with the analog video data voltages output from the source drive ICs. Therefore, during the first sub-frame period SF1, the analog video data voltage is sequentially charged (that is, written into) the first block BL1 by one line at a time.

During the first sub frame period SF1, a second gate start pulse GSP2 and a gate shift clock GSC generated in the second-1 pulse P2_black are applied to the second gate drive IC 832, . Therefore, the second gate drive IC 832 has a pulse width of approximately one horizontal period in response to the second gate start pulse GSP2 and the gate shift clock GSC generated by the second-1 pulse P2_black And sequentially supplies gate pulses to the gate lines of the second block BL2. While the second block BL2 is being scanned, the source drive IC alternately outputs the black gradation voltage and the analog video data voltage in response to the source output enable signal SOEb as shown in FIG. 8A. At this time, the gate pulses sequentially supplied to the gate lines of the second block BL2 are synchronized with the black gradation voltage outputted from the source drive ICs. Therefore, during the first sub frame period SF1, the black gradation voltage is sequentially charged in the second block BL2 one line at a time.

During the first sub frame period SF1, the gate start pulse is not applied to the third and fourth gate drive ICs 833 and 834 as shown in FIG. 10A. Accordingly, during the first sub frame period SF1, the liquid crystal cells of the third and fourth blocks BL3 and BL4 maintain the analog data voltage charged in the previous frame period.

During the second sub frame period SF2, the gate start pulse is not applied to the first gate drive IC 831 as shown in FIG. 10B. Therefore, the liquid crystal cells of the first block BL1 hold the analog data voltage charged in the first sub frame period SF1 during the second sub frame period SF2.

During the second sub frame period SF2, the second gate drive IC 832 is supplied with the second gate start pulse GSP2 and the gate shift clock GSC generated by the second -2 pulse (P2_data) . Accordingly, the second gate drive IC 832 generates the second gate drive pulse GSP2 having the pulse width of approximately one horizontal period in response to the second gate start pulse GSP2 and the gate shift clock GSC generated by the second-second pulse P2_data And sequentially supplies gate pulses to the gate lines of the second block BL2. While the second block BL2 is being scanned, the source driver IC alternately outputs the black gradation voltage and the analog video data voltage in response to the BDI source output enable signal SOEb as shown in FIG. 8B. At this time, the gate pulses sequentially supplied to the gate lines of the second block BL2 are synchronized with the analog video data voltages output from the source drive ICs. Therefore, during the second sub-frame period SF2, the analog video data voltage is sequentially charged into the second block BL2 one line at a time.

During the second sub frame period SF2, a third gate start pulse GSP3 and a gate shift clock GSC generated in the third-1 pulse P3_black are applied to the third gate drive IC 833, . Therefore, the third gate drive IC 833 generates a third gate drive pulse GSP3 having a pulse width of approximately one horizontal period in response to the third gate start pulse GSP3 and the gate shift clock GSC generated in the third-1 pulse P3_black And sequentially supplies the gate pulse to the gate lines of the third block BL3. While the third block BL3 is being scanned, the source drive IC alternately outputs the black gradation voltage and the analog video data voltage in response to the BDI source output enable signal SOEb as shown in FIG. 8B. At this time, the gate pulses sequentially supplied to the gate lines of the third block BL3 are synchronized with the black gradation voltages outputted from the source drive ICs. Therefore, during the second sub frame period SF2, the black gradation voltage is sequentially charged in the third block BL3 one line at a time.

During the second sub frame period SF2, the gate start pulse is not applied to the fourth gate drive IC 834 as shown in FIG. 10B. Therefore, during the second sub-frame period SF2, the liquid crystal cells of the fourth block BL4 maintain the analog data voltage charged in the previous frame period.

During the third sub frame period SF3, the gate start pulse is not applied to the first gate drive IC 831 as shown in FIG. 10C. Therefore, the liquid crystal cells of the first block BL1 hold the analog data voltage charged in the first sub frame period SF1 during the third sub frame period SF3.

During the third sub frame period SF3, the gate start pulse is not applied to the second gate drive IC 832 as shown in FIG. 10C. Therefore, the liquid crystal cells of the second block BL2 hold the analog data voltage charged in the second sub frame period SF2 during the third sub frame period SF3.

During the third sub frame period SF3, the third gate drive IC 833 receives the third gate start pulse GSP3 and the gate shift clock GSC generated by the third-second pulse P3_data as shown in FIG. 10C . Accordingly, the third gate drive IC 833 generates a third gate drive pulse GSP3 having a pulse width of approximately one horizontal period in response to the third gate start pulse GSP3 generated by the third-second pulse P3_data and the gate shift clock GSC And sequentially supplies the gate pulse to the gate lines of the third block BL3. While the third block BL3 is being scanned, the source drive IC alternately outputs the black gradation voltage and the analog video data voltage in response to the BDI source output enable signal SOEb as shown in Fig. 8C. At this time, the gate pulses sequentially supplied to the gate lines of the third block BL3 are synchronized with the analog video data voltages output from the source drive ICs. Therefore, during the third sub frame period SF3, the analog video data voltage is sequentially charged in the third block BL3 one line at a time.

During the third sub frame period SF3, the fourth gate drive IC 834 receives the fourth gate start pulse GSP4 and the gate shift clock GSC generated by the 4-1 pulse P4_black as shown in FIG. 10C . Accordingly, the fourth gate drive IC 834 has a pulse width of approximately one horizontal period in response to the fourth gate start pulse GSP4 and the gate shift clock GSC generated by the 4-1 pulse P4_black And sequentially supplies the gate pulse to the gate lines of the fourth block BL4. While the fourth block BL4 is being scanned, the source drive IC alternately outputs the black gradation voltage and the analog video data voltage in response to the BDI source output enable signal SOEb as shown in Fig. 8C. At this time, the gate pulses sequentially supplied to the gate lines of the fourth block BL4 are synchronized with the black gradation voltages outputted from the source drive ICs. Therefore, during the third sub frame period SF3, the black gradation voltage is sequentially charged in the fourth block BL4 one line at a time.

During the fourth sub frame period SF4, the first gate drive IC 831 receives the first gate start pulse GSP1 and the gate shift clock GSC generated by the first pulse P1_black as shown in FIG. . Therefore, the first gate drive IC 831 generates a pulse width corresponding to approximately one horizontal period in response to the first gate start pulse GSP1 and the gate shift clock GSC generated by the first pulse P1_black Sequentially supplies gate pulses to the gate lines of the first block BL1. While the first block BL1 is being scanned, the source drive IC alternately outputs the black gradation voltage and the analog video data voltage in response to the BDI source output enable signal SOEb as shown in Fig. 8D. At this time, the gate pulses sequentially supplied to the gate lines of the first block BL1 are synchronized with the black gradation voltages outputted from the source drive ICs. Therefore, during the fourth sub frame period SF4, the black gradation voltage is sequentially charged in the first block BL1 one line at a time.

During the fourth sub frame period SF4, the gate start pulse is not applied to the second gate drive IC 832 as shown in Fig. 10D. Therefore, during the fourth sub frame period SF4, the liquid crystal cells of the second block BL2 hold the analog data voltage charged in the second sub frame period SF2.

During the fourth sub frame period SF4, the gate start pulse is not applied to the third gate drive IC 833 as shown in FIG. 10D. Therefore, during the fourth sub frame period SF4, the liquid crystal cells of the third block BL3 hold the analog data voltage charged in the third sub frame period SF2.

During the fourth sub frame period SF4, the fourth gate drive IC 833 receives the fourth gate start pulse GSP4 and the gate shift clock GSC generated by the fourth-second pulse P4_data as shown in Fig. . Therefore, the fourth gate drive IC 833 outputs a pulse having a pulse width of approximately one horizontal period in response to the fourth gate start pulse GSP4 and the gate shift clock GSC generated by the 4-2 pulse (P4_data) And sequentially supplies the gate pulse to the gate lines of the fourth block BL4. While the fourth block BL4 is being scanned, the source drive IC alternately outputs the black gradation voltage and the analog video data voltage in response to the BDI source output enable signal SOEb as shown in Fig. 8D. At this time, the gate pulses sequentially supplied to the gate lines of the fourth block BL4 are synchronized with the analog video data voltages output from the source drive ICs. Therefore, during the fourth sub frame period SF4, the analog video data voltage is sequentially charged in the fourth block BL4 one line at a time.

As described above, the liquid crystal display device and the driving method thereof according to the present invention independently supply gate start pulses to a plurality of gate drive ICs corresponding to each of a plurality of blocks of a liquid crystal display panel that is divided and driven, Impulse driving can be enabled by performing data write, data holding, and black insertion independently for each block based on the pulse.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. For example, in the embodiment of the present invention, a liquid crystal display device driven by an impulse through four blocks, four gate drive ICs, four gate start pulses, and four subframes has been described as an example, but the technical idea of the present invention is limited thereto But it may be applied to a liquid crystal display device which is impulse driven through k blocks (k is a natural number of 2 or more) blocks, k gate drive ICs, k gate start pulses, and k subframes. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a characteristic diagram showing a light emission characteristic of a cathode ray tube. FIG.

2 is a characteristic diagram showing the luminescence characteristics of a liquid crystal display device.

3 is a view showing a perception image of a cathode ray tube felt by a spectator.

4 is a view showing a perception image of a liquid crystal display device felt by a spectator.

5 is a block diagram showing a liquid crystal display device according to an embodiment of the present invention.

6 is a detailed view of the gate drive circuit of FIG. 5;

FIG. 7 is a waveform diagram showing first to fourth gate start pulses shown in FIG. 5; FIG.

8A to 8D show the gate timing control signals applied to the gate drive ICs for each block and the gate pulses generated from the gate drive ICs according to the subframe in FIG. 7, A timing control signal and an analog data voltage alternately supplied to a data line and a black gradation voltage.

9 is a view showing data write, data holding, and black insertion operations for each block when the liquid crystal display device according to the embodiment of the present invention drives an impulse.

FIGS. 10A to 10D are diagrams showing gate timing control signals and display states of a screen applied to gate drive ICs of respective blocks according to a sub-frame in FIG. 9;

Description of the Related Art

80: liquid crystal display panel 81: timing controller

82: Data driving circuit 83: Gate driving circuit

84: Data line 85: Gate line

831,832,833,834: Gate drive IC

Claims (16)

A liquid crystal display panel in which a plurality of data lines and a plurality of gate lines are crossed and driven by k (k is a natural number of 2 or more) blocks; A gate driving circuit having k gate drive ICs formed on the liquid crystal display panel and supplying gate pulses to the gate lines of the k blocks independently; A data driving circuit for supplying an analog data voltage and a black gradation voltage to the data lines; And And a timing controller for generating a data timing control signal for controlling the operation timing of the data driving circuit and generating a gate timing control signal for controlling the operation timing of the gate drive ICs driven independently of each other Wherein the liquid crystal display device is a liquid crystal display device. The method according to claim 1, And k is 4. 3. The method of claim 2, The gate timing control signal includes: A first gate start pulse for indicating a start line from which a scan is started so that a first gate pulse is generated from a first one of the gate drive ICs; A second gate start pulse indicating a start line from which a scan is started so that a first gate pulse is generated from the second gate drive IC; A third gate start pulse indicating a start line from which a scan is started so that a first gate pulse is generated from the third gate drive IC; A fourth gate start pulse indicating a start line from which a scan is started so that a first gate pulse is generated from the fourth gate drive IC; And And a gate shift clock signal for shifting the gate start pulses. The method of claim 3, The first gate start pulse includes a 1-1 pulse P1_black and a 1-2 pulse P1_data generated after a period shorter than a 1/4 frame period (1V / 4) ); The second gate start pulse includes a second-first pulse P2_black and a second-second pulse P2_data generated after a period shorter than a 1/4 frame period (1V / 4) ); The third gate-start pulse includes a third-1 pulse (P3_black) and a third-second pulse (P3_data) generated after a period shorter than the 1/4 frame period (1V / 4) ); The fourth gate start pulse includes a 4-1 pulse P4_black and a 4-2 pulse P4_data generated after a period shorter than a 1/4 frame period (1V / 4) from the 4-1 pulse P4_black And a liquid crystal layer formed on the liquid crystal layer. 5. The method of claim 4, The pulse width of the 1-1 pulse (P1_black) and the pulse width of the 1-2 pulse (P1_data) are one horizontal period; The second-1 pulse P2_black and the second-second pulse P2_data are one horizontal period, and the second-1 pulse P2_black is the first 1-2 pulse P1_data, And the second pulse P1_data is overlapped and is generated later than the first 1-2 pulse P1_data; The pulse width of the third-first pulse P3_black and the pulse width of the third-second pulse P3_data are one horizontal period, the third-first pulse P3_black is the second-second pulse P2_data, Is overlapped and is generated later than the second -2 pulse (P2_data); The pulse width of the 4-1 pulse (P4_black) and the pulse width of the 2-2 pulse (P2_data) are one horizontal period, and the 4-1 pulse (P4_black) (P3_data) are overlapped with each other and are generated later than the third-second pulse (P3_data). 6. The method of claim 5, The first gate drive IC sequentially shifts the 1-1 pulse (P1_black) according to the gate shift clock signal to generate 1-1 gate pulses and sequentially supply the 1-1 gate pulses to the gate lines of the first block, Sequentially generates a 1-2 gate pulse by sequentially shifting the 1-2 pulse (P1_data) according to the gate shift clock signal, and sequentially supplies the 1-2 gate pulse to the gate lines of the first block; The second gate drive IC sequentially shifts the second-1 pulse (P2_black) according to the gate shift clock signal to sequentially generate 2-1 gate pulses to the gate lines of the second block, Sequentially generating 2-2 gate pulses by sequentially shifting the 2-2 pulses (P2_data) according to the gate shift clock signal, and sequentially supplying the 2-2 gate pulses to the gate lines of the second block; The third gate drive IC sequentially shifts the 3-1 pulse (P3_black) according to the gate shift clock signal to generate 3-1 gate pulses and sequentially supplies the 3-1 gate pulses to the gate lines of the third block, Sequentially generating a 3-2 gate pulse by sequentially shifting the 3-2 pulse (P3_data) according to the gate shift clock signal, and sequentially supplying the 3-2 gate pulse to the gate lines of the third block; The fourth gate drive IC sequentially shifts the 4-1 pulse (P4_black) according to the gate shift clock signal to generate 4-1 gate pulses and sequentially supplies the gate pulses to the gate lines of the fourth block, And sequentially generating a 4-2 gate pulse by sequentially shifting the 4-2 pulse (P4_data) according to the gate shift clock signal, and sequentially supplying the generated 4-2 pulse to the gate lines of the fourth block. The method according to claim 6, The 1-2 gate pulse is synchronized with the analog data voltage supplied from the data driving circuit and the 2-1 gate pulse is supplied to the black gradation voltage supplied from the data driving circuit during the first sub frame period of one frame period Synchronized; The 2-2 gate pulse is synchronized with the analog data voltage supplied from the data driving circuit during the second sub frame period following the first sub frame period and the 3-1 gate pulse is synchronized with the analog data voltage supplied from the data driving circuit Synchronized with the black gradation voltage; The 3-2 gate pulse is synchronized with the analog data voltage supplied from the data driving circuit during the third sub frame period subsequent to the second sub frame period, and the 4-1 gate pulse is synchronized with the analog data voltage supplied from the data driving circuit Synchronized with the black gradation voltage; The 4-2 gate pulse is synchronized with the analog data voltage supplied from the data driving circuit during the fourth sub frame period subsequent to the third sub frame period, and the 1-1 gate pulse is synchronized with the analog data voltage supplied from the data driving circuit And is synchronized with the black gradation voltage. 8. The method of claim 7, During the first sub frame period, no gate start pulse is applied to the third gate drive IC and the fourth gate drive IC; During the second sub frame period, no gate start pulse is applied to the first gate drive IC and the fourth gate drive IC; During the third sub frame period, no gate start pulse is applied to the first gate drive IC and the second gate drive IC; And no gate start pulse is applied to the second gate drive IC and the third gate drive IC during the fourth sub frame period. A liquid crystal display panel in which a plurality of data lines and a plurality of gate lines cross each other and are divided and driven into k blocks (k is a natural number of 2 or more) blocks, a plurality of data lines formed on the liquid crystal display panel, A driving method of a liquid crystal display device having a gate driving circuit having k gate drive ICs supplying pulses independently and a data driving circuit supplying analog data voltages and black gradation voltages to the data lines, Generating a data timing control signal for controlling an operation timing of the data driving circuit; And And generating gate timing control signals for controlling the operation timings of the gate drive ICs driven independently of each other. 10. The method of claim 9, And k is 4. The method of claim 1, 11. The method of claim 10, The gate timing control signal includes: A first gate start pulse indicating a start line at which a scan is started so that a first gate pulse is generated from a first one of the gate drive ICs; A second gate start pulse indicating a start line from which a scan is started so that a first gate pulse is generated from the second gate drive IC; A third gate start pulse indicating a start line from which a scan is started so that a first gate pulse is generated from the third gate drive IC; A fourth gate start pulse indicating a start line from which a scan is started so that a first gate pulse is generated from the fourth gate drive IC; And And a gate shift clock signal for shifting the gate start pulses. 12. The method of claim 11, The first gate start pulse includes a 1-1 pulse P1_black and a 1-2 pulse P1_data generated after a period shorter than a 1/4 frame period (1V / 4) ); The second gate start pulse includes a second-first pulse P2_black and a second-second pulse P2_data generated after a period shorter than a 1/4 frame period (1V / 4) ); The third gate-start pulse includes a third-1 pulse (P3_black) and a third-second pulse (P3_data) generated after a period shorter than the 1/4 frame period (1V / 4) ); The fourth gate start pulse includes a 4-1 pulse (P4_black) and a 4-2 pulse (P4_data) generated after a period shorter than the 1/4 frame period (1V / 4) And a driving method of the liquid crystal display device. 13. The method of claim 12, The pulse width of the 1-1 pulse (P1_black) and the pulse width of the 1-2 pulse (P1_data) are one horizontal period; The second-1 pulse P2_black and the second-second pulse P2_data are one horizontal period, and the second-1 pulse P2_black is the first 1-2 pulse P1_data, And the second pulse P1_data is overlapped and is generated later than the first 1-2 pulse P1_data; The pulse width of the third-first pulse P3_black and the pulse width of the third-second pulse P3_data are one horizontal period, the third-first pulse P3_black is the second-second pulse P2_data, Is overlapped and is generated later than the second -2 pulse (P2_data); The pulse width of the 4-1 pulse (P4_black) and the pulse width of the 2-2 pulse (P2_data) are one horizontal period, and the 4-1 pulse (P4_black) (P3_data) is overlapped with the third pulse (P3_data). 14. The method of claim 13, The first gate drive IC sequentially shifts the 1-1 pulse (P1_black) according to the gate shift clock signal to generate 1-1 gate pulses and sequentially supply the 1-1 gate pulses to the gate lines of the first block, Sequentially generates a 1-2 gate pulse by sequentially shifting the 1-2 pulse (P1_data) according to the gate shift clock signal, and sequentially supplies the 1-2 gate pulse to the gate lines of the first block; The second gate drive IC sequentially shifts the second-1 pulse (P2_black) according to the gate shift clock signal to sequentially generate 2-1 gate pulses to the gate lines of the second block, Sequentially generating 2-2 gate pulses by sequentially shifting the 2-2 pulses (P2_data) according to the gate shift clock signal, and sequentially supplying the 2-2 gate pulses to the gate lines of the second block; The third gate drive IC sequentially shifts the 3-1 pulse (P3_black) according to the gate shift clock signal to generate 3-1 gate pulses and sequentially supplies the 3-1 gate pulses to the gate lines of the third block, Sequentially generating a 3-2 gate pulse by sequentially shifting the 3-2 pulse (P3_data) according to the gate shift clock signal, and sequentially supplying the 3-2 gate pulse to the gate lines of the third block; The fourth gate drive IC sequentially shifts the 4-1 pulse (P4_black) according to the gate shift clock signal to generate 4-1 gate pulses and sequentially supplies the gate pulses to the gate lines of the fourth block, And sequentially generates a 4-2 gate pulse by sequentially shifting the 4-2 pulses (P4_data) according to the gate shift clock signal to sequentially supply the 4-2 pulses to the gate lines of the fourth block. Way. 15. The method of claim 14, The 1-2 gate pulse is synchronized with the analog data voltage supplied from the data driving circuit and the 2-1 gate pulse is supplied to the black gradation voltage supplied from the data driving circuit during the first sub frame period of one frame period Synchronized; The 2-2 gate pulse is synchronized with the analog data voltage supplied from the data driving circuit during the second sub frame period following the first sub frame period and the 3-1 gate pulse is synchronized with the analog data voltage supplied from the data driving circuit Synchronized with the black gradation voltage; The 3-2 gate pulse is synchronized with the analog data voltage supplied from the data driving circuit during the third sub frame period subsequent to the second sub frame period, and the 4-1 gate pulse is synchronized with the analog data voltage supplied from the data driving circuit Synchronized with the black gradation voltage; The 4-2 gate pulse is synchronized with the analog data voltage supplied from the data driving circuit during the fourth sub frame period subsequent to the third sub frame period, and the 1-1 gate pulse is synchronized with the analog data voltage supplied from the data driving circuit And the second voltage is synchronized with the black gradation voltage. 16. The method of claim 15, During the first sub frame period, no gate start pulse is applied to the third gate drive IC and the fourth gate drive IC; During the second sub frame period, no gate start pulse is applied to the first gate drive IC and the fourth gate drive IC; During the third sub frame period, no gate start pulse is applied to the first gate drive IC and the second gate drive IC; And a gate start pulse is not applied to the second gate drive IC and the third gate drive IC during the fourth sub frame period.

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