KR20080051357A - Liquid crystal display and driving method thereof - Google Patents

Abstract

An LCD(Liquid Crystal Display) device and a driving method thereof are provided to ensure sufficiently charge time by charging image data voltages in pixels during a two thirds frame. An LCD(Liquid Crystal Display) device includes a signal controller(600), data and gate drivers(500,400), and an LCD panel(300). The signal controller receives original image signals and provides first, second, and third image signals corresponding to the original image during first, second, and third intervals, respectively. The data driver provides image data voltages corresponding to the first to third image signals. The gate driver sequentially provides gate signals during the first to third intervals. The LCD panel includes plural pixels for displaying images corresponding to the image data voltages by turning on and off according to the gate signals.

Description

Liquid crystal display and driving method thereof

1 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of one pixel of FIG. 1.

3 is a block diagram illustrating the signal controller of FIG. 1.

FIG. 4 is a graph for explaining the signal controller of FIG. 3.

5 is a signal diagram illustrating a gate signal provided by the gate driver of FIG. 1.

FIG. 6 is a signal diagram for describing inversion driving of the liquid crystal display of FIG. 1.

(Explanation of symbols for the main parts of the drawing)

10: liquid crystal display device 100: first display panel

150: liquid crystal 200: second display panel

300: liquid crystal panel 400: gate driver

500: data driver 600: signal controller

610: lookup table 620: multiplexer

630: selection signal generator 700: frame memory

800: gray voltage generator

The present invention relates to a liquid crystal display device and a driving method thereof.

The liquid crystal display includes two display panels including a pixel electrode and a common electrode, and a liquid crystal layer having dielectric anisotropy interposed therebetween. The pixel electrodes are arranged in a matrix and connected to switching elements such as thin film transistors (TFTs) to receive data voltages one by one in sequence. The common electrode is formed over the entire surface of the display panel and receives a common voltage. The pixel electrode, the common electrode, and the liquid crystal layer therebetween form a liquid crystal capacitor, and the liquid crystal capacitor becomes a basic unit that forms a pixel together with a switching element connected thereto.

In such a liquid crystal display, an image is generated by applying an image data voltage and a common voltage to the pixel electrode and the common electrode, respectively, and an electric field is generated in the liquid crystal layer. Get In this case, in order to prevent deterioration caused by an electric field applied to the liquid crystal layer for a long time, the polarity of the image data voltage with respect to the common voltage is inverted frame by frame, row by pixel, or pixel by pixel. However, when the polarity of the data voltage is inverted as described above, the response speed of the liquid crystal molecules is slow, so that it takes a long time for the liquid crystal capacitor to charge to the target voltage, so that the screen is not clear and blurring occurs.

In order to solve this problem, a black insertion driving method (or an impulsive driving method) for inserting a black screen for a short time has been developed. According to this method, however, the charging time of the image data voltage is reduced, the luminance is reduced, and the display quality is degraded. In addition, in order to overcome the shortcoming of the charging time, the same method as the black insertion driving method is used below a certain gray level, and a driving method that separates / provides a video signal having a high gray level and a low gray level for a video signal above a certain gray level is developed. It became. However, since this method is not a black insertion driving above a certain gray level, the screen is still not clear and blurring occurs.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a liquid crystal display device capable of improving display quality.

Another object of the present invention is to provide a method of driving a liquid crystal display device capable of improving display quality.

The technical problems of the present invention are not limited to the above-mentioned technical problems, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, a liquid crystal display device receives a plurality of raw image signals of an nth frame, and provides first image signals corresponding to each of the raw image signals during a first period. A signal controller configured to provide second image signals corresponding to each of the original image signals during a second period, and to provide third image signals corresponding to each of the original image signals during a third period; A data driver providing an image data voltage corresponding to the image signals, a gate driver sequentially providing a gate signal during each of the first to third periods, and an ON / OFF state of the gate signal to correspond to the image data voltage It includes a liquid crystal panel having a plurality of pixels for displaying an image.

According to another aspect of the present invention, there is provided a method of driving a liquid crystal display device, wherein a plurality of raw image signals of an nth frame are input, and a first image corresponding to each of the raw image signals during a first period. Providing signals, providing second image signals corresponding to each of the original image signals during a second period, and providing third image signals corresponding to each of the original image signals during a third period; Providing image data voltages corresponding to the third to third image signals; sequentially providing gate signals during the first to third periods; and turning on / off the gate signals to correspond to the image data voltages. And displaying an image.

Other specific details of the present invention are included in the detailed description and drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms, and only the embodiments make the disclosure of the present invention complete, and the general knowledge in the art to which the present invention belongs. It is provided to fully inform the person having the scope of the invention, which is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

1 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of one pixel of FIG. 1, and FIG. 3 is a block diagram illustrating the signal controller of FIG. 1. 4 is a graph illustrating the signal controller of FIG. 3, FIG. 5 is a signal diagram illustrating the gate driver of FIG. 1, and FIG. 6 is a signal illustrating the inversion driving of the liquid crystal display of FIG. 1. It is also.

Referring to FIG. 1, the liquid crystal display 10 may include a liquid crystal panel 300, a gate driver 400, a data driver 500, a signal controller 600, a frame memory 700, and a gray voltage generator 800. It includes.

The liquid crystal panel 300 includes a plurality of display signal lines G1 -Gn and D1 to Dm and a plurality of pixels PX connected to the display signal lines G1-Gn and D1 to Dm in an equivalent circuit. Here, referring to FIG. 2, the liquid crystal panel 300 includes a first display panel 100, a second display panel 200, and a liquid crystal 150 interposed therebetween.

The display signal lines G1 to Gn and D1 to Dm include a plurality of gate lines G1 to Gn transferring gate signals and a plurality of data lines D1 to Dm transferring data signals. The gate lines G1 to Gn extend substantially in the row direction and are substantially parallel to each other, and the data lines D1 to Dm extend substantially in the column direction and are substantially parallel to each other.

2 shows an equivalent circuit for one pixel PX of FIG. 1. The color filter CF may be formed in a portion of the common electrode CE of the second display panel 200 to face the pixel electrode PE of the first display panel 100. Each pixel, for example, a pixel connected to an i-th (i = 1 to n) gate line Gi and a j-th (j = 1 to m) data line Dj may include a switching element connected to the signal lines Gi and Dj. Q) and a liquid crystal capacitor Clc and a storage capacitor Cst connected thereto.

Meanwhile, the frame memory 700 receives and stores the raw video signal DATn + 1 of the n + 1th frame from an external graphic controller (not shown), and stores the raw video signal DATn of the nth frame. Provided at 600.

The signal controller 600 receives an input control signal for controlling the raw image signal DATn of the nth frame and a display thereof from the frame memory 700. Examples of the input control signal include a vertical sync signal Vsync, a vertical sync signal Hsync, a main clock MCLK, and a data enable signal DE.

The signal controller 600 generates a gate control signal CONT1 and a data control signal CONT2 based on the input control signal, and provides them to the gate driver 400 and the data driver 500, respectively.

In addition, the signal controller 600 receives a plurality of raw image signals DATn of an nth frame, and provides first image signals DATn_1 corresponding to each of the original image signals DATn during a first period. The second image signals DATn_2 corresponding to the respective raw image signals DATn are provided for two sections, and the third image signals B corresponding to the respective original image signals DATn are provided for a third section. . The signal controller 600 will be described later with reference to FIG. 3.

The data driver 500 receives the first to third image signals DATn_1, DATn_2, and B from the signal controller 600, and outputs image data voltages corresponding to the gray level voltages provided from the gray voltage generator 800. Select and apply it to the data lines D1 to Dm.

Specifically, image data voltages corresponding to the first image signals DATn_1 are applied to the data lines D1 to Dm during the first period, and corresponding to the second image signals DATn_2 during the second period. Image data voltages are applied to the data lines D1 to Dm, and image data voltages corresponding to the third image signals B are applied to the data lines D1 to Dm during the third period. The gray of the first image signal DATn_1 may be the same as or greater than the gray of the original image signal DATn, and the gray of the second image signal DATn_2 may be the same as or smaller than the gray of the original image signal DATn. The gray of the third image signal B may be black gray. This will be described later with reference to FIG. 4.

The gate driver 400 receives the gate control signal CONT1 from the signal controller 600 and sequentially applies the gate signal to the gate lines G1 to Gn during the first to third periods. The gate signal is a combination of a gate on voltage Von and a gate off voltage Voff provided from a gate on / off voltage generator (not shown). The gate control signal CONT1 is a signal for controlling the operation of the gate driver 500. The gate control signal CONT1 is a vertical start signal for starting the operation of the gate driver 500 and a gate clock signal for determining the output timing of the gate-on voltage Von. And an output enable signal for determining a pulse width of the gate-on voltage Von.

The gate driver 400 or the data driver 500 may be mounted directly on the liquid crystal panel 300 in the form of a plurality of driving integrated circuit chips, or mounted on a flexible printed circuit film (not shown). The liquid crystal panel 300 may be attached to the liquid crystal panel 300 in the form of a carrier package. Alternatively, the gate driver 400 or the data driver 500 may be integrated in the liquid crystal panel 300 together with the display signal lines G1 to Gn and D1 to Dm and the switching element Q.

The signal controller 600 of FIG. 1 will be described in detail with reference to FIG. 3.

Referring to FIG. 3, the signal controller 600 includes a lookup table 610, a multiplexer 620, and a selection signal SEL generator 630.

The lookup table 610 stores the first image signal DATn_1, the second image signal DATn_2, and the third image signal B corresponding to each of the original image signals DATn of the nth frame. Therefore, when the raw image signal DATn of the nth frame is provided from the frame memory 700, the first to third image signals DATn_1, DATn_2, and B corresponding to the input original image signal DATn of the nth frame are provided. ) Is provided to the multiplexer 620.

The selection signal generator 630 is a block for generating the selection signal SEL which is a control signal of the multiplexer 620. The multiplexer 620 has one image among the first to third image signals DATn_1, DATn_2, and B. The selection signal SEL is provided to select the signal. That is, the selection signal SEL to select the first video signal DATn_1 in the first section, select the second video signal DATn_2 in the second section, and select the third video signal B in the third section. ).

The multiplexer 620 receives the selection signal SEL, outputs the first image signal DATn_1 in the first section, outputs the second image signal DATn_2 in the second section, and third in the third section. The video signal B is output.

The first to third image signals DATn_1, DATn_2, and B will be described in detail with reference to FIG. 4. The graph shown in FIG. 4 shows the grays of the first to third image signals provided to one pixel during one frame.

Referring to FIG. 4, the gray of the original image signal DATn of the nth frame input to the signal controller 600 of FIG. 3 and the first to third video signals DATn_1, DATn_2, and B output by the signal controller are illustrated. Gray is shown.

In one frame, the image data voltage corresponding to the gray of the first image signal DATn_1 is applied in one frame and the image data voltage corresponding to the gray of the second image signal DATn_2 in the second section. Is applied, and a video data voltage corresponding to the gray of the third video signal B is applied in the third section. Here, the gray of the first image signal DATn_1 is equal to or higher than the gray of the original image signal DATn, the gray of the second image signal DATn_2 is equal to or lower than the gray of the original image signal DATn, and the third The gray of the image signal B may be 0 as black gray.

When the image data voltages corresponding to the first to third image signals DATn_1, DATn_2, and B are applied to the pixel, the charging time may be sufficiently secured since the image data voltages are provided during the first and second sections. Since the black screen is inserted during the third section, it is possible to prevent the screen from being blurred and blurring.

A gate signal provided from the gate driver 400 will be described in detail with reference to FIG. 5.

Referring to FIG. 5, the gate control signal CONT1 provided from the signal controller 600 includes a vertical start signal STV, which is connected to each gate line G1 to Gn in synchronization with the vertical start signal STV. The device (see Q in FIG. 2) is sequentially turned on.

More specifically, the vertical start signal STV is repeated three times during one frame. That is, one period of the vertical start signal STV may be 1/3 frame.

Every 1/3 frame, since the switching elements (see Q in FIG. 2) connected to each gate line in synchronization with the rising edge of the vertical start signal STV are sequentially turned on, each gate line G1 to Gn The gate-on voltage is provided three times during one frame, and each pixel connected to each gate line (see PX in FIG. 1) is used for the first image signal DATn_1, the second image signal DATn_2, and the third image signal for one frame. The image data voltage corresponding to (B) may be charged.

An inversion driving of the liquid crystal display device 10 of the present invention will be described in detail with reference to FIG. 6. For convenience of description, the image data voltages of the first to third image signals applied to one pixel for three frames are illustrated.

Referring to FIG. 6, positive and negative image data voltages are sequentially applied to the first frame, the second frame, and the third frame based on the common voltage Vcom. That is, in the first frame and the third frame, the first image signal D ₁₁ and D ₃₁ and the second image signal D ₁₂ and D ₃₂ have a voltage level higher than the common voltage Vcom, and in the second frame. The first image signal D ₂₁ and the second image signal D ₂₂ have a voltage level lower than the common voltage Vcom. In each frame, since the third image signal B (D ₁₃ , D ₂₃ , D ₃₃ ) has a black gray level, the common voltage Vcom may have the same voltage level.

According to the liquid crystal display and the driving method thereof, since the image data voltage is charged in the pixel for 2/3 frames, the charging time can be sufficiently secured, and since the black screen is inserted during the third period, the screen becomes unclear and blurred. Blurring can be prevented. Therefore, the display quality is improved.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

According to the liquid crystal display device and the driving method thereof according to the present invention as described above, since the black insertion drive can be performed while sufficiently securing the charging time, the display quality is improved.

Claims (11)

Receiving a plurality of raw image signals of an n-th frame, providing first image signals corresponding to each of the original image signals during a first period, and second image signals corresponding to each of the original image signals during a second period; A signal controller configured to provide third image signals corresponding to each of the original image signals during a third period; A data driver configured to provide an image data voltage corresponding to the first to third image signals; A gate driver which sequentially provides a gate signal during each of the first to third periods; And And a liquid crystal panel having a plurality of pixels on / off of the gate signal to display an image corresponding to the image data voltage. The method of claim 1, The sum of the first to third sections is one frame. The method of claim 1, The gray of each first image signal is equal to or higher than the gray of each of the original image signals, and the gray of each of the second image signals is equal to or lower than the gray of each of the original image signals. The method of claim 3, wherein The gray of each third image signal is a black gray. The method of claim 1, wherein the signal control unit, A look-up table for providing the first video signal, the second video signal, and the third video signal corresponding to each of the original video signals; And a selector configured to provide the first image signal in the first section, to enhance the second image signal in the second section, and to provide the third image signal in the third section. The method of claim 5, The selection unit includes a multiplexer (MUX). The method of claim 1, And a frame memory configured to receive and store raw image signals of an n + 1th frame, and provide raw signal signals of the nth frame to the signal controller. Receiving a plurality of raw image signals of an n-th frame, providing first image signals corresponding to each of the original image signals during a first period, and second image signals corresponding to each of the original image signals during a second period; Providing third image signals corresponding to each of the original image signals during a third period; Providing an image data voltage corresponding to the first to third image signals; Providing a gate signal sequentially during each of the first to third periods; And And displaying an image corresponding to the image data voltage by being on / off of the gate signal. The method of claim 8, The sum of the first to third sections is one frame. The method of claim 8, The gray of each of the first image signals is equal to or higher than the gray of each of the original image signals, and the gray of each of the second image signals is equal to or less than the gray of each of the original image signals. The method of claim 10, And a gray of each of the third image signals is a black gray.

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