KR101359922B1 - Display device - Google Patents

Abstract

The present invention relates to a drive device for a liquid crystal display device. The driving device may include a signal processing unit for inputting an image signal in units of a first frame having a first frame frequency, a plurality of frame memories, a light source unit having a plurality of light sources for supplying light to the plurality of pixels, and an output image signal. And a data driver which selects a corresponding gray voltage and applies it to the pixel as a data voltage. The signal processor sequentially stores the image signals input in units of a first frame in the plurality of frame memories, and at least two frame memories different from each other in the plurality of frame memories in a second frame unit having a second frame frequency. The image signal is read from the image signal, and the image signal selected in one of two frames is transferred to the data driver as the output image signal. The image quality is improved by reducing color distortion and reducing flicker.

LCD, Time Division, Impulsive, Field Sequential Driving, Frame Frequency Change, FRC, Redundant Frame

Description

Display device {DISPLAY DEVICE}

1 is a block diagram of a liquid crystal display device according to an embodiment of the present invention.

2 is an equivalent circuit diagram of a pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a block diagram of a signal controller of a liquid crystal display according to an exemplary embodiment of the present invention.

4 is an operation timing diagram of a memory unit of the liquid crystal display according to the exemplary embodiment of the present invention.

5 is a flowchart illustrating an operation of a signal processor of a liquid crystal display according to an exemplary embodiment of the present invention.

6 (a) to 6 (d) are diagrams illustrating the degree of color distortion in accordance with the display form of an image according to time change.

* Description of the Drawing Symbols *

3: liquid crystal layer 100, 200: substrate

270: common electrode 300: liquid crystal panel assembly

400: gate driver 500: data driver

600: signal controller 610: signal processor

620: memory 621-624: frame memory

800: gray voltage generator PX: pixel

G ₁ -G _n : Gate line D ₁ -D _m : Data line

Clc: Liquid Crystal Capacitor Cst: Maintenance Capacitor

Q: switching device CONT1: gate control signal

ONT2: .Data control signal CONT3: Light source control signal

STV: Vertical Sync Start Signal Vcom: Common Voltage

Von: gate-on voltage Voff; Gate-off voltage

OE: Output enable signal LOAD: Load signal

HCLK: data clock signal RVS: inverted signal

DAT: video data RL, GL, BL: light source

The present invention relates to a display device.

2. Description of the Related Art A general liquid crystal display (LCD) includes two display panels having pixel electrodes and a common electrode, and a liquid crystal layer having a dielectric anisotropy therebetween. The pixel electrodes are arranged in a matrix and connected to switching elements such as thin film transistors (TFTs) to receive data voltages one by one in sequence. The common electrode is formed over the entire surface of the display panel and receives a common voltage. The pixel electrode, the common electrode, and the liquid crystal layer between the pixel electrode and the common electrode form a liquid crystal capacitor in a circuit view, and the liquid crystal capacitor together with the switching device connected thereto constitutes a pixel unit.

In such a liquid crystal display device, a voltage is applied to the two electrodes to generate an electric field in the liquid crystal layer, and the intensity of the electric field is adjusted to adjust the transmittance of light passing through the liquid crystal layer to obtain a desired image.

To implement color display in a liquid crystal display, each pixel may display one of the primary colors uniquely (space division) or each pixel may alternately display the primary colors over time (time division). Make sure the desired color is recognized by the spatial and temporal sum of. Examples of the primary colors may include three primary colors of red, green, and blue or one or more primary colors in addition to the three primary colors such as red, green, blue, and white.

 In the case of the spatial division method, a color filter of the primary color is mounted in an area corresponding to the pixel electrode to display colors. In this case, light from a white light source such as a light emitting diode (LED) or a cold cathode fluorescent lamp (CCFL) may be passed through a liquid crystal layer and a color filter to display a corresponding color.

In the case of the time division method, a color of a liquid crystal display is implemented by separately installing a light source (light emitting diode or a fluorescent lamp) having a primary color.

When the primary color is the three primary colors, the time division scheme applies a red data voltage to all the pixels in turn for one frame and then turns on the red light source, and then applies the green data voltage to all the pixels and turns on the green light source. After the blue data voltage is finally applied to all the pixels, the blue light source is turned on.

Therefore, in the time division scheme, one frame is divided into three sections (sub-frames) for lighting the red, green, and blue light sources, respectively, and after all data voltages are applied during each sub-frame, It is lit.

However, when displaying a desired image using these methods, a problem such as flicker occurs due to a luminance difference or a frequency of a signal between adjacent pixels, thereby deteriorating the image quality of the liquid crystal display. In particular, when the luminance difference between neighboring pixels is large, the degree of flicker is increased. When the image is displayed using four colors of red, green, blue, and white, the difference between the lowest and highest luminance that can be expressed is large. The flicker phenomenon is even worse.

In addition, color display is realized by combining pixels of the same frame with spatial and temporal combinations of primary colors such as red, green, and blue, but color display is performed by mixing colors displayed during different frames, causing unwanted color display. ) Phenomenon occurs.

Accordingly, an object of the present invention is to improve the image quality of a display device.

A driving device according to an embodiment of the present invention is a driving device of a display device having a plurality of pixels, the signal processing unit for inputting an image signal in units of a first frame having a first frame frequency, a plurality of frame memories, and the plurality of pixels. A light source unit having a plurality of light sources for supplying light to a pixel of the pixel; and a data driver for selecting a gray voltage corresponding to an output image signal and applying the data voltage to the pixel as a data voltage; The image signals inputted are sequentially stored in the plurality of frame memories, and the image signals are read from at least two different frame memories among the plurality of frame memories in a second frame unit having a second frame frequency. The image signal selected in one of the frames is used as the output image signal. And it transmits the group data driver.

The magnitude of the first frame frequency may be smaller than the magnitude of the second frame frequency.

An excess frame having one second frame frequency is generated for each predetermined number of first frames, and the signal processor may read the image signal from two frame memories during the redundant frame.

The first frame frequency may be about 60 Hz, and the second frame frequency may be about 90 Hz.

The signal processor compares two image signals read from the two frame memories with each other during the redundant frame, calculates a difference value, and outputs an image signal having a predetermined gray level when the calculated difference value is larger than a set value. It is preferable to set as a video signal.

Preferably, the predetermined gradation is black gradation.

The video signal includes a video signal corresponding to each of a plurality of primary colors, the signal processor divides the second frame into a plurality of subframes, and outputs an image signal corresponding to one of the primary colors during each subframe. It is preferable to transfer to the data driver.

The plurality of light sources may emit light of the plurality of primary colors, respectively.

The colors of light supplied during adjacent subframes are preferably different from each other.

The image signal may include an image signal corresponding to each of the first primary colors, and the first primary colors may be red, green, and blue.

The signal processor may convert the image signal corresponding to the first primary color into an image signal corresponding to the second primary color, and store the image signal in the frame memory. The second primary color may be red, green, blue, and It may be white.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which: FIG.

In the drawings, the thickness is enlarged to clearly represent the layers and regions. Like parts are designated with like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. Conversely, when a part is "directly over" another part, it means that there is no other part in the middle.

A liquid crystal display, which is an embodiment of the display device of the present invention, will be described in detail with reference to FIGS. 1 to 3.

1 is a block diagram of a liquid crystal display according to an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of one pixel of the liquid crystal display according to an embodiment of the present invention, and FIG. 3 is an embodiment of the present invention. It is a block diagram of the signal control part of the liquid crystal display which concerns on an example.

As shown in FIG. 1, the liquid crystal display according to the exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, and a gray voltage generator. 800, a backlight unit 900, a light source controller 910, and a signal controller 600 for controlling them.

1, the liquid crystal panel assembly 300 is connected to a plurality of signal lines G ₁ -G _n and D ₁ -D _m in terms of an equivalent circuit and is arranged in a matrix form And includes a plurality of pixels PX. 2, the liquid crystal display panel assembly 300 includes lower and upper display panels 100 and 200 facing each other and a liquid crystal layer 3 interposed therebetween.

The signal lines G ₁ -G _n and D ₁ -D _m are a plurality of gate lines G ₁ -G _n for transmitting a gate signal (also called a “scan signal”) and a plurality of data lines for transmitting a data signal ( D ₁ -D _m ). The gate lines G _{1 to} G _n extend in a substantially row direction and are substantially parallel to each other, and the data lines D _{1 to} D _m extend in a substantially column direction and are substantially parallel to each other.

Each pixel PX, for example, the i-th (i = 1, 2, ..., n) gate line G _i and the j-th (j = 1, 2, ..., m) data line D _The pixel PX connected to _j ) includes a switching element Q connected to the signal lines G _i and D _j , a liquid crystal capacitor Clc, and a storage capacitor Cst connected thereto. . The storage capacitor Cst can be omitted if necessary.

The switching element Q is a three terminal element such as a thin film transistor provided in the lower panel 100. The control terminal is connected to the gate line G _i and the input terminal is connected to the data line D _j And the output terminal is connected to the liquid crystal capacitor Clc and the storage capacitor Cst.

The liquid crystal capacitor Clc has the pixel electrode 191 of the lower panel 100 and the common electrode 270 of the upper panel 200 as two terminals and the liquid crystal layer 3 between the two electrodes 191 and 270, . The pixel electrode 191 is connected to the switching element Q and the common electrode 270 is formed on the entire surface of the upper panel 200 to receive the common voltage Vcom. 2, the common electrode 270 may be provided on the lower panel 100. At this time, at least one of the two electrodes 191 and 270 may be linear or bar-shaped.

The storage capacitor Cst serving as an auxiliary capacitor of the liquid crystal capacitor Clc is formed by superimposing a separate signal line (not shown) and a pixel electrode 191 provided on the lower panel 100 with an insulator interposed therebetween, A predetermined voltage such as the common voltage Vcom is applied to the separate signal lines. However, the storage capacitor Cst may be formed by overlapping the pixel electrode 191 with the previous gate line immediately above via an insulator.

The liquid crystal panel assembly 300 is provided with at least one polarizer (not shown).

Referring again to FIG. 1, the gradation voltage generator 800 generates the total gradation voltage related to the transmittance of the pixel PX or a limited number of gradation voltages (hereinafter referred to as "reference gradation voltage"). (Reference) gradation voltage may have a positive value and a negative value with respect to the common voltage Vcom.

The gate driver 400 is connected to the gate lines G ₁ -G _n of the liquid crystal panel assembly 300 and supplies a gate signal composed of a combination of the gate-on voltage Von and the gate-off voltage Voff to the gate line G ₁ -G _n .

The data driver 500 is connected to the data lines D ₁ -D _m of the liquid crystal panel assembly 300 and selects the gradation voltages from the gradation voltage generator 800 and supplies them as data voltages to the data lines D ₁ -D _m . . However, when the gray voltage generator 800 does not provide all of the gray voltages but provides only a limited number of reference gray voltages, the data driver 500 divides the reference gray voltages to generate a desired data voltage.

The backlight unit 900 is mounted on the side or the back of the liquid crystal panel assembly 300 and includes a red light source unit RL, a green light source unit GL, and a blue light source unit BL. In this case, each light source unit RL, GL, BL includes at least one light source, and in this case, the light source may be a red, green, or blue light emitting diode.

The light source controller 910 outputs a light source control signal for controlling the blinking of the light sources RL, GL, and BL.

As shown in FIGS. 1 and 3, the signal controller 600 includes a signal processor 610 and a memory 620, and includes a gate driver 400, a data driver 500, a light source controller 910, and the like. To control. The memory unit 620 includes a plurality of, for example, four frame memories 621-624 connected to the signal processor 610. Each frame memory of the memory unit 620 (621-624) stores the video signal output from the signal processor 610 in units of frames. Unlike FIG. 1, the memory unit 620 may be mounted outside the signal controller 600.

Each of the driving devices 400, 500, 600, 800, and 910 may be mounted directly on the liquid crystal panel assembly 300 in the form of at least one integrated circuit chip, or may be a flexible printed circuit film (not shown). It may be mounted on the liquid crystal panel assembly 300 in the form of a tape carrier package (TCP), or mounted on a separate printed circuit board (not shown). Alternatively, these driving devices 400, 500, 600, 800, and 910 may be connected to the liquid crystal panel assembly 300 together with the signal lines G ₁ -G _n , D ₁ -D _m and the thin film transistor switching element Q. It may be integrated into. In addition, the driving devices 400, 500, 600, 800, and 910 may be integrated into a single chip, in which case at least one of them or at least one circuit element constituting them may be outside the single chip.

The operation of the liquid crystal display device will now be described in detail.

The signal processor 610 of the signal controller 600 receives an input image signal R, G, and B and an input control signal for controlling the display thereof from an external graphic controller (not shown). The input image signals R, G and B contain luminance information of each pixel PX and the luminance has a predetermined number, for example, 1024 (= 2 ¹⁰ ), 256 (= 2 ⁸ ) 2 ⁶ ) gray levels. Examples of the input control signal include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a main clock MCLK, and a data enable signal DE.

The signal processor 610 of the signal controller 600 properly processes the input image signals R, G, and B and the input control signal according to the operating conditions of the liquid crystal panel assembly 300.

That is, the signal processor 610 of the signal controller 600 may convert the three-color input image signals R, G, and B into four color image signals based on the input image signals R, G, and B and the input control signal. After conversion to ', G', B ', and W), the data is sequentially recorded in the frame memories 621-624 of the memory unit 620. Then, the signal processor 610 of the signal controller 600 changes the frame frequency to store the image signals R ', G', B ', and W stored in two adjacent frame memories of the frame memories 621-624. Read simultaneously and select one image signal (R ', G', B ', W), and at this time, a black gray image signal may be selected according to the difference between the two image signals. The operation of the signal processor 610 and the memory unit 620 of the signal controller 600 will be described in more detail below.

In addition, the signal processor 610 of the signal controller 600 may control the gate control signal CONT1, the data control signal CONT2, and the light source control signal CONT3 based on the input image signals R, G, and B and the input control signal. And the like, the gate control signal CONT1 is sent to the gate driver 400, the data control signal CONT2 and the processed image signal DAT are sent to the data driver 500, and the light source control signal CONT3. To the light source controller 910. The gate control signal CONT1 includes at least one clock signal for controlling the output period of the scan start signal STV indicating the start of scanning and the gate-on voltage Von. The gate control signal CONT1 may further include an output enable signal OE that defines the duration of the gate on voltage Von.

The data control signal CONT2 is a load signal for applying an analog data voltage to the horizontal synchronization start signal STH indicating the start of transmission of the digital image signal for one row of pixels PX and the data lines D ₁ -D _m . (LOAD) and data clock signal HCLK. The data control signal CONT2 is also an inverted signal that inverts the voltage polarity of the analog data voltage relative to the common voltage Vcom (hereafter referred to as "polarity of the data voltage" by reducing the "polarity of the data voltage relative to the common voltage"). (RVS) may be further included.

The light source control signal CONT3 includes red, green, and blue light source control signals that turn on or off each light source unit RL, GL, BL at a corresponding time based on the gate signal.

According to the data control signal CONT2 from the signal controller 600, the data driver 500 performs four data scanning operations during one frame. That is, the data driver 500 generates a digital image signal DAT for one row of pixels PX during each of the red subframe, the green subframe, the blue subframe, and the white subframe included in one frame. The digital image signal DAT is converted into an analog data signal by receiving a gray voltage corresponding to each digital image signal DAT, and then applied to the corresponding data lines D ₁ -D _m . At this time, during each of the red, green, blue, and white sub-frames, the digital image signal DAT corresponding to the color stored in the frame memory 621-624 of the memory unit 620, that is, red, green, and blue Alternatively, the white digital image signal DAT is applied to the data driver 500, or the black gray digital image signal DAT is the data driver 500 instead of the red, green, blue or white digital image signal DAT. Is applied to. As such, one frame is divided into four subframes (red, green, blue and white subframes), and all subframes have the same time, but all may be different or only some.

The gate driver 400 applies the gate-on voltage Von to the gate lines G ₁ -G _n in response to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G ₁ -G _n . Turn on the switching element (Q) connected to.

Then, the data voltages applied to the data lines D ₁ -D _m are applied to the corresponding pixels PX through the turned-on switching elements Q.

The difference between the data voltage applied to the pixel PX and the common voltage Vcom appears as the charging voltage of the liquid crystal capacitor Clc, that is, the pixel voltage. The liquid crystal molecules have different arrangements according to the magnitude of the pixel voltage, and thus the polarization of light passing through the liquid crystal layer 3 changes. This change in polarization is caused by a change in the transmittance of light by the polarizer attached to the display panel assembly 300, whereby the pixel PX displays the luminance represented by the gray level of the image signal DAT.

This process is repeated in units of one horizontal period (also referred to as "1H" and equal to one period of the horizontal sync signal Hsync and the data enable signal DE), thereby all the gate lines G ₁ -G _n. ), The gate-on voltage Von is sequentially applied to all the pixels PX. When data voltages are applied to all the pixels during each subframe, the light source controller 910 turns on the light source units RL, GL, and BL based on the light source control signal CONT3. In this case, when all of the white data voltages are applied to the pixel during the white subframe, the light source controller 910 turns on all of the light source units RL, GL, and BL so that white light can be emitted.

As a result, red, green, blue, and white light is sequentially supplied during each subframe to display an image of one frame.

When one frame ends, the next frame starts and the state of the inversion signal RVS applied to the data driver 500 is controlled such that the polarity of the data voltage applied to each pixel PX is opposite to the polarity of the previous frame "Frame inversion"). At this time, the polarity of the data voltage flowing through one data line changes (for example, row inversion and dot inversion) depending on the characteristics of the inversion signal RVS in one frame, or the polarity of the data voltage applied to one pixel row is different (For example, thermal inversion, dot inversion).

Next, the operations of the signal processor 610 and the memory unit 620 of the signal controller 600 will be described in more detail with reference to FIGS. 4 and 5, 1, and 3 again.

4 is an operation timing diagram of a memory unit of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 5 is an operation flowchart of a signal processor of the liquid crystal display according to an exemplary embodiment of the present invention.

The vertical synchronization signal Vsync applied to the signal processor 610 of the signal controller 600 has a frequency of about 60 Hz. Therefore, the signal processor 610 reads the three-color input video signals R, G, and B during one frame at an input frequency of about 60 Hz (S11), and then red, green, blue, and white four-color video signals. Convert to (R ', G', B ', W) (S12).

To this end, the signal processor 610 arranges the three-color input image signals R, G, and B according to their gray levels, and at this time, determines the image signal having the lowest gray level as the white image signal W. Then, the gray level of the white image signal W is subtracted from the gray level of each of the input image signals R, G, and B, and the input image signals R, G, and B having the calculated gray level are respectively new image signals. Determined by (R ', G', B '). By the method of calculating the white image signal W, one of the newly calculated red, green, and blue image signals R ', G', and B 'has a gray level of "0". In the present embodiment, the three-color image signals R, G, and B are converted into the four-color image signals R ', G', B ', and W through this method, but the present invention is not limited thereto. Four color image signals R ', G', B ', and W may be calculated.

After calculating the four-color image signals R ', G', B ', and W using the three-color image signals R, G, and B, the signal processor 610 stores the respective memory ( The four color video signals R ', G', B ', and W for one frame are sequentially recorded on the frames 621-624 (S13). For example, four color image signals R ', G', B ', and W are written to the first memory 621 of the memory unit 620 in the "write 1" section, and the memory unit in the "write 2" section. Four color image signals R ', G', B ', and W are written to the second memory 622 of 620, and four to the third memory 623 of the memory unit 620 in the "write 3" section. The color image signals R ', G', B ', and W are written, and the four color image signals R', G ', and B are written to the fourth memory 624 of the memory unit 620 in the "write 4" section. ', W) is written, and then the four color image signals R', G ', B', and W are written from the first memory 621 again.

When recording the four-color video signals R ', G', B ', and W in each frame memory 621-624, the signal processor 610 divides the area of each frame memory 621-624 into four equal parts. The red, green, blue and white video signals R ', G', B ', and W are separately recorded in each area.

As such, while the write operation of the four color image signals R ', G', B ', and W is performed, the signal processing unit 610 may include a plurality of four frame memories 621 to 624, that is, images of adjacent frames. The video signals R ', G', B ', and W are read from the two frame memories in which the signals R', G ', B', and W are stored (S13). At this time, the write operation and the read operation of the four-color video signals R ', G', B ', and W do not occur at the same time with respect to the same frame memory 621-624. Therefore, one frame memory in which a write operation is performed and two frame memories in which a read operation is performed are different from each other.

In the read operation mode, the signal processor 610 converts the frame frequency Vsync 'for one frame into about 90 Hz, which is about 1/2 times increased by the frequency of the vertical synchronization signal Vsync. Therefore, since the processing speed increases by about 3/2 times in the read operation mode than in the write operation mode, three read operations are performed when two write operations are performed.

That is, as shown in FIG. 4, while the write operations to the first frame memory 621 and the second frame memory 622 are sequentially performed in the "write 1" section and the "write 2 section", the "read 2," Simultaneous read operations to the second and third frame memories 622 and 623 and the third and fourth frame memories 623 and 624 in the 3 "section and the" first and second read 3,4 "section. Simultaneous read operations are performed in this case, wherein the frame memory read in the "second read 3, 4" section is the same as the frame memories 623 and 624 read in the "first and second read 3,4" section, This frame is a surplus frame generated as the frame frequency increases from about 60 Hz to about 90 Hz, ie, the redundant frame reads the two frame memories read from the immediately preceding frame once more, thus, as described above, in this embodiment Surplus frames Is produced by one after completion of the read operation for the two frames, it made when the two write operations and enables the three read operations.

As such, when four color image signals R ', G', B ', and W are simultaneously read from two frame memories, the signal processor 610 may read the four color image signals R' and G 'of the two frame memories. , B ', W) is determined (S14).

That is, the signal processor 610 determines whether the read four-color image signals R ', G', B ', and W are the image signals read in the redundant frame (S14), and when the image signals are not read in the redundant frame. The signal processor 610 selects one of the two frame memories, for example, the image signals R ', G', B ', and W read from the previous frame memory among the two frame memories (S15). However, when ignoring the surplus frames, the video signals R ', G', B ', and W stored in the four frame memories 621-624 have to be sequentially selected. Image signals R ', G', B ', and W read from the frame memory can be selected. Then, the signal processor 610 may select one image signal selected from the image signals R ', G', B ', and W read from the two frame memories as the output image signal DAT during the corresponding subframe. ) Is applied (S16).

In this case, since one frame is divided into four subframes, and red, green, blue, and white image signals R ', G', B ', and W must be sequentially displayed, the frame frequency of each subframe is about 360H. Becomes As described above, each frame memory 621-624 is divided into four regions, and then red, green, blue, and white image signals R ', G', B ', and W are separately recorded in each region. Therefore, the red, green, blue, and white image signals R ', G', B ', and W are sequentially output during the corresponding subframe.

However, when the read image signals R ', G', B ', and W are the image signals read in the excess frame (S14), the signal processor 610 reads the image signals R', G 'read from the two frame memories. , B ', W) are compared (S17), and it is determined whether the difference value is larger than the set value (S18). If the difference is greater than or equal to the set value (S19), for example, when the gray level difference between the video signals of two adjacent frames is large, the signal processor 610 outputs the video signal having the black gray level to the output video signal. The data driver 500 transmits the data to the data driver 500 as DAT (S16).

However, when the difference value is smaller than the set value (S18), in the case of a still image in which the gray level difference between the video signals of two adjacent frames is large, the signal processor 610 may use one frame memory, for example, of two frame memories. The video signals R ', G', B ', and W read from the previous frame memory are selected (S20), and then transmitted to the data driver 500 as an output video signal DAT (S16). As described above, the video signals R ', G', B ', and W read out from the frame memory which comes after the two frame memories can be selected.

In this manner, the frame frequency at the time of the read operation is increased rather than the frame frequency at the time of the write operation, thereby generating a surplus frame capable of further performing the read operation. Then, when displaying a moving picture or the like in which a large difference in luminance between adjacent frames is displayed, impulsive implementation is performed pixel by pixel using the gray level of the pixel as black. As a result, the liquid crystal capacitor is not charged to the target voltage for a predetermined time due to the slow response speed of the liquid crystal, thereby reducing color breakup such as blurring and blurring of the screen, thereby improving color reproducibility. The picture quality of the device is improved. In addition, since an image signal input to the signal controller 600 at a frequency of about 60 Hz is applied to the data driver 500 at a frequency of about 360 Hz, the output frequency increases about four times compared to the input frequency, and thus decreases as the frequency increases. The flicker phenomenon is greatly reduced.

Next, referring to FIGS. 6 (a) to 6 (d), color distortion is compared when displaying an image according to the present embodiment and when displaying an image according to the prior art.

6 (a) to 6 (d) are diagrams showing the degree of occurrence of color distortion according to the display form of an image according to time variation, and FIG. 6 (a) shows a frame frequency of about 60 Hz according to the related art. Is a graph showing the degree of color distortion when an image is displayed by the red, green, and blue image signals R, G, and B on the basis thereof, and FIG. 6B is about 90 Hz according to one embodiment of the present invention. Fig. 6 (c) is a graph showing the degree of color distortion when an image is displayed by red, green and blue image signals R, G, and B based on the frame frequency of Fig. 6 (c) is an embodiment of the present invention. Therefore, when the redundant frame is inserted, it is a graph showing the degree of color distortion when the image is displayed by the red, green and blue video signals (R, G, B), Figure 6 (d) is an embodiment of the present invention For example, when the video signal in the redundant frame is black, the red, green, and blue video signals (R, G, B) It is a graph showing the degree of distortion when the image is displayed. Here, reference numerals "PB1", "PB2", "PB3", "PB2 '", and "PB4" each represent an image for any one pixel displayed in a unit frame.

The degree of color distortion increases with a lower frame frequency. 6 (a) shows that an image of any one pixel changes from “PB2” to “PB1” when the unit frame frequency is about 60 Hz, and FIG. 6 (a) shows excess when the unit frame frequency is about 90 Hz. It shows that a frame is inserted and the image for any one pixel changes to PB2-PB3-PB1. Accordingly, it can be seen that the portion (color distortion portion) B, which is displayed by mixing two colors at the interface of the displayed images PB1, PB2, and PB3, is wider than that of FIG. 6 (a). . In FIG. 6B, the image signal block PB3 is an image signal block displayed in the redundant frame.

 In addition, when the unit frame frequency is about 90 Hz as shown in FIG. It can be seen that the color distortion portion A is also reduced in -PB1 as compared with FIG. 6 (a). Unlike FIG. 6C, the same result occurs when the image in the surplus frame is the same as the image in the next frame.

Furthermore, as shown in FIG. 6 (d), when a unit frame frequency is about 90 Hz, an excess frame is inserted, and when the image PB4 for any one pixel represents black, the color distortion between adjacent frames is It does not occur, and color distortion part A does not arise.

In FIGS. 6A to 6D, "B" is a portion in which all three color image signals of red, green, and blue are mixed so that color distortion does not occur.

In the exemplary embodiment of the present invention, the signal processing unit converts the three-color image signal into a four-color image signal, and then sequentially displays each of the four color image signals during the corresponding subframe, but is not limited thereto. The present invention can also be applied to sequentially displaying corresponding video signals during the subframes.

In addition, although four frame memories that are separated in this embodiment are used, one memory is divided into four blocks in which input / output operations are separated, so that image signals R ', G', B ', and W are separated. Read and write operations may be performed.

As described above, by using a plurality of frame memories and by varying the frame frequency at the time of the write operation and the frame frequency at the time of the read operation, one write operation and two read operations are performed to generate an excess frame. Impulsive implementation is performed pixel-by-pixel because black gradation is displayed using the difference between the video signals of two adjacent frames during the redundant frame. Therefore, color distortion between frames is reduced, thereby improving image quality. Moreover, the flicker phenomenon is reduced by increasing the output frequency rather than the input frequency.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of right.

Claims (13)

A liquid crystal panel assembly having a plurality of pixels, A signal processor configured to input an image signal in units of a first frame having a first frame frequency; Multiple frame memories, A backlight unit supplying light to the plurality of pixels and including a light source unit of a plurality of colors, and A data driver which selects a gray voltage corresponding to an output image signal and applies it to the pixel as a data voltage. Including, The signal processor sequentially stores the image signals input in units of a first frame in the plurality of frame memories, and at least two frame memories different from each other in the plurality of frame memories in a second frame unit having a second frame frequency. Reads the video signal from and transfers the video signal selected in one of two frames to the data driver as the output video signal, During the sub-frames, the plurality of light source beams sequentially supply light of different colors to display the image of the one frame. Display device. In claim 1, The display device of which the magnitude of the first frame frequency is smaller than the magnitude of the second frame frequency. 3. The method of claim 2, A redundant frame having one second frame frequency is generated for each predetermined number of first frames, and the signal processor reads the image signal from two frame memories during the redundant frame. 4. The method of claim 3, The first frame frequency is 60 Hz, the second frame frequency is 90 Hz. 5. The method of claim 4, The signal processor compares two image signals read from the two frame memories with each other during the redundant frame, calculates a difference value, and outputs an image signal having a predetermined gray level when the calculated difference value is larger than a set value. A display device set as a video signal. The method of claim 5, And the predetermined gray level is a black gray level. The method of claim 6, The image signal includes image signals corresponding to a plurality of primary colors, respectively, and the signal processor divides the second frame into a plurality of subframes, and the image corresponding to one of the primary colors during each subframe. A display device for transmitting a signal to the data driver. 8. The method of claim 7, The display device of the plurality of colors includes the plurality of primary colors. delete In claim 1, And the image signal includes an image signal corresponding to each of the first primary colors. 11. The method of claim 10,  The first primary color is red, green, and blue. 12. The method of claim 11, And the signal processor converts the video signal corresponding to the first primary color into an image signal corresponding to the second primary color and stores the image signal in the frame memory. The method of claim 12, The second primary color is red, green, blue, and white.

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