KR20090070393A - A method for fabricating a nor flash memory device - Google Patents

A method for fabricating a nor flash memory device Download PDF

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KR20090070393A
KR20090070393A KR1020070138390A KR20070138390A KR20090070393A KR 20090070393 A KR20090070393 A KR 20090070393A KR 1020070138390 A KR1020070138390 A KR 1020070138390A KR 20070138390 A KR20070138390 A KR 20070138390A KR 20090070393 A KR20090070393 A KR 20090070393A
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pmos
nmos
transistor
implant
pattern
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KR100937665B1 (en
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고영선
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주식회사 동부하이텍
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures

Abstract

A method for manufacturing a NOR flash memory is provided to simplify a manufacturing process of the NOR flash memory by performing LDD(Lightly Doped Drain) implant by classifying an implant process of a logic transistor into an NMOS type and a PMOS type. An oxide layer and a gate terminal are formed on a substrate. Each device is separated to a device isolation layer. An NMOS pattern is formed in a low voltage transistor and a high voltage transistor with a P well region(S301). The implant is performed in the corresponding transistor by using the NMOS pattern(S302). A photoresist layer used for the NMOS pattern is removed when the ion implantation is complemented(S303). The PMOS pattern is formed in the low voltage transistor and the high voltage transistor of the N well region by performing a PMOS type transistor process(S304). The implant is performed in the corresponding transistor by using the PMOS pattern(S305). If the ion implantation is completed, the photoresist layer for the PMOS pattern is removed(S306).

Description

노어 플래쉬 메모리 제조방법{a method for fabricating a NOR Flash memory device}Method for fabricating a NOR Flash memory device

본 발명은 반도체 메모리 제조방법에 관한 것으로서, 더욱 상세하게는 엘디디 임플란트 공정을 단순화한 노어 플래쉬 메모리 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory, and more particularly, to a method of manufacturing a NOR flash memory in which an LED implant process is simplified.

일반적으로, 반도체 메모리 소자는 램(RAM; Random Access Memory)과 롬(ROM; Read Only Memory)으로 구분된다. 여기서, 롬(ROM)은 제조 과정에서 데이터가 입력되는 마스크 롬(Mask ROM)과 사용자가 데이터를 입력할 수 있는 피롬(PROM; Programmable ROM)으로 구분된다. 또한, 피롬에는 자외선 광원에 노출시켜 소거(erase)할 수 있는 이피롬(EPROM), 전기적으로 데이터의 입력 및 소거가 가능한 이이피롬(EEPROM; Electrically Erasable Programmable Read Only Memory), 데이터의 일괄 소거가 가능한 플래시 메모리(Flash Memory) 등이 있다.In general, semiconductor memory devices are classified into random access memory (RAM) and read only memory (ROM). The ROM is divided into a mask ROM through which data is input during a manufacturing process and a programmable ROM (PROM) through which a user may input data. In addition, pyrom includes an EPROM that can be erased by exposure to an ultraviolet light source, an EEPROM that can electrically input and erase data, and an erasure of data collectively. Flash memory.

플래시 메모리는 플로팅 게이트(Floating Gate) 및 콘트롤 게이트(Control Gate)를 포함하는 스택(Stack)형 게이트 구조를 가지고 있다. 이러한 플래시 메모리는 낸드(NAND)형과 노어(NOR)형으로 구분할 수 있는데, NOR형 플래시 메모리는 각각의 셀이 비트 라인과 접지 라인 사이에 병렬로 연결되어 있는 구조로 되어 있 다. 특히, NOR형 플래시 메모리에는 공통소스(Common Source)가 형성되는데, 즉 16개의 셀마다 1개의 콘택(Contact)이 형성되고, 이 16개의 셀의 소스 라인이 n+ 확산층으로 연결되는 구조를 갖는다.The flash memory has a stack type gate structure including a floating gate and a control gate. Such flash memory can be divided into NAND and NOR type. NOR flash memory has a structure in which each cell is connected in parallel between a bit line and a ground line. In particular, a common source is formed in a NOR-type flash memory, that is, one contact is formed every 16 cells, and the source lines of the 16 cells are connected to an n + diffusion layer.

일반적으로, 플래시 메모리 소자(Flash memory device)는 도 1에 도시된 바와 같이 셀 영역과 주변회로(Peripheral) 영역으로 분리되며, 주변회로 영역은 고전압용 트랜지스터(High voltage transistor)가 형성되는 HV(High Voltage) 영역과, 저전압용 트랜지스터(Low voltage transistor)가 형성되는 LV(Low Voltage) 영역으로 분리된다. 이러한 셀 영역과 주변회로 영역에 각각 형성되는 게이트 산화막(Gate oxide)은 각 영역의 특성에 따라 두께가 서로 다르게 형성된다. 예컨대, 셀 영역의 게이트 산화막으로는 터널 산화막(Tunnel oxide)이 형성되고, 주변회로 영역의 'High Voltage' 영역에서는 고전압용 게이트 산화막이 형성되며, 'Low Voltage' 영역에서는 저전압용 게이트 산화막이 형성된다.In general, a flash memory device is divided into a cell region and a peripheral circuit region as shown in FIG. 1, and the peripheral circuit region is a high voltage transistor (HV) in which a high voltage transistor is formed. A voltage region and a low voltage (LV) region in which a low voltage transistor is formed. Gate oxides formed in the cell region and the peripheral circuit region are formed to have different thicknesses according to the characteristics of each region. For example, a tunnel oxide film is formed as a gate oxide film in a cell region, a high voltage gate oxide film is formed in a 'high voltage' region of a peripheral circuit region, and a low voltage gate oxide film is formed in a 'low voltage' region. .

각각 N-타입과 P-타입을 가지고 있기 때문에 4가지 타입의 MOS 트랜지스터로 구성된다. 즉, 'Low Voltage' 영역은 저전압 NMOS 타입 트랜지스터와 저전압 PMOS 트랜지스터로 이루어지고, 'High Voltage' 영역은 고전압 NMOS 타입 트랜지스터와 고전압 PMOS 트랜지스터로 이루어진다. 4가지 로직 트랜지스터(Logic transistor)는 소스와 드레인을 형성하기 위해서 엘디디(Lightly doped drain: 이하 "LDD"라 칭함) 임플란트 공정을 진행해야 한다.Since each has an N-type and a P-type, it consists of four types of MOS transistors. That is, the 'Low Voltage' region consists of a low voltage NMOS type transistor and a low voltage PMOS transistor, and the 'High Voltage' region consists of a high voltage NMOS type transistor and a high voltage PMOS transistor. Four logic transistors must go through a lightly doped drain (LDD) implant process to form a source and a drain.

단채널 효과(특히 디플리션 영역의 확장에 따른 펀치-쓰루(punch through)의 억제를 위해 최근의 플래시 메모리 트랜지스터들은 LDD 구조의 소오스/드레인 전극 들을 구비한다.Recent flash memory transistors have source / drain electrodes of LDD structure to suppress short channel effects (especially punch through through expansion of the depletion region).

도 2는 종래 기술에 따른 LDD 임플란트 공정을 나타낸 흐름도이다.2 is a flowchart illustrating an LDD implant process according to the prior art.

그 공정과정을 살펴보면 크게 고전압부 공정과 저전압부 공정으로 나눌 수 있다. 먼저 고전압부 공정을 살펴보면, 고전압 NMOS 패턴을 형성하는 단계(S201), 고전압부 NMOS 트랜지스터의 임플란트를 수행하는 단계(S202), NMOS 패턴에 사용된 감광막을 제거하는 단계(S203), 고전압 PMOS 패턴을 형성하는 단계(S204), 고전압부 PMOS 트랜지스터의 임플란트를 수행하는 단계(S205), PMOS 패턴에 사용된 감광막을 제거하는 단계(S206)를 포함하여 이루어진다.Looking at the process, it can be divided into high voltage part process and low voltage part process. First, referring to the high voltage unit process, forming a high voltage NMOS pattern (S201), performing an implant of the high voltage NMOS transistor (S202), removing a photoresist film used in the NMOS pattern (S203), and removing the high voltage PMOS pattern Forming (S204), performing implantation of the high voltage PMOS transistor (S205), and removing the photosensitive film used for the PMOS pattern (S206).

한편, 저전압부 공정은 고전압부 공정과 유사한 과정을 거치게 된다. 즉, 저전압 NMOS 패턴을 형성하는 단계(S207), 저전압부 NMOS 트랜지스터의 임플란트를 수행하는 단계(S208), NMOS 패턴에 사용된 감광막을 제거하는 단계(S209), 저전압 PMOS 패턴을 형성하는 단계(S210), 저전압부 PMOS 트랜지스터의 임플란트를 수행하는 단계(S211), PMOS 패턴에 사용된 감광막을 제거하는 단계(S212)를 포함하여 이루어진다.Meanwhile, the low voltage part process is similar to the high voltage part process. That is, forming a low voltage NMOS pattern (S207), performing an implant of a low voltage portion NMOS transistor (S208), removing a photoresist film used for the NMOS pattern (S209), and forming a low voltage PMOS pattern (S210). ), Performing implantation of the low voltage PMOS transistor (S211), and removing the photoresist film used in the PMOS pattern (S212).

이와 같이, 로직 트랜지스터의 LDD 임플란트 공정을 위해 각각의 로직 트랜지스터 그룹에 따로따로 임플란트를 수행함으로써 모두 12 스텝의 공정이 필요하다. 따라서, 비용과 함께 생산성에도 영향을 미치므로 개선이 필요하다.As such, a 12-step process is required by performing implants separately for each logic transistor group for the LDD implant process of the logic transistor. Therefore, improvement is required because it affects productivity as well as cost.

본 발명은 반도체 제조 공정을 단순화하는 것을 목적으로 한다.The present invention aims to simplify the semiconductor manufacturing process.

본 발명의 다른 목적은 노어 플래쉬 메모리의 제조 공정을 단순화하는 것이다.Another object of the present invention is to simplify the manufacturing process of NOR flash memory.

본 발명의 또 다른 목적은 생산성을 향상시키고 생산 비용을 절감할 수 있는 노어 플래쉬 메모리 제조방법을 제공하는 것이다.Still another object of the present invention is to provide a NOR flash memory manufacturing method capable of improving productivity and reducing production cost.

이러한 목적을 달성하기 위한 본 발명에 따른 노어 플래쉬 메모리 제조방법은 로직 트랜지스터(Logic Transistor)의 임플란트 공정을 NMOS 타입과 PMOS 타입의 2가지 종류로 구분하여 엘디디(Lightly Doped Drain) 임플란트를 수행하는 것을 특징으로 한다.The NOR flash memory manufacturing method according to the present invention for achieving the above object is to divide the implant process of the logic transistor (Logic Transistor) into two types of NMOS type and PMOS type to perform the LED (Lightly Doped Drain) implant It features.

본 발명에 따른 노어 플래쉬 메모리 제조방법의 다른 특징은 숏 채널 효과를 줄이기 위한 엘디디(Lightly Doped Drain) 구조를 위한 임플란트 공정이, 저전압 NMOS와 고전압 NMOS 임플란트를 동시에 수행하는 NMOS 타입 트랜지스터 형성과정과 저전압 PMOS와 고전압 PMOS 임플란트를 동시에 수행하는 PMOS 타입 트랜지스터형성과정을 포함하여 이루어지는 점이다.Another feature of the method of manufacturing a NOR flash memory according to the present invention is an NMOS type transistor forming process and a low voltage, in which an implant process for a lightly doped drain structure to reduce a short channel effect simultaneously performs a low voltage NMOS and a high voltage NMOS implant. This includes the formation of a PMOS type transistor that simultaneously performs a PMOS and a high voltage PMOS implant.

본 발명에 따른 노어 플래쉬 메모리 제조방법의 세부적 특징은 상기 NMOS 타입 트랜지스터 처리과정이 P웰 영역의 저전압 및 고전압 트랜지스터에 NMOS 패턴을 동시에 형성하는 단계와 상기 NMOS 패턴을 이용하여 해당 트랜지스터에 임플란트를 수행하는 단계 및 NMOS 패턴에 사용된 감광막을 제거하는 단계로 이루어지고, 상기 PMOS 타입 트랜지스터 처리과정이 N웰 영역의 저전압 및 고전압 트랜지스터에 PMOS 패턴을 동시에 형성하는 단계와 상기 PMOS 패턴을 이용하여 해당 트랜지스터에 임플란트를 수행하는 단계 및 PMOS 패턴에 사용된 감광막을 제거하는 단계로 이루어지는 점이다.A detailed feature of the NOR flash memory manufacturing method according to the present invention is that the NMOS type transistor processing simultaneously forms an NMOS pattern on low and high voltage transistors in a P well region and performs implantation on the transistor using the NMOS pattern. And removing the photoresist film used in the NMOS pattern, wherein the PMOS type transistor processing simultaneously forms a PMOS pattern in the low and high voltage transistors of the N well region and implants the corresponding transistor using the PMOS pattern. And a step of removing the photoresist film used in the PMOS pattern.

본 발명에 따른 플래쉬 메모리 제조방법은 다음과 같은 효과를 갖는다.The flash memory manufacturing method according to the present invention has the following effects.

첫째, LDD 임플란트 공정을 단순화함으로써 생산성을 향상시킨다.First, productivity is improved by simplifying the LDD implant process.

둘째, LDD 임플란트 공정의 단순화에 따라 비용이 절감된다.Second, costs are reduced by simplifying the LDD implant process.

셋째, LDD 임플란트 공정을 단순화함으로써 생산에 소요되는 시간이 단축된다.Third, the time required for production is reduced by simplifying the LDD implant process.

이하, 첨부된 도면을 참조로 본 발명에 따른 플래쉬 메모리 제조 방법의 진행과정을 설명하기로 한다.Hereinafter, a process of manufacturing a flash memory according to the present invention will be described with reference to the accompanying drawings.

도 3은 본 발명에 따른 LDD 임플란트 공정을 나타낸 흐름도이다. 종래 기술과 달리 본 발명에 따른 LDD 임플란트 공정은 모두 6개의 공정으로 이루어진다.3 is a flowchart illustrating an LDD implant process according to the present invention. Unlike the prior art, the LDD implant process according to the present invention consists of all six processes.

크게 숏 채널 효과를 줄이기 위한 엘디디(Lightly Doped Drain) 구조를 위한 임플란트 공정은 NMOS 타입 트랜지스터 형성과정과 PMOS 타입 트랜지스터형성과정을 포함하여 이루어진다. 또한, NMOS 타입 트랜지스터 형성과정에서는 저전압 NMOS와 고전압 NMOS 임플란트를 동시에 수행하고, PMOS 타입 트랜지스터 형성과정 에서는 저전압 PMOS와 고전압 PMOS 임플란트를 동시에 수행한다.The implant process for the lightly doped drain structure, which greatly reduces the short channel effect, includes an NMOS type transistor formation process and a PMOS type transistor formation process. In the process of forming an NMOS type transistor, a low voltage NMOS and a high voltage NMOS implant are simultaneously performed. In the process of forming a PMOS type transistor, a low voltage PMOS and a high voltage PMOS implant are simultaneously performed.

먼저, 도 4a와 같이 기판(1) 위에 산화막(3)과 게이트단(4)이 형성되어 있고, 각 소자는 소자 분리막(4)으로 분리되어 있다. P웰 영역을 갖는 저전압 및 고전압 트랜지스터에 NMOS 패턴(5)을 동시에 형성한다 (S301).First, as shown in FIG. 4A, an oxide film 3 and a gate end 4 are formed on a substrate 1, and each device is separated by an element isolation film 4. The NMOS pattern 5 is simultaneously formed in the low voltage and high voltage transistors having the P well region (S301).

이어, 도 4b에서 보는 바와 같이, 상기 NMOS 패턴을 이용하여 해당 트랜지스터에 임플란트를 수행한다 (S302).Subsequently, as shown in FIG. 4B, an implant is performed on the transistor using the NMOS pattern (S302).

이온 주입이 완료되면, NMOS 패턴에 사용된 감광막을 제거하면 도 4c와 같이 나타난다 (S303).When the ion implantation is completed, removing the photoresist film used in the NMOS pattern appears as shown in Figure 4c (S303).

PMOS 타입 트랜지스터 처리 과정이 수행된다. 도 4d와 같이 N웰 영역의 저전압 및 고전압 트랜지스터에 PMOS 패턴(5)을 동시에 형성한다 (S304).PMOS type transistor processing is performed. As shown in FIG. 4D, the PMOS pattern 5 is simultaneously formed in the low voltage and high voltage transistors of the N well region (S304).

이어, 도 4e에서 보는 바와 같이, 상기 PMOS 패턴을 이용하여 해당 트랜지스터에 임플란트를 수행한다 (S305).Subsequently, as illustrated in FIG. 4E, an implant is performed on the corresponding transistor using the PMOS pattern (S305).

이온 주입이 완료되면, PMOS 패턴에 사용된 감광막을 제거하면 도 4f와 같이 나타난다 (S306).When the ion implantation is completed, the photoresist film used for the PMOS pattern is removed, as shown in FIG. 4F (S306).

이와 같이, 스텝 S301, S302, S303에서 저전압 NMOS 및 고전압 NMOS의 LDD 임플란트를 동시에 진행한다. 마찬가지로 스텝 S304, S305, S306에서 저전압 PMOS 및 고전압 PMOS의 LDD 임플란트를 동시에 진행한다. 따라서, 각각 진행되던 LDD 임플란트 공정 스텝을 절반으로 줄일 수 있다.In this way, the LDD implants of the low voltage NMOS and the high voltage NMOS are simultaneously performed in steps S301, S302, and S303. Similarly, in step S304, S305, S306, the LDD implant of a low voltage PMOS and a high voltage PMOS advances simultaneously. Therefore, the steps of the LDD implant process that have been progressed can be reduced by half.

도 1은 플래쉬 메모리의 구조를 개략적으로 나타낸 예시도이다.1 is an exemplary view schematically showing a structure of a flash memory.

도 2는 종래 기술에 따른 LDD 임플란트 공정을 나타낸 흐름도이다.2 is a flowchart illustrating an LDD implant process according to the prior art.

도 3은 본 발명에 따른 LDD 임플란트 공정을 나타낸 흐름도이다.3 is a flowchart illustrating an LDD implant process according to the present invention.

도 4a 내지 도 4f는 본 발명에 따른 LDD 임플란트 공정에 따른 플래쉬 소자의 단면 예시도이다.4A to 4F are cross-sectional views of a flash device according to an LDD implant process according to the present invention.

Claims (3)

로직 트랜지스터(Logic Transistor)의 임플란트 공정을 NMOS 타입과 PMOS 타입의 2가지 종류로 구분하여 엘디디(Lightly Doped Drain) 임플란트를 수행하는 것을 특징으로 하는 노어 플래쉬 메모리 제조방법.A method of manufacturing a NOR flash memory, comprising performing a lightly doped drain implant by dividing a logic transistor implant process into two types, an NMOS type and a PMOS type. 숏 채널 효과를 줄이기 위한 엘디디(Lightly Doped Drain) 구조를 위한 임플란트 공정이,The implant process for the lightly doped drain structure to reduce the short channel effect, 저전압 NMOS와 고전압 NMOS 임플란트를 동시에 수행하는 NMOS 타입 트랜지스터 형성과정;Forming an NMOS type transistor which simultaneously performs a low voltage NMOS and a high voltage NMOS implant; 저전압 PMOS와 고전압 PMOS 임플란트를 동시에 수행하는 PMOS 타입 트랜지스터형성과정을 포함하여 이루어지는 것을 특징으로 하는 노어 플래쉬 메모리 제조방법.A method of manufacturing a NOR flash memory comprising the step of forming a PMOS transistor which simultaneously performs a low voltage PMOS and a high voltage PMOS implant. 제 2 항에 있어서, 상기 NMOS 타입 트랜지스터 처리과정은,The process of claim 2, wherein the processing of the NMOS type transistor comprises: P웰 영역의 저전압 및 고전압 트랜지스터에 NMOS 패턴을 동시에 형성하는 단계;Simultaneously forming NMOS patterns in the low voltage and high voltage transistors in the P well region; 상기 NMOS 패턴을 이용하여 해당 트랜지스터에 임플란트를 수행하는 단계;Performing an implant on a corresponding transistor using the NMOS pattern; 감광막을 제거하는 단계로 이루어지고,Removing the photoresist film, 상기 PMOS 타입 트랜지스터 처리과정은,The PMOS transistor processing process, N웰 영역의 저전압 및 고전압 트랜지스터에 PMOS 패턴을 동시에 형성하는 단계;Simultaneously forming a PMOS pattern in the low voltage and high voltage transistors of the N well region; 상기 PMOS 패턴을 이용하여 해당 트랜지스터에 임플란트를 수행하는 단계;Performing an implant on a corresponding transistor using the PMOS pattern; 감광막을 제거하는 단계로 이루어지는 것을 특징으로 하는 노어 플래쉬 메모리 제조방법.NOR flash memory manufacturing method comprising the step of removing the photosensitive film.
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