JPS61174667A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS61174667A
JPS61174667A JP60014733A JP1473385A JPS61174667A JP S61174667 A JPS61174667 A JP S61174667A JP 60014733 A JP60014733 A JP 60014733A JP 1473385 A JP1473385 A JP 1473385A JP S61174667 A JPS61174667 A JP S61174667A
Authority
JP
Japan
Prior art keywords
well
region
implantation
oxide film
channel transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60014733A
Inventor
Kazuo Kunimasa
Original Assignee
Nec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corp filed Critical Nec Corp
Priority to JP60014733A priority Critical patent/JPS61174667A/en
Publication of JPS61174667A publication Critical patent/JPS61174667A/en
Application status is Pending legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS

Abstract

PURPOSE:To shorten a term of works by forming a P well and a drain low concentration region in a P channel transistor through the implantation of the same ions and an N well and a drain low concentration region in an N channel transistor through the implantation of the same ions and simultaneously driving in both the wells and the regions. CONSTITUTION:A P well forming region section in an oxide film 102 formed onto an N-type semiconductor substrate 101 is removed and a thin oxide film 102' is shaped, and a P well 30 is formed through ion implantation. The P well region section and an oxide film 102 on a low-concentration drain region in a P channel transistor are removed and a thinn oxide film is shaped, and ion implantation regions 104', 105' are formed through the implantation of a P-type impurity. A resist 18 is applied, an N well formig section and the oxide film 102 in a drain low concentration region in an N channel transistor are removed, and ion implantation region regions 106', 107' are shaped through the implantation of an N-type impurity. The resist 108 is peeled off, and a P well 104 for a low voltage element, an N well 107, a P-type drain low- concentration region 105 in a high voltage element and an N-type drain low- concentration region 106 are formed through a diffusion at two steps.
JP60014733A 1985-01-29 1985-01-29 Manufacture of semiconductor device Pending JPS61174667A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60014733A JPS61174667A (en) 1985-01-29 1985-01-29 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60014733A JPS61174667A (en) 1985-01-29 1985-01-29 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS61174667A true JPS61174667A (en) 1986-08-06

Family

ID=11869324

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60014733A Pending JPS61174667A (en) 1985-01-29 1985-01-29 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS61174667A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0193161A (en) * 1987-10-05 1989-04-12 Sharp Corp Complementary mos transistor
JPH02284462A (en) * 1989-03-17 1990-11-21 Delco Electron Corp Process for forming high/low voltage cmos transistor on single integrated circuit chip
JPH04320368A (en) * 1991-04-19 1992-11-11 Sanyo Electric Co Ltd Semiconductor device
JPH07106429A (en) * 1993-09-30 1995-04-21 Nec Corp Fabrication of semiconductor device
EP0730305A1 (en) * 1995-02-28 1996-09-04 SGS-THOMSON MICROELECTRONICS S.r.l. High voltage N-channel MOSFET in CMOS-type technology and relating manufacturing process
US5698457A (en) * 1995-02-28 1997-12-16 Nec Corporation Method for manufacturing high voltage semiconductor device
JP2008166788A (en) * 2006-12-29 2008-07-17 Dongbu Hitek Co Ltd Dmos device and method for manufacturing same
KR100937665B1 (en) * 2007-12-27 2010-01-19 주식회사 동부하이텍 A method for fabricating a NOR Flash memory device
JP2014192279A (en) * 2013-03-27 2014-10-06 New Japan Radio Co Ltd Semiconductor device manufacturing method

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0193161A (en) * 1987-10-05 1989-04-12 Sharp Corp Complementary mos transistor
JPH02284462A (en) * 1989-03-17 1990-11-21 Delco Electron Corp Process for forming high/low voltage cmos transistor on single integrated circuit chip
JPH04320368A (en) * 1991-04-19 1992-11-11 Sanyo Electric Co Ltd Semiconductor device
JPH07106429A (en) * 1993-09-30 1995-04-21 Nec Corp Fabrication of semiconductor device
EP0730305A1 (en) * 1995-02-28 1996-09-04 SGS-THOMSON MICROELECTRONICS S.r.l. High voltage N-channel MOSFET in CMOS-type technology and relating manufacturing process
US5698457A (en) * 1995-02-28 1997-12-16 Nec Corporation Method for manufacturing high voltage semiconductor device
US5850360A (en) * 1995-02-28 1998-12-15 Sgs-Thomson Microelectronics, S.R.L. High-voltage N-channel MOS transistor and associated manufacturing process
JP2008166788A (en) * 2006-12-29 2008-07-17 Dongbu Hitek Co Ltd Dmos device and method for manufacturing same
KR100937665B1 (en) * 2007-12-27 2010-01-19 주식회사 동부하이텍 A method for fabricating a NOR Flash memory device
JP2014192279A (en) * 2013-03-27 2014-10-06 New Japan Radio Co Ltd Semiconductor device manufacturing method

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