KR20090069936A - Method for manufacturing nonvolatile memory device - Google Patents

Abstract

A method for manufacturing nonvolatile memory device is provided to simplify a process and reduce manufacturing costs by forming a drain contact plug and a source contact plug at one mask process. An inter insulating layer(112B) is formed to cover a substrate formed a first and a second selection transistor and an memory cell. A first contact hole is formed by etching the inter insulating layer to expose a drain region of a first selection transistor and a source region of a second selection transistor. A first and a second contact plug(114,115A) are formed so that the first contact hole be buried, and a hard mask is formed in order to cover the inter-layer insulating film and the first and the second contact plug. The hard mask is etched and the second contact plug upper part is exposed, and a second contact plug is formed by recessing the second contact plug.

Description

Manufacturing method of nonvolatile memory device {METHOD FOR MANUFACTURING NONVOLATILE MEMORY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method of manufacturing a nonvolatile memory device, and more particularly, to a NAND type flash memory device in which a plurality of memory cells are connected in series to form a string. It relates to a manufacturing method.

NAND flash memory devices, which are nonvolatile memory devices, are wired to transfer driving voltages (bias voltages) applied from the outside through metal wirings to the source and drain regions, which are junction regions formed in the lower semiconductor structure layers, particularly the active regions. There is a need for a contact plug that connects the contact area with the junction. The contact plug is formed not only in the cell region in which the memory cell is formed, but also in the peripheral circuit region in which a driving circuit for driving the memory cell, for example, a decoder and a page buffer, is formed.

In general, a contact plug formed in a cell region of a NAND flash memory device includes a drain contact plug connecting a string to a bit line and a source contact plug connecting a string to a ground voltage source. Used. The drain contact plug is formed in a hole type, and the source contact plug is formed in a line type as a common source line.

In the method of manufacturing the NAND flash memory device, the source contact plug forming process and the drain contact plug forming process are independently performed using different mask processes in order to prevent an electrical short between the source contact plug and the drain contact plug. In one example, the drain contact plug is formed after the source contact plug is formed. As described above, in the manufacturing method of the NAND flash memory device according to the related art, since the source contact plug and the drain contact plug are independently performed using different mask processes, the process becomes complicated and the manufacturing cost increases. .

Accordingly, the present invention has been proposed to solve the problems of the prior art, and provides a method of manufacturing a nonvolatile memory device which can reduce the manufacturing cost of the device by reducing the number of mask processes and planarization processes while simplifying the manufacturing process. There is a purpose.

According to an aspect of the present invention, there is provided a nonvolatile memory including a plurality of strings including first and second select transistors and a plurality of memory cells connected in series between the first and second select transistors. A method of manufacturing a device, the method comprising: forming an interlayer insulating film to cover a substrate on which the first and second selection transistors and the memory cell are formed; etching the interlayer insulating film to etch a drain region of the first selection transistor Forming a first contact hole through which a source region of the second selection transistor is exposed, forming first and second contact plugs so as to fill the first contact hole, respectively; Forming a hard mask to cover the second contact plug, and etching the hard mask to form an upper portion of the second contact plug. Forming a second contact hole by recessing the second contact plug to a predetermined depth, and oxidizing an upper portion of the second contact plug to form an oxide layer in which the second contact hole is buried. It provides a method of manufacturing a nonvolatile memory device comprising the step of.

According to another aspect of the present invention, a plurality of strings including a first and a second selection transistor and a plurality of memory cells connected in series between the first and second selection transistors are provided in a cell region. In the method of manufacturing a nonvolatile memory device having a high voltage transistor formed in the peripheral circuit region, an interlayer insulating film is formed to cover the first and second selection transistors, the memory cell, and the substrate on which the high voltage transistor is formed. Etching the interlayer insulating layer to form a first contact hole through which the drain region of the first select transistor and the source region of the second select transistor are respectively exposed; Forming first and second contact plugs, and forming the interlayer insulating film and the first and second contact plugs. Forming a hard mask, exposing the second contact plug and the gate electrode of the high voltage transistor by etching the hard mask, and recessing the second contact plug to a predetermined depth for a second contact. A method of manufacturing a nonvolatile memory device, the method comprising forming a hole and oxidizing an upper portion of the second contact plug to form an oxide layer in which the second contact hole is embedded.

According to the present invention including the above-described configuration, the following effects can be obtained.

First, according to the present invention, the drain contact plug and the source contact plug are simultaneously formed through one mask process and the planarization process, thereby simplifying the process and lowering the manufacturing cost.

Second, according to the present invention, after the source contact plug and the drain contact plug are formed on the same layer, the source contact plug is recessed to a predetermined depth. The top of the source contact plug is then oxidized to fill the recessed portions with an oxide layer, thereby implementing electrical isolation between them (the source contact plug and the drain contact plug), thereby forming a drain contact plug as compared to the prior art. By reducing the thickness of the insulating interlayer by the thickness of the oxide layer, an etching margin may be secured during the process of forming a contact hole for a drain contact plug.

For reference, in the related art, for the electrical insulation between the source contact plug and the drain contact plug, the source contact plug is formed in the first interlayer insulating film, and then the second interlayer insulating film is formed thereon, and the drain contact plug therein. Was formed. As described above, in the prior art, since the interlayer insulating film is formed of two layers, the height of the interlayer insulating film increases so that the etching process is difficult during the formation of the contact hole for the drain contact plug.

Hereinafter, with reference to the accompanying drawings, the most preferred embodiment of the present invention will be described. In addition, in the drawings, the thicknesses and spacings of layers and regions are exaggerated for ease of explanation and clarity, and when referred to as being on or above another layer or substrate, it is different. It may be formed directly on the layer or the substrate, or a third layer may be interposed therebetween. In addition, the parts denoted by the same reference numerals throughout the specification represent the same layer, and when the reference numerals include the English, it means that the same layer is partially modified through an etching or polishing process.

Example

1A to 1H are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with an embodiment of the present invention. As an example, a method of forming a contact plug of a NAND flash memory device will be described. In addition, among the regions indicated in the drawings, 'CELL' represents a cell region and 'PERI' represents a peripheral circuit region.

First, as illustrated in FIG. 1A, triple n-wells (not shown) and p-wells (not shown) are formed in a semiconductor substrate 100, for example, a p-type substrate, and then ion implantation for adjusting the threshold voltage is performed. Carry out the process.

Subsequently, any one selected from the Conventional-Shallow Trench Isolation (C-STI), Self Aligned STI (SA-STI), Advanced Self Aligned-STI (ASA-STI), or Self Aligned Floating Gate (SAFG) processes may be performed. An isolation layer (not shown) is formed, and a drain select transistor DST (hereinafter referred to as a first select transistor) and a source select transistor SST (hereinafter referred to as a second select transistor) are formed on the semiconductor substrate 100. ), The high voltage transistor HVT, and the gate electrodes 105, 106, 107, and 108 of the memory cells M0 to M31 are formed, respectively. In this case, the gate electrodes 105, 106, 107, and 108 include a gate insulating film (or tunnel insulating film) 101, a floating gate 102, a dielectric film 103, and a control gate 104.

In addition, each of the gate electrodes 105, 106, 107, and 108 further includes a conductive layer (not shown) and a hard mask (not shown) formed on the control gate 104. In this case, the conductive layer may be formed of a transition metal, an alloy film in which two kinds of transition metals are mixed, a silicide layer made of a transition metal, or a laminated structure in which these are stacked. For example, iron (Fe), cobalt (Co), tungsten (W), nickel (Ni), palladium (Pd), platinum (Pt), molybdenum (Mo) or titanium (Ti) is used as the transition metal. In addition, a tungsten silicide layer (Wsix) is used as the metal silicide layer.

In addition, the hard mask may be formed of a nitride film such as silicon nitride film (Si ₃ N ₄ ), and in this case, a buffer film (not shown) may be further formed between the conductive layer and the hard mask to protect the conductive layer. Can be. In this case, the buffer film is formed of an oxide film.

In detail, the gate electrode 108 of the memory cells M0 to M31 has a structure in which the gate insulating film 101, the floating gate 102, the dielectric film 103, and the control gate 104 are stacked. On the other hand, the gate electrodes 105, 106, and 107 of the first and second selection transistors DST and SST and the high voltage transistor HVT are formed in the same stacked structure as the gate electrode 108, but the dielectric film 103 The through-holes are formed to have a structure in which the floating gate 102 and the control gate 104 are electrically connected to each other. In this case, the gate insulating film 101 may be formed of an oxide film. In addition, the dielectric film 103 may be formed of a stacked structure of an oxide film-nitride film-oxide film, or a dielectric film of any one selected from high dielectric film-Al ₂ O ₃ , HfO ₂ , and ZrO ₂ -or a mixed film or a laminated film thereof. .

Subsequently, a junction region 109 is formed in the substrate 100 exposed between the gate electrodes 105, 106, 107, and 108 to function as a source and a drain region, respectively. In this case, the junction region 109 may include a lightly doped drain (LDD) region to prevent short channel effects.

Subsequently, an insulating film for a spacer is deposited along the upper surface of the structure including the gate electrodes 105, 106, 107, and 108, and then a dry etching process such as an etch back process is performed to perform the gate electrode ( Spacers 110 are formed on both side walls of the 105, 106, 107, and 108. In this case, the spacer insulating film may be formed of an oxide film, a nitride film, or a laminated film in which these layers are stacked.

Subsequently, an etch stop layer 111 functioning as a self aligned contact (SAC) layer is formed along the upper surface of the structure including the spacer 110. In this case, the etch stop layer 111 may be formed of a nitride layer, for example, silicon nitride layer (Si ₃ N ₄ ), but the present invention is not limited thereto. Any material that can be used can be used. For example, the etch stop layer 111 is formed at a temperature of 600 to 800 ° C using DCS (DiChloroSilane (SiH ₂ Cl ₂ )) and NH ₃ gas.

The etch stop layer 111 may be formed only in the cell region CELL.

Subsequently, an interlayer insulating layer 112 is formed on the etch stop layer 111 so as to fill the gate electrodes 105, 106, 107, and 108. In this case, the interlayer insulating layer 112 is formed of an oxide-based material, preferably silicon oxide (SiO ₂ ) containing silicon. More specifically, BPSG (BoroPhosphoSilicate Glass) film, PSG (PhosphoSilicate Glass) film, USG (Un-doped Silicate Glass) film, TEOS (Tetra Ethyle Ortho Silicate) film, SOG (Spin On Glass) film, HDP (High Density Plasma) ) Film or a carbon doped oxide (CDO) film. Preferably, it is formed of an HDP film having excellent embedding characteristics.

Subsequently, a planarization process may be performed on the interlayer insulating layer 112 to planarize the upper surface. At this time, the planarization process is performed by a chemical mechanical polishing (CMP) process.

Subsequently, as shown in FIG. 1B, one of the junction regions 109 of the first and second selection transistors DST and SST is locally etched by locally etching the interlayer insulating layer 112A and the etch stop layer 111A. Alternatively, the contact hole 113 (hereinafter, referred to as a first contact hole) in which the source region is partially or fully exposed is formed. In this case, the etching process is preferably performed by a dry etching process using a plasma etching equipment so that the cross section to be etched has a vertical profile (vertical profile).

Subsequently, as shown in FIG. 1C, the conductive material is formed to fill the first contact holes 113 (see FIG. 1B), respectively, and then a planarization process such as a CMP process or an etch back process is performed. An isolated drain contact plug 114 (hereinafter referred to as a first contact plug) and a source contact plug 115 (hereinafter referred to as a second contact plug) are formed in the first contact hole 113. In this case, the conductive material may be formed of a conductive material such as a polysilicon film or a transition metal doped with impurity ions to have conductivity.

Subsequently, as illustrated in FIG. 1D, the hard mask 116 is formed to cover the interlayer insulating layer 112B and the first and second contact plugs 114 and 115. In this case, the hard mask 116 is formed of a material having a high etching selectivity with the interlayer insulating film 112B. For example, when the interlayer insulating film 112B is formed of an oxide film, it is formed of a nitride film, more specifically a silicon nitride film.

Subsequently, the hard mask 116 is etched to expose the second contact plug 115 and to expose the interlayer insulating layer 112B at a portion corresponding to the gate electrode 107 of the high voltage transistor. As a result, a hard mask pattern is formed.

Subsequently, the interlayer insulating layer 112B and the etch stop layer 111B are etched using the hard mask pattern as an etch mask to expose an upper portion of the gate electrode 107 of the high voltage transistor HVT.

Subsequently, as shown in FIG. 1E, the exposed second contact plug 115A is partially etched to recess the predetermined depth, thereby contacting the contact hole 117 (hereinafter referred to as a second contact hole). Form. In this case, the etching process is performed by a dry etching process, for example, an etch back process using a plasma etching equipment. For example, the etching process uses an etching gas having a high etching selectivity for the oxide film (interlayer insulating film) and the nitride film (hard mask) as the source gas. More specifically, hydrogen bromide (HBr), chlorine (Cl ₂ ) or a mixed gas thereof (HBr / Cl ₂ ) is used as the source gas, and oxygen (O ₂ ) is further added and used.

On the other hand, in the same figure, the depth of the second contact hole 117 is not limited.

Subsequently, as illustrated in FIG. 1F, an oxide layer 118 in which the second contact hole 117 is embedded by oxidizing an upper portion of the second contact plug 115A exposed through the second contact hole 117 (see FIG. 1E). ). Preferably, the top surface of the oxide layer 118 is formed to extend to the top surface of the hard mask 116. In this case, the oxidation process may use any one selected from an oxidation process using wet oxidation, dry oxidation, or radical ions. For example, when the second contact plug 115A is made of a polycrystalline silicon film, the wet oxidation process is performed at a temperature of 900 to 1000 ° C. using water vapor as an oxidizing gas. Dry oxidation process is performed at 1000 ~ 1200 ℃ using pure oxygen as oxidizing gas.

Subsequently, as shown in FIG. 1G, the hard mask 116A is partially etched to expose the upper portion of the first contact plug 114, while the opening-high voltage transistor HVT formed in the interlayer insulating layer 112B in FIG. 1D. An opening having a wider width is formed in a portion corresponding to the opening through which the gate electrode 107 is exposed. In this case, the opening in which the upper portion of the first contact plug 114 is exposed is formed to have a width larger than the width of the first contact plug 114.

Subsequently, as shown in FIG. 1H, metal wirings 119 are formed on the first contact plug 114 and the gate electrode 107 of the high voltage transistor HVT, respectively. The metal wire 119 formed on the upper portion of the first contact plug 114 among the metal wires 119 becomes a bit line. The metal wire 119 is formed of any one selected from transition metals. Preferably, it is formed of a metal selected from tungsten (W), aluminum (Al) or copper (Cu).

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In particular, although the embodiment of the present invention has been described as a NAND flash memory device as an example, this is an example, and the memory cell array can be applied to all nonvolatile memory devices having a string structure. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1A to 1H are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100: semiconductor substrate

101: gate insulating film (tunnel insulating film

102: floating gate

103: dielectric film

104: control gate

105, 106, 107, 108: gate electrode

109: junction region (source and drain regions)

110: spacer

111, 111A, 111B: Etch stop film

112, 112A, 112B: interlayer insulating film

113: first contact hole

114: first contact plug (drain contact plug)

115: second contact plug (source contact plug)

116, 116A: Hard Mask

117: second contact hole

118: oxide layer

119: metal wiring

Claims (14)

A method of manufacturing a nonvolatile memory device, comprising: a plurality of strings including first and second select transistors and a plurality of memory cells connected in series between the first and second select transistors, Forming an interlayer insulating film to cover the substrate on which the first and second selection transistors and the memory cell are formed; Etching the interlayer insulating layer to form a first contact hole exposing a drain region of the first select transistor and a source region of the second select transistor; Forming first and second contact plugs to respectively fill the first contact holes; Forming a hard mask to cover the interlayer insulating layer and the first and second contact plugs; Etching the hard mask to expose an upper portion of the second contact plug; Recessing the second contact plug to a predetermined depth to form a second contact hole; And Oxidizing an upper portion of the second contact plug to form an oxide layer in which the second contact hole is embedded Method of manufacturing a nonvolatile memory device comprising a. The method of claim 1, And the oxide layer is formed such that an upper surface thereof extends to an upper surface of the hard mask. The method of claim 1, The forming of the oxide layer is a method of manufacturing a nonvolatile memory device performed by an oxidation process. The method of claim 1, The first and second contact plugs are formed of a polysilicon film. The method of claim 1, And the hard mask is formed of a nitride film. The method of claim 1, After forming the oxide layer, Etching the hard mask to expose the first contact plug; And Forming a metal wire on the exposed first contact plug Method of manufacturing a nonvolatile memory device further comprising. The method of claim 1, And recessing the second contact plug to a predetermined depth by using an etch back process. Fabrication of a nonvolatile memory device in which a plurality of strings including first and second selection transistors and a plurality of strings of memory cells connected in series between the first and second selection transistors are formed, and a high voltage transistor is formed in the peripheral circuit region. In the method, Forming an interlayer insulating film covering the substrate on which the first and second selection transistors, the memory cell, and the high voltage transistor are formed; Etching the interlayer insulating layer to form a first contact hole through which a drain region of the first select transistor and a source region of the second select transistor are respectively exposed; Forming first and second contact plugs to respectively fill the first contact holes; Forming a hard mask to cover the interlayer insulating layer and the first and second contact plugs; Etching the hard mask to expose the second contact plug and the gate electrode of the high voltage transistor; Recessing the second contact plug to a predetermined depth to form a second contact hole; And Oxidizing an upper portion of the second contact plug to form an oxide layer in which the second contact hole is embedded Method of manufacturing a nonvolatile memory device comprising a. The method of claim 8, And the oxide layer is formed such that an upper surface thereof extends to an upper surface of the hard mask. The method of claim 8, The forming of the oxide layer is a method of manufacturing a nonvolatile memory device performed by an oxidation process. The method of claim 8, The first and second contact plugs are formed of a polysilicon film. The method of claim 8, And the hard mask is formed of a nitride film. The method of claim 8, After forming the oxide layer, Etching the hard mask to expose the first contact plug; And Forming a metal wiring on the exposed first contact plug and the gate electrode of the high voltage transistor Method of manufacturing a nonvolatile memory device further comprising. The method of claim 8, And recessing the second contact plug to a predetermined depth by using an etch back process.

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