KR20090069857A - Method for forming a contact plug in semiconductor device - Google Patents

Abstract

A method for forming a contact plug in a semiconductor device is provided to intercept a leakage current by forming a short prevention layer on the interior wall of a contact hole. A gate structure(105) is formed on a substrate(100), and a junction area(107) is formed within a substrate exposed by both sides of the gate structure. An etch stop layer is formed on structure including the junction area along the top of the structure, and an inter-layer insulating film(109A) is formed on the etch stopper layer. The inter-layer insulting film is etched and A first contact hole is formed at the etch stopper layer corresponding to a junction area. The short prevention layer(112A) is formed on the inner surface of the first contact hole. The short prevention layer and the etch stopper layer are etched and a second contact hole is formed on the junction area.

Description

TECHNICAL FOR FORMING A CONTACT PLUG IN SEMICONDUCTOR DEVICE

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method of forming a contact plug of a semiconductor device, and more particularly, a method of forming a contact plug of a nonvolatile memory device.

In the NAND flash memory device, which is a nonvolatile memory device, the metal wiring transfers a driving voltage (bias voltage) applied from the outside to a lower semiconductor structure, for example, a source region and a drain region, which are junction regions. A contact plug is required to electrically connect such a junction region with each other.

In general, a contact plug formed in a cell region of a NAND flash memory device includes a drain contact plug connecting a string to a bit line and a source contact plug connecting a string to a ground voltage source. Used.

However, in the method of forming a contact plug of a NAND flash memory device according to the related art, when the distance between drain contact plugs is reduced in response to high integration of devices, shorting occurs between neighboring drain contact plugs. A problem arises. Due to these problems, a lot of difficulties arise in integrating the device.

Accordingly, the present invention has been proposed to solve the problems of the prior art, and provides a method for forming a contact plug of a semiconductor device capable of preventing electrical short circuits between neighboring drain contact plugs while implementing high integration. There is a purpose.

According to an aspect of the present invention, there is provided a method including: forming a gate structure on a substrate, forming a junction region in the substrate exposed to both sides of the gate structure, and the junction region. Forming an etch stop layer along an upper surface of the structure; forming an interlayer insulating layer on the etch stop layer; and etching the interlayer insulating layer to expose the etch stop layer at a portion corresponding to the junction region. Forming a contact hole, forming a short circuit prevention layer on an inner surface of the first contact hole, and etching the short circuit prevention layer and the etch stop layer to form a second contact hole exposing the junction region; And forming a contact plug in which the second contact hole is buried.

According to the present invention including the above-described configuration, the following effects can be obtained.

First, according to the present invention, high integration is achieved by forming a short-circuit prevention film on the inner wall of the contact hole where the contact plug is to be formed, while preventing electrical short circuit between neighboring drain contact plugs, thereby preventing leakage current at this site. In addition, the device yield can be improved by reducing power consumption and improving device operating characteristics.

Second, according to the present invention, the short circuit prevention layer is formed on the inner wall of the contact hole where the contact plug is to be formed, and the short circuit prevention layer is formed on the substrate instead of extending into the junction region. It is possible to prevent junction area degradation due to current crowding due to an ionization impact.

Hereinafter, with reference to the accompanying drawings, the most preferred embodiment of the present invention will be described. In addition, in the drawings, the thicknesses and spacings of layers and regions are exaggerated for ease of explanation and clarity, and when referred to as being on or above another layer or substrate, it is different. It may be formed directly on the layer or the substrate, or a third layer may be interposed therebetween. In addition, the parts denoted by the same reference numerals throughout the specification represent the same layer, and when the reference numerals include the English, it means that the same layer is partially modified through an etching or polishing process.

Example

1A to 1E are cross-sectional views illustrating a method of forming a contact plug of a semiconductor device according to an exemplary embodiment of the present invention. As an example, a method of manufacturing a NAND flash memory device among nonvolatile memory devices will be described for convenience of description.

First, as shown in FIG. 1A, a triple n-well (not shown) and a p-well (not shown) are formed in a semiconductor substrate 100, for example, a p-type substrate, and then a threshold voltage is formed. A control ion implantation step is carried out.

Subsequently, C-STI (Conventional-Shallow Trench Isolation), SA-STI (Self Aligned STI), ASA-STI (Advanced Self Aligned-STI) or SAFG (Self Aligned Floating Gate) processes are performed on the substrate 100. A gate structure 105 connected to the drain select line DSL is formed. In this case, the gate structure 105 includes a gate insulating film (or tunnel insulating film) 101, a floating gate 102, a dielectric film 103, and a control gate 104.

In addition, the gate structure 105 may further include a conductive layer (not shown) and a hard mask (not shown) formed on the control gate 104. In this case, the conductive layer may be formed of a transition metal, an alloy film in which two kinds of transition metals are mixed, a silicide layer made of a transition metal, or a laminated structure in which these are stacked. For example, iron (Fe), cobalt (Co), tungsten (W), nickel (Ni), palladium (Pd), platinum (Pt), molybdenum (Mo) or titanium (Ti) is used as the transition metal. In addition, a tungsten silicide layer (Wsix) is used as the metal silicide layer. In addition, the hard mask is formed of a nitride film, for example, a silicon nitride film (Si ₃ N ₄ ).

Meanwhile, the floating gate 102 and the control gate 104 are each formed of one selected from a polysilicon film or a transition metal. The dielectric film 103 is formed of a laminated structure in which an oxide film-nitride film-oxide film is laminated, or a metal oxide having a dielectric constant of 3.9 or more, such as an aluminum oxide film (Al ₂ O ₃ ), a zirconium oxide film (ZrO ₂ ), and a hafnium oxide film (HfO ₂ ). It is formed of any one selected.

Subsequently, spacers 106 are formed on both sidewalls of the gate structure 105. In this case, the spacer 106 may be formed of an oxide film, a nitride film, or a laminated film in which they are stacked.

Subsequently, a junction region 107 that functions as a source and a drain region, respectively, is formed in the substrate 100 exposed to both sides of the gate structure 105. In this case, the junction region 107 may further include a lightly doped drain (LDD) region to prevent short channel effects.

Subsequently, an etch stop layer 108 is formed of a self aligned contact (SAC) layer along the upper surface of the structure including the junction region 107. In this case, the etch stop layer 108 may be formed of a nitride layer, for example, silicon nitride layer (Si ₃ N ₄ ), but is not limited thereto. The etch stop layer 108 may have sufficient insulating properties to secure an etching selectivity with a subsequent interlayer insulating layer. Any material that can be used can be used. For example, the etch stop layer 108 is formed at a temperature of 600 to 800 ° C. using DCS (DiChloroSilane (SiH ₂ Cl ₂ )) and NH ₃ gas.

Subsequently, an interlayer insulating film 109 (hereinafter referred to as a first interlayer insulating film) is formed to fill the gap between the gate structures 105. In this case, the first interlayer insulating layer 109 may be formed of an oxide-based material such as a BPSG (BoroPhosphoSilicate Glass) film, a PSG (PhosphoSilicate Glass) film, a USG (Un-doped Silicate Glass) film, a TEOS (Tetra Ethyle Ortho Silicate) film, and SOG. (Spin On Glass) film, HDP (High Density Plasma) film, CDO (Carbon Doped Oxide) film. Preferably, the film is formed of an HDP film having excellent embedding characteristics.

Subsequently, a planarization process may be performed on the first interlayer insulating layer 109 to planarize the upper surface. At this time, the planarization process is performed by a chemical mechanical polishing (CMP) process.

Next, an interlayer insulating film 110 (hereinafter referred to as a second interlayer insulating film) is formed on the first interlayer insulating film 109. In this case, the second interlayer insulating layer 110 may be formed of any one selected from materials used as the first interlayer insulating layer 109. Preferably, it is formed of a TEOS film.

Meanwhile, although the interlayer insulating film is separated into the first and second interlayer insulating films 109 and 110 and formed in a stacked structure, the interlayer insulating film may be formed in a single layer structure using the same material.

Subsequently, as illustrated in FIG. 1B, the first and second interlayer insulating layers 109A and 110A are exposed to expose the etch stop layer 108 at the portion corresponding to the junction region 107 between the drain select line DSL. Etching is sequentially performed to form a contact hole 111 (hereinafter referred to as a first contact hole). In this case, the first contact hole 11 may be formed in a circular or bar type.

Subsequently, as illustrated in FIG. 1C, a short circuit prevention layer 112 is formed on the inner surface (including side walls and bottom surfaces) of the first contact hole 111 (see FIG. 1B). In this case, the short-circuit prevention layer 112 is formed of the same material as the etch stop layer 108, preferably, a nitride-based material such as silicon nitride (Si ₃ N ₄ ) to a thickness of 50 to 200 μm.

Subsequently, as illustrated in FIG. 1D, the short-circuit prevention layer 112A and the etch stop layer 108A are etched to expose the junction region 107 between the drain select line DSL to form the second contact hole 113. do. In this case, the etching process may be performed by a dry etching process using an plasma etching apparatus, for example, an etch back process. For example, the etching process uses a CHF ₃ and O ₂ mixed gas or a CH ₂ F ₂ gas having a high etching selectivity between the oxide film and the silicon substrate.

Meanwhile, the second contact hole 113 may be formed by extending the junction region 107 to a predetermined depth. That is, the etching process is performed so that the junction region 107 is etched by a predetermined thickness by performing an excessive etching process, thereby allowing the bottom of the second contact hole 113 to exist in the junction region 107. For example, the junction region 107 may be excessively etched at about 400 to 500 ms.

Subsequently, as shown in FIG. 1E, the contact plug 114 is formed to fill the second contact hole 113 (see FIG. 1D). In this case, the contact plug 114 is formed of any one selected from a polycrystalline silicon film or a metal film. For example, the metal film is formed of tungsten (W), aluminum (Al), and copper (Cu).

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In particular, although the embodiment of the present invention has been described with respect to the method for forming a contact plug of a NAND flash memory device, this is for convenience of description and may be applied to all semiconductor devices including a contact plug. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1A to 1E are cross-sectional views illustrating a method for forming a contact plug of a semiconductor device according to an exemplary embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100 semiconductor substrate 101 gate insulating film (tunnel insulating film)

102 floating gate 103 dielectric film

104: control gate 105: gate structure

106: spacer 107: junction area

108: etch stop film 109, 109A: first interlayer insulating film

110, 110A: Second interlayer insulating film 111: First contact hole

112, 112A: short-circuit prevention film 113: second contact hole

114: contact plug

Claims (7)

Forming a gate structure on the substrate; Forming a junction region in the substrate exposed to both sides of the gate structure; Forming an etch stop layer along an upper surface of the structure including the junction region; Forming an interlayer insulating layer on the etch stop layer; Etching the interlayer insulating layer to form a first contact hole exposing the etch stop layer of a portion corresponding to the junction region; Forming a short circuit prevention film on an inner surface of the first contact hole; Etching the short circuit prevention layer and the etch stop layer to form a second contact hole exposing the junction region; And Forming a contact plug in which the second contact hole is embedded Contact plug forming method of a semiconductor device comprising a. The method of claim 1, Forming the second contact hole, Forming a contact plug of the semiconductor device; The method of claim 1, The method of claim 1, wherein the short circuit prevention layer is formed of the same material as the etch stop layer. The method of claim 1, And the short circuit prevention film is formed of a nitride film. The method of claim 1, The etching stop layer is a contact plug forming method of a semiconductor device formed of a nitride film. The method of claim 1, The method of claim 1, wherein the first contact hole is formed in a circular or bar type. The method of claim 1, The short-circuit prevention layer is a contact plug forming method of a semiconductor device to form a thickness of 50 ~ 200 ~.

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