KR20090069502A - Method for forming cu metal line of semiconductor device - Google Patents

Method for forming cu metal line of semiconductor device Download PDF

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KR20090069502A
KR20090069502A KR1020070137189A KR20070137189A KR20090069502A KR 20090069502 A KR20090069502 A KR 20090069502A KR 1020070137189 A KR1020070137189 A KR 1020070137189A KR 20070137189 A KR20070137189 A KR 20070137189A KR 20090069502 A KR20090069502 A KR 20090069502A
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film
forming
nitride film
hole
semiconductor device
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KR1020070137189A
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Korean (ko)
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김상권
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주식회사 동부하이텍
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Publication of KR20090069502A publication Critical patent/KR20090069502A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

A method for forming a Cu metal line of a semiconductor device is provided to shorten the process time without performing an ashing and cleaning process in a hole etching process and a metal wiring etching process. The first photoresist and first nitride film are formed on a semiconductor substrate(110). A hole(150) is formed in the first nitride film. The predetermined gas is injected through a hole to form a gas layer(160). The second photosensitive film and the second nitride film are formed on the first nitride film. The second nitride film and gas layer are selectively removed to form the contact hole. The copper foil is evaporated on the semiconductor substrate. The planarization process is performed on the copper thin film to form the copper wiring in the contact hole.

Description

반도체 소자의 구리배선 형성방법{METHOD FOR FORMING CU METAL LINE OF SEMICONDUCTOR DEVICE}TECHNICAL FOR FORMING CU METAL LINE OF SEMICONDUCTOR DEVICE

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 질소가스 복층 절연막을 이용한 반도체 소자의 구리배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming copper wiring in a semiconductor device using a nitrogen gas multilayer insulating film.

일반적으로, 반도체 소자의 금속배선으로 널리 사용하는 금속으로 알루미늄(Al), 알루미늄 합금 및 텅스텐(W) 등이 있다. Generally, metals widely used as metal wirings of semiconductor devices include aluminum (Al), aluminum alloys, and tungsten (W).

그러나, 반도체 소자가 점점 고집적화됨에 따라 텅스텐과 알루미늄 합금은 비저항이 크고, 일렉트로 마이그레이션(EM: electro migration)이나 스트레스 마이그레이션(SM: stress migration)으로 인해 신뢰성이 저하되기 때문에 비저항이 작으며 소자의 신뢰성이 우수한 구리가 강력한 금속배선 재료로 등장하였다.However, as semiconductor devices become increasingly integrated, tungsten and aluminum alloys have high resistivity, and the resistivity decreases due to electromigration (EM) or stress migration (SM). Good copper has emerged as a powerful metallization material.

여기서, EM은 금속배선 내의 전류밀도가 증가하기 때문에 생기는 불량이다. 배선폭의 미세화에 의해서 소자의 고속동작 때문에 배선 내의 전류밀도는 높아진다.Here, EM is a defect which arises because the current density in metal wiring increases. As the wiring width becomes smaller, the current density in the wiring increases due to the high speed operation of the device.

또한, SM은 배선에 잡아당기는 기계적 응력이 가해져 생기는 크리프 파괴모드이다. 이 응력은 배선을 보호하기 위해 절연막과 금속배선과의 열팽창계수의 차 가 생성원인이 되고 있고, 배선폭의 미세화에 따라 크게 되는 경향이 있다.In addition, SM is a creep fracture mode generated by applying mechanical stress applied to a wiring. This stress causes a difference in the coefficient of thermal expansion between the insulating film and the metal wiring to protect the wiring, and tends to increase as the wiring width becomes smaller.

이하, 첨부된 도면을 참조하여 종래의 반도체 소자의 구리배선 형성방법을 설명하면 다음과 같다.Hereinafter, a method of forming a copper wiring of a conventional semiconductor device will be described with reference to the accompanying drawings.

도 1a 내지 도 1d는 종래의 반도체 소자의 구리배선 형성방법을 나타낸 공정단면도이다.1A to 1D are cross-sectional views illustrating a method of forming a copper wiring in a conventional semiconductor device.

먼저, 도 1a에 도시된 바와 같이, 반도체 기판(11)상에 금속막을 증착한 후 선택적으로 제거하여 하부 금속배선(12)을 형성한다.First, as shown in FIG. 1A, a metal film is deposited on the semiconductor substrate 11 and then selectively removed to form a lower metal wiring 12.

그리고, 하부 금속배선(12)을 포함한 반도체 기판(11)의 전면에 층간 절연막(13)을 형성하고, 하부 금속배선(12)의 표면이 소정부분 노출되도록 듀얼 다마신(dual damascene) 공정에 의해 층간 절연막(13)을 선택적으로 제거하여 콘택홀(14)을 형성한다.In addition, an interlayer insulating layer 13 is formed on the entire surface of the semiconductor substrate 11 including the lower metal wiring 12, and a dual damascene process is performed to expose a predetermined portion of the surface of the lower metal wiring 12. The interlayer insulating layer 13 is selectively removed to form the contact hole 14.

여기서, 듀얼 다마신 공정에 의해 형성되는 콘택홀(14)은 포토 및 식각공정을 이용하여 비아홀과 트랜치를 각각 형성한다.Here, the contact holes 14 formed by the dual damascene process may form via holes and trenches, respectively, by using photo and etching processes.

한편, 층간 절연막(13)은 실리콘 산화막, FSG(SiOF: silicon oxy fluoride), 저유전율(Low-k) 절연막 등을 사용하고, 층간 절연막(13)과 반도체 기판(11) 사이에 질화막 등을 이용한 캡핑층을 형성할 수도 있다.Meanwhile, the interlayer insulating film 13 uses a silicon oxide film, a silicon oxy fluoride (SiOF), a low-k dielectric film, or the like, and a nitride film is used between the interlayer insulating film 13 and the semiconductor substrate 11. The capping layer may be formed.

이후, 도 1b에 도시된 바와 같이, 콘택홀(14)을 포함한 반도체 기판(11)의 전면에 베리어 금속(barrier metal)막(15)을 증착하고, 베리어 금속막(15) 상에 구리박막(16a)을 증착한다.Thereafter, as shown in FIG. 1B, a barrier metal film 15 is deposited on the entire surface of the semiconductor substrate 11 including the contact hole 14, and the copper thin film 15 is formed on the barrier metal film 15. 16a) is deposited.

다음으로, 도 1c에 도시된 바와 같이, 층간 절연막(13)의 상부표면에 화학적 기계 연마법(CMP: Chemical Mechanical Polishing) 공정을 실시하여 콘택홀(14)의 내부에 구리배선(16)을 형성한다.Next, as shown in FIG. 1C, a chemical mechanical polishing (CMP) process is performed on the upper surface of the interlayer insulating layer 13 to form a copper wiring 16 in the contact hole 14. do.

이상에서 도시된 종래의 반도체 소자의 구리배선 형성방법은 각 금속배선의 사이에서 상술한 바와 같이 저유전율의 물질을 층간절연막으로 사용하고 있다. 하지만, 이러한 형성방법은 향후 반도체 소자에서 더 낮은 유전율이 요구될 경우, 그 물질을 새로 만들어야 하며 그 후속공정에서도 층간절연막의 처리 공정이 어려운 문제점이 있다.In the above-described conventional method for forming copper wirings of semiconductor devices, a material having a low dielectric constant is used as the interlayer insulating film between the metal wirings as described above. However, such a formation method requires a new material if a lower dielectric constant is required in the semiconductor device in the future, and there is a problem in that the interlayer insulating film is difficult to process even in the subsequent process.

따라서, 상기와 같은 문제점을 해결하기 위하여, 본 발명은 질소가스 복층 절연막을 이용한 반도체 소자의 구리배선 형성방법을 제공하는 데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a copper wiring of a semiconductor device using a nitrogen gas multilayer insulating film.

본 발명에 따른 반도체 소자의 구리배선 형성방법은 일정한 폭을 갖는 하부 금속배선들 사이에 형성된 제 1 층간절연막을 포함한 반도체 기판의 전면에 제 1 감광막과 제 1 질화막을 형성하는 단계와; 상기 제 1 질화막에 서로 일정한 간격을 가지는 홀을 형성하는 단계와; 상기 홀을 통해 소정의 가스를 주입하여 소정의 가스층을 형성하는 단계와; 상기 제 1 질화막 상에 제 2 감광막과 제 2 질화막을 형성하는 단계와; 상기 제 2 질화막과 가스층을 선택적으로 제거하여 콘택홀을 형성하는 단계와; 상기 콘택홀을 포함한 상기 반도체 기판 전면에 구리박막을 증착하는 단계와; 상기 구리 박막의 전면에 평탄화 공정을 수행하여 상기 콘택홀 내부에 구리배선을 형성하는 단계를 포함하는 것을 특징으로 한다.A method of forming a copper wiring of a semiconductor device according to the present invention includes the steps of: forming a first photosensitive film and a first nitride film on an entire surface of a semiconductor substrate including a first interlayer insulating film formed between lower metal wires having a predetermined width; Forming holes in the first nitride film at regular intervals from each other; Injecting a predetermined gas through the hole to form a predetermined gas layer; Forming a second photoresist film and a second nitride film on the first nitride film; Selectively removing the second nitride film and the gas layer to form a contact hole; Depositing a copper thin film on the entire surface of the semiconductor substrate including the contact hole; And forming a copper wiring inside the contact hole by performing a planarization process on the entire surface of the copper thin film.

이상에서 설명한 바와 같이, 본 발명에 따른 반도체 소자의 구리배선 형성방법은 홀 식각 공정과 금속 배선 자리 식각 공정에서 질화막을 열어주는 시간만 필요하게 됨으로써 나머지 부분의 식각은 간단한 사진 처리 공정으로 대신할 수 있다. 또한, 금속 배선 자리 형성 공정을 진행 시 에싱과 세정 처리가 따로 필요없어지므로 공정시간이 단축되고 각 장치와 재료의 가격을 절약할 수 있다. As described above, the copper wiring forming method of the semiconductor device according to the present invention requires only the time for opening the nitride film in the hole etching process and the metal wiring spot etching process, so that the etching of the remaining portions can be replaced by a simple photo processing process. have. In addition, since the ashing and cleaning treatment are not required separately during the metal wiring seat forming process, the processing time can be shortened and the cost of each device and material can be saved.

이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체 소자의 구리배선 형성방법을 설명하면 다음과 같다.Hereinafter, a copper wiring forming method of a semiconductor device according to the present invention will be described with reference to the accompanying drawings.

도 2a 내지 도 2f는 본 발명에 따른 반도체 소자의 구리배선 형성방법을 나타낸 공정단면도이다.2A to 2F are cross-sectional views illustrating a method of forming copper wirings of a semiconductor device according to the present invention.

먼저, 도 2a에 도시된 바와 같이, 반도체 기판(110) 상에 금속막을 증착한 후 선택적으로 제거하여 하부 금속배선(120)을 형성한다. 그리고, 하부 금속배선(120)들 사이에 Oxide를 증착하여 제 1 층간절연막(115)을 형성한다. 이후, 하부 금속배선(120)을 포함한 반도체 기판(110)의 전면에 유기물질을 증착하여 제 1 감광막(130)을 형성하고, 제 1 감광막(130) 상에 하부 금속배선(120)과 후속공정에 의해 형성되는 홀과의 경계면 역할을 하는 제 1 식각 정지막(140)을 형성한다. 여기서, 제 1 식각 정지막(140)은 PECVD(Plasma Enhanced CVD) 장비를 이용하여 질화막(SiN)으로 형성하는 것이 바람직하다.First, as shown in FIG. 2A, a metal film is deposited on the semiconductor substrate 110 and then selectively removed to form a lower metal wiring 120. Oxide is deposited between the lower metal wires 120 to form a first interlayer insulating film 115. Thereafter, an organic material is deposited on the entire surface of the semiconductor substrate 110 including the lower metal interconnection 120 to form a first photoresist layer 130, and the lower metal interconnection 120 and a subsequent process on the first photoresist layer 130. A first etch stop layer 140 is formed to serve as an interface with the hole formed by. Here, the first etch stop layer 140 is preferably formed of a nitride film (SiN) using a plasma enhanced CVD (PECVD) equipment.

이어서, 도 2b에 도시된 바와 같이, 제 1 식각 정지막(140)에 서로 일정한 간격을 가지는 홀(150)을 형성한다. 여기서, 홀(150)은 하부 금속배선(120)과 오버랩되도록 형성하는 것이 바람직하다. 그리고, 홀(150)이 형성된 후, H2SO4/H2O2=4~6:1 , 120~130도 , 30~60분 화학용액으로 처리하여 내부의 제 1 감광막(130)을 제거한다. 그리고, 제 1 식각 정지막(140)에 형성된 홀(150)들을 통해 소정의 가스를 주입하여 소정의 가스층(160)을 형성한다. 여기서, 소정의 가스로 질소가스를 주입하여 질소가스층을 형성하는 것이 바람직하다. Subsequently, as shown in FIG. 2B, holes 150 having a predetermined distance from each other are formed in the first etch stop layer 140. Here, the hole 150 may be formed to overlap the lower metal wire 120. Then, after the hole 150 is formed, the first photosensitive layer 130 is removed by treatment with H 2 SO 4 / H 2 O 2 = 4 to 6: 1, 120 to 130 degrees, and a 30 to 60 minute chemical solution. In addition, a predetermined gas is injected through the holes 150 formed in the first etch stop layer 140 to form a predetermined gas layer 160. Here, it is preferable to form a nitrogen gas layer by injecting nitrogen gas into a predetermined gas.

그리고나서, 도 2c에 도시된 바와 같이, 홀(150)들이 형성된 제 1 식각 정지막(140) 상에 제 2 감광막(170)을 형성하고, 제 2 감광막(170) 상에 제 2 식각 정지막(180)을 형성한다. 그리고, 제 2 식각정지막(180) 상에 제 3 감광막(190)을 형성하고 노광 및 현상 공정을 통해 금속 배선 자리를 노출시킨다. Then, as shown in FIG. 2C, the second photoresist layer 170 is formed on the first etch stop layer 140 on which the holes 150 are formed, and the second etch stop layer is formed on the second photoresist layer 170. Form 180. In addition, the third photoresist layer 190 is formed on the second etch stop layer 180, and the metal wiring sites are exposed through the exposure and development processes.

다음으로, 도 2d에 도시된 바와 같이, 제 3 감광막(190)을 마스크로 이용한 듀얼 다마신 공정에 의해 제 1, 2 식각 정지막(140,180), 제 2 감광막(170) 및 질소가스층(160)을 선택적으로 제거하여 콘택홀(200)을 형성한다. Next, as shown in FIG. 2D, the first and second etch stop layers 140 and 180, the second photoresist layer 170, and the nitrogen gas layer 160 are formed by a dual damascene process using the third photoresist layer 190 as a mask. Selectively removes the contact hole 200.

이후, 도 2e에 도시된 바와 같이, 제 3 감광감(190)을 제거한 후, 콘택홀(200)을 포함한 반도체 기판(110)의 전면에 베리어 금속(barrier metal)막(210)을 증착하고, 베리어 금속막(210)상에 구리박막을 증착한다. 그리고, 제 2 식각 정지막(180)의 전면에 화학적 기계 연마법 (CMP: Chemical Mechanical Polishing) 공정을 실시하여 원하지 않는 부위의 구리박막을 제거하여 구리배선(220)을 형성한다. 이때, 제 2 식각 정지막(180)은 제어층으로 작용하게 된다. Then, as shown in FIG. 2E, after removing the third photosensitive 190, a barrier metal film 210 is deposited on the entire surface of the semiconductor substrate 110 including the contact hole 200. A copper thin film is deposited on the barrier metal film 210. Then, a chemical mechanical polishing (CMP) process is performed on the entire surface of the second etch stop layer 180 to remove a copper thin film of an unwanted portion to form a copper wiring 220. In this case, the second etch stop layer 180 serves as a control layer.

이어서, 도 2f에 도시된 바와 같이, 제 2 식각 정지막(180), 제 2 감광막(170)을 제거하고 후속공정으로 제 2 층간절연막(230)을 형성함으로써 절연막과 질화막 그리고 질소가스층으로 구성되는 복층구조의 절연막층으로 형성되는 구조를 가진 반도체 소자를 완성할 수 있다. Subsequently, as shown in FIG. 2F, the second etch stop layer 180 and the second photoresist layer 170 are removed and a second interlayer dielectric layer 230 is formed in a subsequent process, thereby forming an insulating layer, a nitride layer, and a nitrogen gas layer. A semiconductor device having a structure formed of an insulating film layer having a multilayer structure can be completed.

따라서, 본원 발명에 따른 반도체 소자의 구리배선 형성방법은 구조의 유지는 질화막으로 가능하고 초저유전율을 가진 질산 가스의 절연막이 형성됨으로써 향후 반도체 소자에서의 낮은 유전율 요구를 만족시킬 수 있다. Therefore, in the method for forming a copper wiring of the semiconductor device according to the present invention, the structure can be maintained as a nitride film and an insulating film of nitrate gas having an extremely low dielectric constant can be formed to satisfy a low dielectric constant requirement in a future semiconductor device.

이상 설명한 내용을 통해 당업자라면 본 발명의 기술사상을 일탈하지 아니하는 범위에서 다양한 변경 및 수정이 가능함을 알 수 있을 것이다. 따라서 본 발명의 기술적 범위는 명세서의 상세한 설명에 기재된 내용으로 한정되는 것이 아니라 특허 청구의 범위에 의해 정하여 져야만 할 것이다.Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

도 1a 내지 도 1d는 종래의 반도체 소자의 구리배선 형성방법을 나타낸 공정단면도.1A through 1D are cross-sectional views illustrating a method of forming copper wirings in a conventional semiconductor device.

도 2a 내지 도 2f는 본 발명에 따른 반도체 소자의 구리배선 형성방법을 나타낸 공정단면도.2A to 2F are cross-sectional views illustrating a method of forming copper wirings of a semiconductor device according to the present invention.

Claims (5)

일정한 폭을 갖는 금속배선들 사이에 형성된 제 1 층간절연막을 포함한 반도체 기판의 전면에 제 1 감광막과 제 1 질화막을 형성하는 단계와;Forming a first photosensitive film and a first nitride film on an entire surface of a semiconductor substrate including a first interlayer insulating film formed between metal wires having a predetermined width; 상기 제 1 질화막에 서로 일정한 간격을 가지는 홀을 형성하는 단계와;Forming holes in the first nitride film at regular intervals from each other; 상기 홀을 통해 소정의 가스를 주입하여 소정의 가스층을 형성하는 단계와;Injecting a predetermined gas through the hole to form a predetermined gas layer; 상기 제 1 질화막 상에 제 2 감광막과 제 2 질화막을 형성하는 단계와; Forming a second photoresist film and a second nitride film on the first nitride film; 상기 제 2 질화막과 가스층을 선택적으로 제거하여 콘택홀을 형성하는 단계와;Selectively removing the second nitride film and the gas layer to form a contact hole; 상기 콘택홀을 포함한 상기 반도체 기판 전면에 구리박막을 증착하는 단계와;Depositing a copper thin film on the entire surface of the semiconductor substrate including the contact hole; 상기 구리 박막의 전면에 평탄화 공정을 수행하여 상기 콘택홀 내부에 구리배선을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 구리배선 형성방법.Forming a copper wiring inside the contact hole by performing a planarization process on the entire surface of the copper thin film. 제 1항에 있어서, The method of claim 1, 상기 제 2 질화막과 제 2 감광막을 제거하는 단계와;Removing the second nitride film and the second photosensitive film; 상기 제 1 질화막 상에 제 2 층간절연막을 형성하는 단계를 추가로 포함하는 것을 특징으로 하는 반도체 소자의 구리배선 형성방법.And forming a second interlayer insulating film on the first nitride film. 제 1항에 있어서, The method of claim 1, 상기 소정의 가스는 질소가스인 것을 특징으로 하는 반도체 소자의 구리배선 형성방법.And the predetermined gas is nitrogen gas. 제 1항에 있어서, The method of claim 1, 상기 소정의 가스층은 질소가스층인 것을 특징으로 하는 반도체 소자의 구리배선 형성방법.And the predetermined gas layer is a nitrogen gas layer. 제 1항에 있어서, The method of claim 1, 상기 홀은 상기 금속배선과 오버랩되도록 형성하는 것을 특징으로 하는 반도체 소자의 구리배선 형성방법.And the hole is formed to overlap with the metal wiring.
KR1020070137189A 2007-12-26 2007-12-26 Method for forming cu metal line of semiconductor device KR20090069502A (en)

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