KR20090067988A - Method for fabricating semiconductor device - Google Patents

Method for fabricating semiconductor device Download PDF

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Publication number
KR20090067988A
KR20090067988A KR1020070135833A KR20070135833A KR20090067988A KR 20090067988 A KR20090067988 A KR 20090067988A KR 1020070135833 A KR1020070135833 A KR 1020070135833A KR 20070135833 A KR20070135833 A KR 20070135833A KR 20090067988 A KR20090067988 A KR 20090067988A
Authority
KR
South Korea
Prior art keywords
copper
semiconductor device
coronation
manufacturing
wiring layer
Prior art date
Application number
KR1020070135833A
Other languages
Korean (ko)
Inventor
김상철
Original Assignee
주식회사 동부하이텍
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 동부하이텍 filed Critical 주식회사 동부하이텍
Priority to KR1020070135833A priority Critical patent/KR20090067988A/en
Publication of KR20090067988A publication Critical patent/KR20090067988A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

In the embodiment, a method for manufacturing a semiconductor device is disclosed.

A method of manufacturing a semiconductor device according to the embodiment includes forming a copper wiring layer on the semiconductor substrate by chemical mechanical polishing of a metal film made of copper formed on the semiconductor substrate; Generating a copper interconnection layer and removing the copper coronation existing on the semiconductor substrate, wherein the removing the copper coronation includes forming a capping layer on the copper interconnection layer, and oxalic acid. Removing the copper coronation using a solution.

Description

Manufacturing method of semiconductor device {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

In the embodiment, a method for manufacturing a semiconductor device is disclosed.

Recently, in order to apply copper (Cu) as a metal wiring of a semiconductor device, a dual damascene process of simultaneously forming a trench and a via hole in a line shape is used.

1 is a view showing a method of forming a copper wiring according to the prior art.

Referring to FIG. 1, after the insulating layer 12 is formed on the lower structure 10 on which a predetermined process is completed, the dual layer damascene pattern 13 is formed by etching the insulating layer 12 by a dual damascene process. .

Subsequently, the copper wiring layer 14 is formed using a method such as electroplating until the dual damascene pattern 13 is filled. Subsequently, chemical mechanical polishing (CMP) is performed to separate the adjacent copper wiring layers 14.

The above process is referred to as a 'Cu CMP process', and after the Cu CMP process, a washing process is performed to remove suspended matter and slurry generated during CMP.

However, even after cleaning, copper corrosion (Cu corrosion, 15) made of copper oxide (CuO x , x is natural water) is formed on the surface of the copper wiring layer 14 due to photo corrosion or galvanic corrosion. Is formed.

Deposition of the insulation layer (IMD) immediately without removing the above copper co-rotation (15), the adhesion (Adhesion) is weakened, the probability of shorting between the copper wiring layer 14 increases.

On the other hand, there is a possibility that a defect is generated in the copper wiring layer 14 when an additional cleaning step is performed in order to remove the copper coronation 15.

Therefore, there is a need for a method capable of removing the copper coronation 15 without causing a defect in the copper wiring layer 14.

The embodiment provides a method of manufacturing a semiconductor device.

The embodiment provides a method of manufacturing a semiconductor device capable of removing copper coronation without causing defects in the copper wiring layer.

A method of manufacturing a semiconductor device according to the embodiment includes forming a copper wiring layer on the semiconductor substrate by chemical mechanical polishing of a metal film made of copper formed on the semiconductor substrate; Generating a copper interconnection layer and removing the copper coronation existing on the semiconductor substrate, wherein the removing the copper coronation includes forming a capping layer on the copper interconnection layer, and oxalic acid. Removing the copper coronation using a solution.

The embodiment can provide a method of manufacturing a semiconductor device.

The embodiment can provide a method of manufacturing a semiconductor device capable of removing copper coronation without causing defects in the copper wiring layer.

Hereinafter, a method of manufacturing a semiconductor device according to an embodiment will be described in detail with reference to the accompanying drawings.

2 is a view illustrating a capping film formed on a copper wiring layer in a method of manufacturing a semiconductor device according to an embodiment.

Referring to FIG. 2, after the insulating layer 12 is formed on the lower structure 10 on which a predetermined process is completed, the dual layer damascene pattern 13 is formed by etching the insulating layer 12 by a dual damascene process. .

Subsequently, the copper wiring layer 14 is formed using a method such as electroplating until the dual damascene pattern 13 is filled. Subsequently, chemical mechanical polishing (CMP) is performed to separate the adjacent copper wiring layers 14.

After the CMP process, a washing process is performed to remove suspended matter and slurry generated during CMP.

However, even after cleaning, copper corrosion (15) consisting of copper oxide (CuO x , x is natural water) on the surface of the copper wiring layer 14 due to photo corrosion or galvanic corrosion. This can be formed.

In the embodiment, palladium (Pd) is deposited on the surface of the copper wiring layer 14 by electroless plating in order to remove the copper coronation 15 without causing defects in the copper wiring layer 14.

Therefore, as shown in FIG. 2, Pd x Cu y (20), which is a palladium (Pd) and a copper (Cu) compound, is formed on the surface of the copper wiring layer 14.

The palladium ions are hardly deposited on the copper coronation 15 which is chemically stable as copper oxide, while well deposited on the surface of the copper wiring layer 14.

FIG. 3 is a view illustrating removal of a copper coronation in a method of manufacturing a semiconductor device according to an embodiment. FIG.

Referring to FIG. 3, the copper coronation 15 is removed using an oxalic acid solution at a concentration of 0.05-5%.

Since oxalic acid reacts only with copper oxide, the copper coronation 15 can be removed without defects of the copper wiring layer 14 capped with Pd x Cu y (20).

Thereafter, a washing process using pure water (DIW) is performed.

As described above, in the method of manufacturing the semiconductor device according to the embodiment of the present invention, after forming a capping film on the copper wiring layer 14 on which the copper corrosion 15, which is copper oxide, is formed, the copper wiring layer ( The copper coronation 15 can be removed without damaging 14).

1 is a view showing a method of forming a copper wiring according to the prior art.

2 is a view for explaining that a capping film is formed on the copper wiring layer in the method of manufacturing a semiconductor device according to the embodiment.

3 is a view for explaining the removal of the copper coronation in the method of manufacturing a semiconductor device according to the embodiment.

Claims (5)

Forming a copper wiring layer on the semiconductor substrate by chemical mechanical polishing of a metal film made of copper formed on the semiconductor substrate; A process of removing a copper coronation generated in the process of forming the copper wiring layer and present on the semiconductor substrate, The process of removing the copper coronation includes forming a capping film on the copper wiring layer, and removing the copper coronation using an oxalic acid solution. The method of claim 1, The capping film is a method of manufacturing a semiconductor device is formed by electroless plating palladium (Pd). The method of claim 1, The oxalic acid solution is a method of manufacturing a semiconductor device using an oxalic acid solution of 0.05 ~ 5% concentration. The method of claim 1, The capping film is a method of manufacturing a semiconductor device Pd x Cu y . The method of claim 1, The method of manufacturing a semiconductor device further comprises the step of washing with pure water (DIW) after the process of removing the copper corrosion.
KR1020070135833A 2007-12-21 2007-12-21 Method for fabricating semiconductor device KR20090067988A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020070135833A KR20090067988A (en) 2007-12-21 2007-12-21 Method for fabricating semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020070135833A KR20090067988A (en) 2007-12-21 2007-12-21 Method for fabricating semiconductor device

Publications (1)

Publication Number Publication Date
KR20090067988A true KR20090067988A (en) 2009-06-25

Family

ID=40995648

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020070135833A KR20090067988A (en) 2007-12-21 2007-12-21 Method for fabricating semiconductor device

Country Status (1)

Country Link
KR (1) KR20090067988A (en)

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E902 Notification of reason for refusal
E601 Decision to refuse application