KR20090065989A - Mold die and manufacturing method of semiconductor package using the same - Google Patents

Mold die and manufacturing method of semiconductor package using the same Download PDF

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Publication number
KR20090065989A
KR20090065989A KR1020070133565A KR20070133565A KR20090065989A KR 20090065989 A KR20090065989 A KR 20090065989A KR 1020070133565 A KR1020070133565 A KR 1020070133565A KR 20070133565 A KR20070133565 A KR 20070133565A KR 20090065989 A KR20090065989 A KR 20090065989A
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KR
South Korea
Prior art keywords
encapsulant
expansion
printed circuit
circuit board
cavity
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KR1020070133565A
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Korean (ko)
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KR100934104B1 (en
Inventor
김영준
부경택
Original Assignee
에스티에스반도체통신 주식회사
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Priority to KR1020070133565A priority Critical patent/KR100934104B1/en
Publication of KR20090065989A publication Critical patent/KR20090065989A/en
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Publication of KR100934104B1 publication Critical patent/KR100934104B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67121—Apparatus for making assemblies not otherwise provided for, e.g. package constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67126—Apparatus for sealing, encapsulating, glassing, decapsulating or the like

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

A semiconductor package mold and a semiconductor package manufacturing method using the same are provided to improve productivity and to reduce a manufacturing cost by eliminating a carrier alignment/attachment process and an attaching tape removal process. A plurality of semiconductor chips are attached on a printed circuit board(100). The semiconductor chips of a constant number are encapsulated in block units on the printed circuit board. A semiconductor package mold includes a plurality of cavities and an extended cavity. The semiconductor chips of the constant number are grouped by the cavities. The extended cavity is formed in an intermediate region(150) between two adjacent cavities of the cavities. The extended cavity is connected to one of the adjacent cavities.

Description

Mold for semiconductor package and method for manufacturing semiconductor package using same {Mold die and manufacturing method of semiconductor package using the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package molding die and a method for manufacturing a semiconductor package using the same, and more particularly, to a semiconductor package molding die for encapsulating a plurality of semiconductor chips into blocks and a method for manufacturing a semiconductor package using the same.

Recently, as most electronic products including various portable information communication devices such as personal computers, mobile phones, personal information terminals, etc. are miniaturized, light weighted, and highly functionalized, data processing capacity is increasing. According to such a trend, even in the case of a semiconductor package, a chip scale package that matches the size of a package to the size of a semiconductor chip is gaining much attention.

Such chip scale packages are classified into various types according to their manufacturing methods. One of several manufacturing methods is a method of performing manufacturing processes in a state in which a semiconductor chip is bonded to a thin printed circuit board. In this case, until the semiconductor package is separated into final semiconductor packages for improvement in productivity, the semiconductor package is grouped and encapsulated into blocks including several package regions and finally separated into individual semiconductor packages. In addition, when the encapsulant is used on the front surface of the printed circuit board, the warpage may be severe, so the work is performed by separating into several blocks.

However, a thin printed circuit board generally used in the manufacture of chip scale packages has a relatively thin thickness compared to the printed circuit board used in the manufacture of conventional semiconductor packages. For example, the thickness of a printed circuit board used for manufacturing a typical chip scale package is about 0.20 mm to 0.50 mm, but a thin printed circuit board has a thickness of about 0.15 mm or less. Such thin printed circuit boards have very thin thicknesses, and as a result, they flex well and present a great deal of difficulty in manufacturing semiconductor packages.

1 is a view of a printed circuit board and a carrier for manufacturing a semiconductor package according to the prior art.

Referring to FIG. 1, a semiconductor package manufacturing process is performed in a state in which a carrier 20 is coupled to a printed circuit board 1. At this time, the printed circuit board 1 has a block region 10 including a plurality of package regions 12 and an intermediate region 15 between the block regions 10. According to this method, since the printed circuit board 1 is supported by the carrier 20, the printed circuit board 1 is hardly bent even during the process of manufacturing the semiconductor package. The carrier 20 may be made of a metal material such as a material that is hardly bent, for example, a sus material. The center of the carrier 20 is designed as an empty space that can expose the back of the printed circuit board (1). In order to combine the printed circuit board 1 and the carrier 20, the printed circuit board 1 is fixed to the carrier 20 by using an adhesive tape. Therefore, additionally, an alignment step and an attachment step of the printed circuit board 1 and the carrier 20 are additionally required before the semiconductor package manufacturing process is performed. Furthermore, after the semiconductor package is completed, the carrier ( A further step is required to remove the adhesive tape in 20).

2 to 4 are top, bottom, and cross-sectional views of a printed circuit board of an encapsulant forming step for manufacturing a semiconductor package according to the prior art.

2 to 4, an encapsulant 40 is formed on the block area 10 of the upper surface of the printed circuit board 1. On the other hand, the encapsulant 40 is not formed on the bottom surface of the printed circuit board 1. Looking at the cross section, a mold block is sealed together with the encapsulant 40 while the plurality of semiconductor chips 30 are attached to one block region 10. Each semiconductor chip 30 is separated for each package region 12 in a subsequent process to form an individual semiconductor package. The encapsulant 40 is not formed in the intermediate region 15 between the block regions 10.

Therefore, when the semiconductor package manufacturing process is performed with a thin printed circuit board 1 without a separate support structure such as a carrier, there is a high possibility that the mold block is broken due to the weight of the encapsulant, and thus, subsequent processes Difficult to proceed and productivity is lowered. This also leads to process failures.

The technical problem to be solved by the present invention is to provide a semiconductor package molding die that can form an encapsulant without a separate support structure in order to solve the above problems in manufacturing a semiconductor package.

In addition, another technical problem to be solved by the present invention is to provide a semiconductor package manufacturing method using the semiconductor package molding die.

In order to achieve the above technical problem, the present invention provides a semiconductor package molding die as follows.

The semiconductor package molding die according to the present invention is a molding die that encapsulates a predetermined number of semiconductor chips into blocks on a printed circuit board to which a plurality of semiconductor chips are attached, and encapsulates the predetermined number of semiconductor chips into blocks. An expansion cavity is formed which is connected to one cavity adjacent to the space between the plurality of cavities and two adjacent cavities. Preferably, the depth of the expansion cavity is smaller than the depth of the cavity. The expansion cavity may include a first expansion cavity connected to one adjacent cavity and a second expansion cavity connected to another adjacent cavity.

The first expansion cavity and the second expansion cavity extend more than a centerline between a connected cavity and two cavities adjacent to the intermediate region such that the first and second expansion cavities are located on the centerline and on some horizontal line of the centerline. You can have parts that exist together.

The molding die includes a lower molding die in contact with a lower surface of the printed circuit board to which the plurality of semiconductor chips are attached, and the lower molding die includes an auxiliary cavity for sealing a lower surface of the printed circuit board corresponding to the intermediate region. It may include. The auxiliary cavity may encapsulate the lower surface of the printed circuit board corresponding to the expansion cavity.

In order to achieve the above another technical problem, the present invention provides a method for manufacturing a semiconductor package as follows.

A method of manufacturing a semiconductor package according to the present invention includes preparing a printed circuit board including a plurality of block regions to which a predetermined number of semiconductor chips are attached, and an intermediate region that is a space between two adjacent block regions. Attaching a semiconductor chip to the semiconductor substrate; forming an encapsulant for sealing the predetermined number of semiconductor chips in the block region; and separating the printed circuit board on which the encapsulant is formed into a semiconductor package including individual semiconductor chips. The forming of the encapsulant may include forming an expansion encapsulant formed in the intermediate region and connected to one encapsulant formed in an adjacent block region.

The formation thickness of the expansion encapsulant may have a value smaller than the formation thickness of the encapsulation material. The expansion encapsulant may include a first expansion encapsulation material connected to one adjacent encapsulation material and a second expansion encapsulation material connected to another adjacent encapsulation material.

The forming of the encapsulant may include forming an auxiliary encapsulant together on a lower surface corresponding to the intermediate region of the printed circuit board. In particular, the auxiliary encapsulant may encapsulate the lower surface of the printed circuit board corresponding to the expansion encapsulant.

The first expansion encapsulant and the second expansion encapsulant may extend from a connected encapsulant to a centerline between two encapsulants adjacent to the intermediate region.

In the separating of the semiconductor package, the expansion encapsulant may be separated from the semiconductor package so as to be used only for breaking or bending the printed circuit board.

The semiconductor package molding die and the semiconductor package manufacturing method according to the present invention can prevent the printed circuit board from being broken due to the weight of the encapsulant in the process of manufacturing the semiconductor package. In particular, since the breakage can be prevented without a separate support structure such as a carrier, a process step such as carrier alignment and attachment is unnecessary, and a step of removing the adhesive tape from the carrier after carrier separation is also unnecessary. This simplifies the process, increasing productivity and reducing manufacturing costs.

In addition, by using an additional encapsulant on both the upper and lower surfaces of the printed circuit board, the bending of the printed circuit board due to the encapsulant may also be prevented.

Hereinafter will be described in detail to enable those skilled in the art to easily understand and reproduce the present invention through the preferred embodiments. However, embodiments of the present invention illustrated below may be modified in various other forms within the scope of the same invention, and the scope of the present invention is not limited to the embodiments described below and the accompanying drawings. In the following description, when a component is described as being on top of another component, it may be directly on top of another component, and a third component may be interposed therebetween. In addition, in the drawings, the thickness or size of each component is exaggerated for convenience and clarity of description, and parts irrelevant to the description are omitted. Like numbers refer to like elements in the figures. On the other hand, the terms used are used only for the purpose of illustrating the present invention and are not used to limit the scope of the invention described in the meaning or claims.

5 is a schematic view showing a top surface of a printed circuit board at the stage of forming an encapsulant according to an embodiment of the present invention.

Referring to FIG. 5, the printed circuit board 100 includes a plurality of block regions 110 and an intermediate region 150 that is a space between the block regions. Although not shown, each block region 110 includes a plurality of package regions as shown in FIG. 1. Thus, each block region 110 seals a plurality of semiconductor chips together. An encapsulant 400 is formed on each block region 110. The encapsulant 400 may be made of, for example, an epoxy molding compound (EMC).

An expansion encapsulant 450 is formed in the intermediate region 150, which is a space between the two block regions 110. The expansion encapsulant 450 may be formed of, for example, an epoxy molding compound similarly to the encapsulant 400. The expansion encapsulant 450 is formed to be connected to one encapsulant 400 out of two encapsulants 400 adjacent to the middle region 150.

A plurality of expansion encapsulant 450 may be formed. For example, as shown in the drawing, the expansion encapsulation member 450 may include the first expansion encapsulation member 452 and the other encapsulation member 400 that are connected to one encapsulation member 400 adjacent to the intermediate region 150. It may include a second expansion encapsulant 454 connected to. Of course, a plurality of first expansion encapsulant 452 and second expansion encapsulant 454 may be formed, respectively. Each expansion encapsulation member 450 is not connected to other expansion encapsulation members 450 and is connected to only one encapsulation member 400.

The first expansion encapsulant 452 and the second expansion encapsulant 454 extend from the connected encapsulant 400 to at least half of the width of the intermediate region 150 in the direction of another adjacent encapsulant 400 that is not connected. do. That is, when considering a virtual center line between two encapsulants 400 adjacent to the intermediate region 150, the first encapsulation member 452 and the second encapsulation member 454 are connected encapsulants 400, respectively. ) Extends beyond the virtual center line. Of course, it extends shorter than the entire width of the intermediate region 150 and is not connected to other encapsulant 400. That is, both the first expansion encapsulant 452 and the second expansion encapsulant 454 are formed on the virtual center line.

Therefore, the expansion encapsulant 450 may prevent the printed circuit board 100 from being broken in the middle region due to the weight of each encapsulant 400. In particular, since the first expansion encapsulant 452 and the second expansion encapsulant 454 are formed in a staggered structure, each of the encapsulant 400 is connected to only one encapsulant 400 and not connected to the other encapsulant 400. It can also prevent warpage.

6 is a schematic view showing a bottom surface of a printed circuit board at the stage of forming an encapsulant according to an embodiment of the present invention.

Referring to FIG. 6, an auxiliary encapsulant 455 may be formed on a bottom surface of the printed circuit board 100 corresponding to the intermediate region 150. The auxiliary encapsulant 455 may be made of an epoxy molding compound, for example, like the encapsulant 400 and the expansion encapsulant 450. Since a separate encapsulant is not formed at a position corresponding to the block region 110 on the bottom surface of the printed circuit board 100 on which the auxiliary encapsulant 455 is formed, the formation position of the auxiliary encapsulant 455 is greatly limited. I do not receive it. However, preferably, the auxiliary encapsulant 455 is formed on the lower surface of the printed circuit board 100 corresponding to the position of the expansion encapsulant 450 formed on the upper surface of the printed circuit board 100.

Therefore, when the auxiliary encapsulant 455 is used together on one side, that is, the upper surface of the printed circuit board 100, the middle region 150 of the printed circuit board 100 may be held on the upper and lower surfaces thereof. This can more firmly prevent breaks in the area. The thickness of the auxiliary encapsulant 455 may be thicker or thinner than the thickness of the encapsulant 400, unlike the expansion encapsulant 450.

The auxiliary encapsulant 455 may be formed by forming an encapsulation resin injection unit (not shown) separate from the encapsulant 400 and the expansion encapsulant 450 on the upper surface, or an expansion encapsulant of the printed circuit board 100 ( 450 may be formed by forming a hole (not shown) connecting the upper surface and the lower surface at the formation position so that the sealing resin is injected.

7 is a schematic view showing a bottom surface of a printed circuit board at the stage of forming an encapsulant according to a modification of the embodiment of the present invention.

Referring to FIG. 7, unlike the example shown in FIG. 6, the auxiliary encapsulant 455 is formed to be symmetrical to the expansion encapsulant 450 based on a position corresponding to the virtual center line of the intermediate region 150.

8 is a schematic view showing a cross section of a printed circuit board at the stage of forming an encapsulant according to an embodiment of the present invention. Specifically, it is sectional drawing cut along the line VIII-VIII of FIG.

Referring to FIG. 8, a plurality of semiconductor chips 300 are attached to the block region 110, and the semiconductor chips 300 on the block region 100 are grouped and sealed with the encapsulant 400. That is, after attaching the semiconductor chip 300 to the printed circuit board 100 including the block region 110 and the intermediate region 150, the encapsulant (110) to seal the block region 110 as a unit ( 400). In this case, the semiconductor chip 300 is attached to each of the plurality of package regions 120 existing in the block region 110.

While forming the encapsulant 400, the expansion encapsulant 454 and the auxiliary encapsulant 458 are also formed. The expansion encapsulant 454 is formed in the middle region 150 of the upper surface of the printed circuit board 100, and the auxiliary encapsulant 458 is formed in the lower surface of the printed circuit board 100 corresponding to the intermediate region 150. . At this time, the thickness of the expansion encapsulant 454 and the auxiliary encapsulant 458 may be formed to have a smaller value than the formation thickness of the encapsulant 400, respectively.

The auxiliary encapsulant 458 may be formed on the bottom surface of the printed circuit board 100 corresponding to the position where the expansion encapsulant 454 is formed as shown in the figure, and as shown in FIG. It may be formed to be.

In the subsequent process, the encapsulant 400 and the printed circuit board 100 are cut to separate each package region 120 to complete a semiconductor package. In this process, the auxiliary encapsulant 454 and the expansion encapsulant 458 are separated while being cut so that they are not used in the actually completed semiconductor package.

9 is a schematic view showing an upper molding die for forming an encapsulant and an expansion encapsulant according to an embodiment of the present invention.

Referring to FIG. 9, the upper forming mold 500 has a plurality of cavities 510 and expansion cavities 520 when viewed from the direction toward the upper surface of the printed circuit board 100. The cavity 510 is a space used to form the encapsulant 400, and the expansion cavity 520 is a space used to form the encapsulant 450. The expansion encapsulant 450 is formed in an intermediate region between the two cavities 500, and is formed to be connected to one cavity 500 among two adjacent cavities 500.

A plurality of expansion cavities 520 may be formed. For example, as shown in the drawing, the expansion cavity 520 is connected to the first expansion cavity 522 and the other cavity 500 connected to one of the two adjacent cavities 500. It may include a second expansion cavity 524. Of course, a plurality of first expansion cavities 522 and second expansion cavities 524 may also be formed. Each of the expansion cavities 520 is not connected to the other expansion cavities 520 but is connected to only one cavity 500.

The first expansion cavity 522 and the second expansion cavity 524 are each at least half of the width of the intermediate region between the two cavity 500 in the direction from the connected cavity 500 to another adjacent cavity 500 that is not connected. Is extended. That is, when the virtual center line is considered in the middle region between two adjacent cavities 500, the first expansion cavity 522 and the second expansion cavity 524 respectively move the virtual center line from the connected cavity 500. It extends beyond. Of course, it extends shorter than the entire width of the intermediate region between the two cavities 500 and is not connected to the other cavities 500.

10 is a schematic view showing a cross section of an upper molding die for forming an encapsulant and an expansion encapsulant according to an embodiment of the present invention. Specifically, it is sectional drawing cut along the X-X line of FIG.

Referring to FIG. 10, the depth of the expansion cavity 524 has a smaller value than the depth of the cavity 510. As a result, the expansion encapsulant 450 is thinner than the encapsulant 400.

11 is a schematic view of a lower molding die for forming an auxiliary encapsulant according to an embodiment of the present invention.

Referring to FIG. 11, the lower forming mold 550 has an auxiliary cavity 560 when viewed from a direction toward the bottom surface of the printed circuit board 100. The auxiliary cavity 560 is a space used to form the auxiliary encapsulant 455. The position of the auxiliary cavity 560 is formed at a position corresponding to the middle region between the two cavities 500 of the upper molding die 500 as described above with respect to the position of the auxiliary encapsulant 455. For example, the auxiliary cavity 560 may be formed at a position corresponding to the expansion cavity 520, and the auxiliary cavity 560 may be formed at a position symmetrical with the expansion cavity 520.

The upper mold 100 and the lower mold 550 are bonded to the upper and lower surfaces of the printed circuit board to which the semiconductor chip 300 is attached to form an encapsulant. Although not shown, the upper molding die 500 and the lower molding die 550 may be provided with an injection unit for injecting an encapsulant, an air vent for discharging air or a jet gas, and the like.

12 is a schematic view showing a cross section of a lower molding die for forming an encapsulant and an expansion encapsulant according to an embodiment of the present invention. Specifically, it is sectional drawing cut along the XII-XII line of FIG.

1 is a view of a printed circuit board and a carrier for manufacturing a semiconductor package according to the prior art.

2 to 4 are top, bottom, and cross-sectional views of a printed circuit board of an encapsulant forming step for manufacturing a semiconductor package according to the prior art.

5 and 6 are schematic views showing the top and bottom surfaces of a printed circuit board at the stage of forming an encapsulant according to an embodiment of the present invention.

7 is a schematic view showing a bottom surface of a printed circuit board at the stage of forming an encapsulant according to a modification of the embodiment of the present invention.

8 is a schematic view showing a cross section of a printed circuit board at the stage of forming an encapsulant according to an embodiment of the present invention.

9 and 10 are a schematic view and a cross-sectional view showing an upper molding die for forming an encapsulant and an expansion encapsulant according to an embodiment of the present invention.

11 and 12 are a schematic view and a cross-sectional view of a lower molding die for forming an auxiliary encapsulant according to an embodiment of the present invention.

<Description of main parts of drawing>

100: printed circuit board, 110: block area, 120: package area, 150: middle area, 300: semiconductor chip, 400: encapsulation material, 450: expansion encapsulation material, 455: auxiliary encapsulation material, 500: upper forming mold, 510 : Cavity, 520: expansion cavity, 550: lower molding mold, 560: auxiliary cavity

Claims (13)

A molding die for encapsulating a predetermined number of semiconductor chips into blocks on a printed circuit board with a plurality of semiconductor chips, A plurality of cavities for grouping and sealing the predetermined number of semiconductor chips into blocks; And The semiconductor package molding die formed in an intermediate region, which is a space between two adjacent cavities of the plurality of cavities, and includes an expansion cavity connected to one adjacent cavity. According to claim 1, And wherein the expansion cavity includes a first expansion cavity connected with one adjacent cavity and a second expansion cavity connected with another adjacent cavity. According to claim 1, The molding die includes a lower molding die in contact with a lower surface of the printed circuit board to which the plurality of semiconductor chips are attached. And the lower forming mold includes an auxiliary cavity for sealing a lower surface of the printed circuit board corresponding to the intermediate region. The method of claim 3, wherein The auxiliary cavity is a semiconductor package molding die, characterized in that for sealing the lower surface of the printed circuit board corresponding to the expansion cavity. According to claim 1, The depth of the expansion cavity is a semiconductor package molding die, characterized in that the value smaller than the depth of the cavity The method of claim 2, And wherein the first and second expansion cavities extend further from a connected cavity to a centerline between two cavities adjacent to the intermediate region. Preparing a printed circuit board including a plurality of block regions to which a predetermined number of semiconductor chips are attached, and an intermediate region which is a space between two adjacent block regions; Attaching a semiconductor chip on the printed circuit board; Forming an encapsulant for sealing the predetermined number of semiconductor chips in the block region; And And separating the printed circuit board on which the encapsulant is formed into a semiconductor package including individual semiconductor chips. The forming of the encapsulant may include forming an expansion encapsulant formed in the intermediate region and connected to one encapsulant formed in an adjacent block region. The method of claim 7, wherein The expansion encapsulant includes a first expansion encapsulation material connected to one adjacent encapsulation material and a second expansion encapsulation material connected to another adjacent encapsulation material. The method of claim 7, wherein The formation thickness of the expansion encapsulant has a value smaller than the formation thickness of the encapsulant. The method of claim 7, wherein Forming the encapsulant, And forming an auxiliary encapsulant together on a lower surface corresponding to the intermediate region of the printed circuit board. The method of claim 10, The auxiliary encapsulant, And a bottom surface of the printed circuit board corresponding to the expansion encapsulant. The method of claim 7, wherein And the first expansion encapsulation member and the second expansion encapsulation member extend further from a connected encapsulant than a centerline between two encapsulants adjacent to the intermediate region. The method of claim 7, wherein Separating into the semiconductor package, The expansion encapsulant is separated from the semiconductor package manufacturing method.
KR1020070133565A 2007-12-18 2007-12-18 Semiconductor package molding die and semiconductor package manufacturing method using the same KR100934104B1 (en)

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Application Number Priority Date Filing Date Title
KR1020070133565A KR100934104B1 (en) 2007-12-18 2007-12-18 Semiconductor package molding die and semiconductor package manufacturing method using the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020070133565A KR100934104B1 (en) 2007-12-18 2007-12-18 Semiconductor package molding die and semiconductor package manufacturing method using the same

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KR20090065989A true KR20090065989A (en) 2009-06-23
KR100934104B1 KR100934104B1 (en) 2009-12-29

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Publication number Priority date Publication date Assignee Title
TWI235440B (en) 2004-03-31 2005-07-01 Advanced Semiconductor Eng Method for making leadless semiconductor package
US20050258552A1 (en) 2004-05-18 2005-11-24 Kim Sung J Semiconductor molding method and structure
JP2007109831A (en) * 2005-10-13 2007-04-26 Towa Corp Resin sealing molding method for electronic component

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