KR20090063533A - Data driving device and liquid crystal display device using the same - Google Patents

Abstract

A data driving device and a liquid crystal display using the same are provided, which maintain the color temperature according to gradation by individually controlling the upper gradation voltage for the upper gradation voltage for the blue and red/green. A digital processing part(130) latches the inputted red, green and blue data. The gray voltage generator(120) produces the gradation voltages for the blue of the straight polarity and negative polarity and 3 color common gradation voltages by using a plurality of standard gamma voltages and the first and the second power source. The gray voltage generator produces modulation gradation voltages for the gradation voltages for the red/green of the straight polarity and negative polarity or the red/green. The analog processing part(140) converts the red and green latch data supplied from the digital processing part into the red and green picture signal.

Description

DATA DRIVING DEVICE AND LIQUID CRYSTAL DISPLAY DEVICE USING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data driver and a liquid crystal display using the same, and more particularly, to a data driver and a liquid crystal display using the same to compensate for color temperature according to gray scale.

In general, a liquid crystal display device displays a desired image by applying an electric field to a liquid crystal material having an anisotropic dielectric constant formed between two substrates, and controlling the light transmittance by adjusting the intensity of the electric field.

Such a general liquid crystal display displays grayscales according to light transmittances of red, green, and blue dots (Dot) according to data signals of red (R), green (G), and blue (B), respectively. In this case, each of the red, green, and blue data signals uses the same gray voltage. Accordingly, although the electro-optical characteristics of each of the red, green, and blue dots are clearly different, there is a problem that the color temperature is changed according to the gray level by using the same gray voltage. That is, the color temperature is determined by the blending ratio of the luminance of each of the red, green, and blue dots constituting the pixel. However, since the data signals of the red, green, and blue colors cannot be individually controlled when the grayscale is increased or decreased, FIG. As shown in Fig. 1, the non-uniformity occurs in the upper and lower grayscale regions.

In order to solve the above problems, the present invention is to provide a data driver and a liquid crystal display using the same to compensate for the color temperature (Color Temperature) according to the gray scale (Gray Scale).

According to another aspect of the present invention, there is provided a data driving device including: a digital processor configured to latch inputted red, green, and blue data; By using the plurality of reference gamma voltages and the first and second power supplies, blue and gray color voltages for positive and negative polarities are generated, and positive and negative voltages are generated according to the first and second frame control signals. A gray voltage generator configured to generate negative red / green gray voltages or red / green modulated gray voltages; And red and green latches supplied from the digital processing unit using the positive and negative gradation voltages for red and green or the modulation gradation voltages for red and green and the three common gradation voltages of the positive and negative polarities. Blue latch data supplied from the digital processing unit by converting each data into a red and green image signal and simultaneously using the positive and negative blue gray voltages and the positive and negative three color common gray voltages. It characterized in that it comprises a analog processing unit for converting to a blue image signal.

Each of the first and second frame control signals has an inverted form and is inverted in units of frames.

Each of the positive gray gray voltages has a voltage level higher than each of the positive red / green modulation gray voltages, and each of the negative blue gray voltages has a negative red / green modulation gray voltage. It is characterized by having a lower voltage level than each.

The gray gradation voltages are i to h (where h is a natural number less than i) of the total i gradations corresponding to the number of bits of the data, and / or v (where v is a natural number less than h). To 0 th gray voltage, and the red / green gradation voltages or the red / green gradation voltages are i th to h th gradation voltages and / or v th to 0 th gradation voltages of the i th gradations. The three common gray voltages may be the 0th to h-1 gradation voltages or the v + 1 to i gradation voltages or the v + 1 to h-1 gradation voltages among the i numbers of gradations.

A liquid crystal display according to an exemplary embodiment of the present invention includes an image display unit having a plurality of pixel cells formed for each region defined by a plurality of data lines and gate lines; A gate driver for driving a gate line of the image display unit; A data driver for supplying an image signal to a data line of the image display unit; A timing controller which supplies a data signal to the data driver and controls the data driver and the gate driver; And a reference gamma voltage generator configured to generate a plurality of reference gray voltages and supply the plurality of reference gray voltages to the data driver, wherein at least one data driver included in the data driver comprises: a digital processor configured to latch red, green, and blue data input; Using the plurality of reference gamma voltages and the first and second power supplies, the positive and negative blue gray voltages and the three color common gray voltages are generated, and the positive and A gray voltage generator configured to generate negative red / green gray voltages or red / green modulated gray voltages; And red and green latches supplied from the digital processing unit using the positive and negative gradation voltages for red and green or the modulation gradation voltages for red and green and the three common gradation voltages of the positive and negative polarities. Blue latch data supplied from the digital processing unit by converting each data into a red and green image signal and simultaneously using the positive and negative blue gray voltages and the positive and negative three color common gray voltages. An analog processing unit for converting the signal into a blue image signal.

The timing controller generates the first and second frame control signals that are inverted from each other and inverted in units of frames, and supplies the first and second frame control signals to the data driving devices.

The data driving device and the liquid crystal display using the same according to the present invention separately control the upper gray voltage for blue and the upper gray voltage for red / green, and individually control the red / green gray voltage or the red / green color for each frame. By alternately generating the modulated gradation voltages, the color temperature according to the gradations can be kept constant, the luminance deterioration can be minimized, and the size of the gradation voltage generation unit can be reduced.

In addition, the present invention is configured in the digital analog converter to configure the number of decoders for converting digital data into image signals equal to the number of output channels of the data drive device to reduce the size of the data drive device to more easily respond to the larger size Can be.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings and embodiments.

2 is a block diagram schematically illustrating a data driving device according to a first embodiment of the present invention.

Referring to FIG. 2, the data driver 100 according to the first embodiment of the present invention relays red, green, and blue data signals R, G, and B and data control signals DCs supplied from the outside. Control block 110; It generates three-color common gradation voltages (PCV, NCV) and blue gradation voltages (PBV, NBV), and red / green gradation voltages (PRGV, NRGV) according to the first and second frame control signals (FCS1, FCS2). ) Or a gray voltage generator 120 generating red / green modulation gray voltages PRGMV and NRGMV; A digital processor 130 for latching the data signals R, G, and B supplied from the control block 110 according to the data control signals EN1, SSC, and SOE supplied from the control block 110; First and second polarities supplied from the control block 110 to the latch data RData supplied from the digital processor 130 using the gray voltages (PCV, NCV, PBV, NBV, PRGV or PRGMV, NRGV, or NRGMV). And an analog processor 140 that converts and outputs an image signal VData having a data polarity corresponding to the control signals POL1 and POL2.

The control block 110 restores the N-bit red, green, and blue data signals R, G, and B supplied from the outside to correspond to the data interface method, and supplies them to the digital processor 130. In addition, the control block 110 includes data including a source start pulse SSP, a source shift clock SSC, a source output signal SOE, and first and second polarity control signals POL1 and POL2 supplied from an external source. Each of the digital processor 130 and the analog processor 140 is controlled using the control signal DCS.

As shown in FIG. 3, the gray scale generator 120 includes first to third divided resistance strings 122, 124, and 126.

The first divided resistor row 122 includes first to g-th divided resistors R_1 to R_g connected in series between the driving power source VDD and the base power source VSS. The first divided resistor string 122 is divided into first and second regions 122a and 122b and first and second common regions 122c1 and 122c2 according to voltages generated by voltage division using a resistor. .

The first region 122a includes first to cth voltage divider resistors R_1 to R_c connected in series. Further, a gamma reference gamma of the first to k1 (where k1 is a natural number smaller than j / 2) of j (where j is a natural number) reference gamma voltages GMA_j in the divided node in the middle of the first region 122a. Voltages GMA_1 to GMA_k1 are supplied. For example, the first reference gamma voltage GMA_1 is supplied to the divided voltage node R_1 and R_2 that generate the i-th gray voltage PBV_i among the divided nodes of the first region 122a, and i-1 The second reference gamma voltage GMA_2 may or may not be supplied to the divided nodes R_2 and R_3 generating the gray voltage PBV_i-1. In addition, the k th reference gamma voltage GMA_k1 is supplied to the divided node R_c-1 and R_c generating the h th gray voltage PBV_h. Here, i is N squared of 2 when the number of bits of the data signal is N. For example, i may be 255 when the number of bits of the data signal is eight. G is a natural number and c is a natural number less than g. In addition, h is a natural number smaller than i, and may be, for example, 223 when the number of bits of the data signal is eight. In addition, k1 may be set to a natural number smaller than j / 2 according to at least one of the electro-optical characteristics, gamma characteristics, and color temperature characteristics of the liquid crystal. For example, k1 may be 2 or 3 when j is 18.

The first region 122a includes the i-th to h-th gray voltages PBV_i to PBV_h generated by voltage division at each divided node formed between the first to c-th voltage divider R_1 to R_c. The upper blue gray-level voltage PBV_x having x pieces is supplied to the analog processor 140. Here, when the number of bits of the data signal is 8, the first region 122a generates 33 positive blue upper grayscale voltages PBV_x including the positive 255th to 223th grayscale voltages PBV_255 to PBV_223. .

The first common area 122c1 includes the c to d + 1 voltage divider resistors R_c to R_d + 1. The k1 + 1 to j / 2 reference gamma voltages GMA_k1 + 1 to GMA_j / 2 of the j reference gamma voltages GMA_j are supplied to the divided node in the middle of the first common region 122c1. Each of the k1 + 1 to j / 2 reference gamma voltages GMA_k1 + 1 to GMA_j / 2 has a first common region (e.g. 122c1) can be supplied to any partial pressure node. For example, the j / 2 reference gamma voltage GMA_j / 2 is supplied to the divided node which generates the positive tricolor common zero grayscale voltage PCV_0 among the divided nodes of the first common region 122c1. The j / 2-1 reference gamma voltage GMA_j / 2-1 may or may not be supplied to the divided node which generates the positive tricolor common first gradation voltage PCV_1 among the divided nodes of the first common region 122c1. Can be. Each of the k1 + 1 to j / 2-2 reference gamma voltages GMA_k1 + 1 to GMA_j / 2-2 has a positive polarity among the divided nodes of the first common region 122c1 so as to have an equal interval or a boiling interval. It is supplied to an arbitrary divided node which generates each of the three color common third to h-1 gradation voltages PCV_3 to PCV_h-1.

The first common region 122c1 includes the positive h-1 gradation voltage PCV_h generated by voltage distribution at each divided node formed between the c to d + 1 divided resistors R_c to R_d + 1. The positive three-color common gradation voltage PCV_y including y up to the zeroth gradation voltage PCV_0 from -1) is supplied to the analog processor 140. Here, when the number of bits of the data signal is 8, the first common area 122c1 generates 223 positive three-color common gradation voltages PCV_y including the zeroth to 222th gradation voltages PCV_0 to PCV_222 of the positive polarity. do.

The second common area 122c2 includes dd (where dd is a natural number greater than d and less than g) to ff (where ff is a natural number greater than dd and less than g) partial pressure resistances R_dd to R_ff. do. Further, j / 2 + 1 to k2-1 (where k2 is larger than j / 2 and smaller than j) among the j reference gamma voltages GMA_j in the divided voltage node in the middle of the second common area 122c2. ) The reference gamma voltages GMA_j / 2 + 1 to GMA_k2-1 are supplied. Each of the j / 2 + 1 to k2-1 reference gamma voltages GMA_j / 2 + 1 to GMA_k2-1 may have equal intervals or boiling intervals depending on the electro-optical, color temperature, and gamma characteristics of the liquid crystal. 2 may be supplied to any partial pressure node of the common area 122c2. For example, the j / 2 + 1 reference gamma voltage GMA_j / 2 + 1 is a divided node that generates a negative tricolor common zero gray level voltage NCV_0 among the divided nodes of the second common region 122c2. And a j / 2 + 2 reference gamma voltage GMA_j / 2 + 2 is a divided node that generates a negative tricolor common first gradation voltage NCV_1 among the divided nodes of the second common region 122c2. May or may not be supplied. Each of the j / 2 + 3 to k2-1 reference gamma voltages GMA_j / 2 + 3 to GMA_k2-1 has a negative polarity among the divided nodes of the second common region 122c1 so as to have an equal interval or a boiling interval. Are supplied to any of the divided voltage nodes which generate each of the three color common third to h-1 gradation voltages NCV_3 to NCV_h-1.

The second common region 122c2 is formed from the negative zero grayscale voltage NCP_0 generated by voltage division at each divided node formed between the dd to ff divided voltage resistors R_dd to R_ff. Each of the negative three-color common gradation voltages NCV_y having y pieces including up to the h-1 gradation voltages NCV_h-1 is supplied to the analog processor 140. Here, when the number of bits of the data signal is 8, the second common area 122c2 includes 223 negative tri-color common gradation voltages NCV_y including the 0th to 222nd gradation voltages NCV_0 to NCV_222 of the negative polarity. Create

Meanwhile, at least one dummy resistor (not shown) may be connected between the first common region 122c1 and the second common region 122c2.

The second region 122b includes the ff to gth voltage divider resistors R_ff to R_g connected in series. The kth to jth reference gamma voltages GMA_k2 to GMA_j of the j reference gamma voltages GMA_j are supplied to the divided nodes in the middle of the second region 122b. For example, a k2 reference gamma voltage GMA_k2 is supplied to the divided voltage node R_ff and R_ff + 1 that generate the h-th gray voltage NBV_h among the divided voltage nodes of the second region 122b. The j-1 reference gamma voltage GMA_j-1 may or may not be supplied to the divided node R_g-2 and R_g-1 generating the -1 gray voltage NBV_i-1. In addition, the j-th reference gamma voltage GMA_j is supplied to the divided node R_g-1 and R_g generating the i-th gray voltage NBV_i. Here, k2 may be set to a natural number larger than j / 2 and smaller than j, for example, j-1 or j-2.

The second region 122b includes the h-th gray voltage NBV_h to the i-th gray voltage NBV_i generated by voltage division at each divided node formed between the ff to gth divided resistors R_ff to R_g. The blue upper gray-level voltage NBV_x having x pieces including the power supply to the analog processor 140 is supplied. In this case, when the number of bits of the data signal is 8, the second region 122b receives 33 negative blue upper gray level voltages NBV_x including the negative 223th to 255th grayscale voltages NBV_223 to NBV_255. Create Here, the negative blue upper grayscale voltage NBV_x having x pieces has a voltage level symmetrical with the positive blue upper grayscale voltage PBV_x having x pieces based on a common voltage (not shown).

As described above, the first divided resistance row 122 generates x gray positive voltages PBV_x and NBV_x having positive and negative polarities through the first and second regions 122a and 122b. Through the first and second common areas 122c1 and 122c2, y-color positive and negative three-color common gradation voltages PCV_y and NCV_y are generated and supplied to the analog processor 140.

The second divided resistor string 124 is connected in series between the driving power source VDD and the base power source VSS, and has a positive red / green high gray level voltage according to the first and second frame control signals FCS1 and FCS2. PRGV_x) or the first to cth voltage divider resistors Rr_1 to Rr_c for positive red / green, which generate positive red / green higher modulation gradation voltages PRGMV_x.

Each of the first to c divided voltage resistors Rr_1 to Rr_c for the positive red / green color is each of the first to c divided voltage resistors R_1 to R_c configured in the first region 122a of the first divided voltage resistance row 122. It has the same resistance value as

The first and second frame control signals FCS1 and FCS2 and at least one positive external voltage PEVi-1 are supplied from the outside to the divided node in the middle of the second divided resistor row 124. For example, the first frame is controlled by the first resistor R1 at the first divided node Rr_1 and Rr_2 that generate the i-th gray voltage PRGV_i among the divided voltage nodes of the second divided resistor string 124. The signal FCS1 is supplied, and the second frame control signal FCS2 is supplied to the divided node Rr_c-1 and Rr_c generating the h th gray voltage PRGV_h through the second resistor R2. In addition, the divided external voltage PEVi for the i-1th gray level is divided into the divided voltage nodes Rr_2 and Rr_3 that generate the i-1th gray voltage PRGV_i-1 among the divided voltage nodes of the second divided resistor row 124. -1) may or may not be supplied.

As shown in FIG. 4, the first and second frame control signals FCS1 and FCS2 are inverted from each other in units of frames so as to correspond to frame frequencies from the outside. That is, the first frame control signal FCS1 has a first logic state (high level) during an odd-numbered frame (section A) among the frames corresponding to the frame frequency, and a second logic state (high-level) during an even-numbered frame (section B). Low level). The second frame control signal FCS2 has a second logic state during odd-numbered frames among the frames corresponding to the frame frequency, and has a first logic state during even-numbered frames.

The resistance value of the first resistor R1 of the second divided resistor row 124 is generated at the first divided node of the second divided resistor row 124 according to the first frame control signal FCS1 of the first logic state. The positive red / green i-th gray voltage PRGV_i has the same voltage level as that of the positive blue-th i-th gray voltage PBV_i, and according to the first frame control signal FCS1 in the second logic state. The positive red / green i-th gray voltage PRGV_i generated at the first divided node of the second divided resistor row 124 is set to have a voltage level lower than that of the positive blue i-th gray voltage PBV_i.

The resistance value of the second resistor R2 of the second divided resistor row 124 may be set at the h divided voltage node of the second divided resistor row 124 according to the second frame control signal FCS2 of the second logic state. The generated red / green (th) gradation voltage PRGV_h has the same voltage level as that of the positive blue (h) gradation voltage PBV_h, and is applied to the second frame control signal FCS2 in the first logic state. Accordingly, the positive red / green (h) gray voltage PRGV_h generated at the h divided voltage node of the second divided resistor string 124 has a voltage level lower than that of the positive blue (h) gray voltage (PBV_h). Is set.

The second voltage divider resistor 124 includes the first to the second red / green polarities according to the first frame control signal FCS1 in the first logic state and the second frame control signal FCS2 in the second logic state. c) i-th to h-th gray voltages having the same voltage level as the i-th to h-th gray voltages PBV_i to PBV_h for the positive blue color by voltage division in each of the divided nodes formed between the divided voltage resistors Rr_1 to Rr_c. A positive red / green high gray level voltage PRGV_x having x pieces including PRGV_i to PRGV_h) is generated and supplied to the analog processor 140.

On the other hand, the second voltage divider resistor 124 has the positive red / green first through the first frame control signal FCS1 in the second logic state and the second frame control signal FCS2 in the first logic state. I-th to h-th modulations having a voltage level lower than each of the i-th to h-th gray voltages PBV_i to PBV_h for the positive blue color by voltage division at each voltage division node formed between the c-th voltage divider Rr_1 to Rr_c. The high-order red / green high-modulation gradation voltage PRGMV_x having x pieces including the gradation voltage is generated and supplied to the analog processor 140.

The third divided resistance string 126 is connected in series between the negative h-th external voltage NEVh and the base power supply VSS, and is connected to the negative voltage according to the first and second frame control signals FCS1 and FCS2. Including the first to c divided voltage resistors Rr_ff to Rr_g for the red / green for generating the red / green high gray voltage (NRGV_x) or the negative red / green high modulation gray voltage (NRGMV_x). It is composed. In this case, the negative h-th external voltage NEVh may have the same level as the k2th reference gamma voltage GMA_k2.

Each of the first to c-th voltage divider resistors Rr_ff to Rr_g for the negative red / green color is the ff to g-th voltage divider resistors R_ff to R_g configured in the second region 122b of the first voltage divider resistor string 122. It has the same resistance value as each.

The first and second frame control signals FCS1 and FCS2 and at least one negative external voltage NEVi-1 are supplied to the divided node in the middle of the third divided resistor row 126. For example, the h-th divided node (between Rr_ff and Rr_ff + 1) that generates the h-th gray voltage NRGV_h among the divided voltage nodes of the third divided resistor row 126 is connected to the second through the third resistor R3. The frame control signal FCS2 is supplied, and the first frame control signal FCS1 is supplied to the divided node Rr_g-1 and Rr_g generating the i th gray voltage NRGV_i through the fourth resistor R4. . In addition, among the divided nodes of the third divided resistor row 126, the divided voltage node Rr_g-2 and Rr_g-1, which generates the i-1th gray voltage NRGV_i-1, has a negative polarity for the i-1th gray level. The external voltage NEVi-1 may or may not be supplied.

The resistance value of the third resistor R3 of the third divided resistor row 126 is generated at the h divided voltage node of the third divided resistor row 126 according to the second frame control signal FCS2 of the second logic state. The negative red / green (th) gray level voltage (NRGV_h) has the same voltage level as that of the negative blue (h) gray level voltage (NBV_h), and is applied to the second frame control signal (FCS2) in the first logic state. Accordingly, the negative red / green (th) gray level voltage (NRGV_h) generated at the h-th voltage divider node of the third divided resistor row 126 has a voltage level higher than that of the negative blue (h) gray level voltage (NBV_h). It is set to.

The resistance value of the fourth resistor R4 of the third divided resistor row 126 may be set at the i-th divided node of the third divided resistor row 126 according to the first frame control signal FCS1 of the first logic state. The generated negative red / green i-th gray voltage NRGV_i has the same voltage level as that of the negative blue i-th gray voltage NBV_i, and the first frame control signal FCS1 in the second logic state. The voltage level of the negative red / green i-th gray voltage NRGV_i generated at the i-th voltage divider node of the third divided resistor row 126 is higher than that of the negative blue i-th gray voltage NBV_i. It is set to have.

The third voltage divider resistor 126 may include the first to third red / green first to third frame control signals FCS1 in the first logic state and the second frame control signal FCS2 in the second logic state. H-th to i-th grays having the same voltage level as the h-th to i-th gray-level voltages NBV_h to NBV_i for the negative polarity by voltage distribution in each of the divided nodes formed between the c-th voltage divider Rr_ff to Rr_g. A negative red / green high gray voltage NRGV_x having x pieces including the voltages NRGV_h to NRGV_i is generated and supplied to the analog processor 140.

On the other hand, the third voltage divider resistor string 126 has a negative red / green first polarity according to the first frame control signal FCS1 in the second logic state and the second frame control signal FCS2 in the first logic state. H-th to h-th voltages having a higher voltage level than each of the h-th to i-th gray-level voltages NBV_h to NBV_i for negative polarity due to voltage distribution in each voltage division node formed between the c-th voltage divider Rr_ff to Rr_g. A negative red / green high modulation gray voltage NRGMV_x having x pieces including the i modulation gray voltage is generated and supplied to the analog processor 140.

Meanwhile, the first voltage dividing resistor Rr_1 of the second voltage dividing resistor row 124 is not connected to the driving power supply VDD, and as illustrated in FIG. 5, the positive electrode among the voltage dividing nodes of the first voltage dividing resistor row 122. It may be connected to the voltage dividing node R_1 and R_2 generating the i th gray voltage PBV_i of the gender. In addition, the g-th voltage divider Rr_g of the third voltage divider resistor 126 is not connected to the base power supply VSS, and as shown in FIG. 5, the negative divider node of the first voltage divider resistor 122 may be negative. It may be connected to the divided node R_g-1 and R_g generating the i th gray voltage NBV_i of the polarity.

As described above, the gray voltage generator 120 uses the first divided resistance string 122 to display the upper and lower gray voltages PBV_x and NBV_x for the positive and negative polarities, and the three common color voltages for the positive and negative polarities. (PCV_y, NCV_y) and positive and negative red / green in accordance with the first and second frame control signals FCS1 and FCS2 using the second and third voltage divider resistor lines 124 and 126. The upper gray level voltages PRGV_x and NRGV_x or the red and green upper modulation gray level voltages PRGMV_x and NRGMV_x are generated. At this time, in order to compensate for the color temperature in every two frame units, that is, even-numbered frames, each of the blue upper gray level voltages PBV_x of the positive polarity is relatively constant than each of the red top green gray level voltages PRGMV_x of the positive polarity. In addition to having a high voltage level, each of the blue upper gray level voltages NBV_x of the negative polarity has a voltage level that is relatively constant lower than that of each of the red and green upper modulation gray level voltages NRGMV_x of the negative polarity.

In FIG. 2, each of the first to j-th reference gamma voltages GMA_1 to GMA_j supplied to the gray voltage generator 120 is buffered by the gamma buffer unit 125 built in the data driver 100. After output to the outside of the driving device 100 (for example, a data printed circuit board) is supplied again. This is to compensate for the deviation of the first to jth reference gamma voltages GMA_1 to GMA_j supplied to the data driving apparatuses 100 when a plurality of data driving apparatuses 100 are used.

The digital processor 130 includes a shift register unit 132 and a latch unit 134.

The shift register unit 132 sequentially shifts the first enable signal EN1 corresponding to the source start pulse SSP from the control block 110 according to the source shift clock SSC to convert the sampling signal Sam. And the generated sampling signal Sam is supplied to the latch unit 134. The shift register unit 132 is a bidirectional shift register, and the forward carry signal Car / EN2 or the reverse carry signal Car / EN1 generated by the shift register unit 132 is externally controlled through the control block 110. It is supplied by the source start pulse SSP of another data driver.

The latch unit 134 latches each of the red, green, and blue data signals R, G, and B supplied from the control block 110 according to the sampling signal Sam supplied from the shift register unit 132. The latch unit 134 supplies the latch data RData to the analog processor 140 according to the source output signal SOE. At this time, the latch unit 134 sequentially latches each of the red, green, and blue data signals R, G, and B corresponding to the number of output channels of the data driver 110. That is, the latch unit 134 sequentially latches the data signal R of the first channel to the data signal B of the last channel, and then the data signals R of all the channels latched according to the source output signal SOE. Output G and B) simultaneously.

The analog processor 140 includes a digital analog converter 142 and an output buffer unit 144.

As illustrated in FIG. 6, the digital-to-analog converter 142 includes a plurality of data conversion blocks having 12 channels, and each data conversion block has x numbers supplied from the gray voltage generator 120. Positive and negative blue upper gradation voltages (PBV, NBV), y positive and negative tricolor common gradation voltages (PCV, NCV) and x positive and negative polarities The red, green, and blue latch data (RData) inputted by using the upper / lower gray voltages (PRGV, NRGV) or higher modulation gray voltages (PRGMV, NRGMV) for red / green are converted into red, green, and blue image signals, respectively. A data converter 200; Red, green, and blue latches supplied to the data converter 200 from the first to twelfth input channels Cm-11 to Cm, where m is a multiple of 12, according to the first and second polarity control signals POL1 and POL2. A data path controller 300 for controlling each path of data RData; And an image signal for controlling a path of each of the red, green, and blue image signals VData supplied from the data converter 200 to the output buffer unit 144 according to the first and second polarity control signals POL1 and POL2. It is configured to include a path control unit 400.

The data converter 200 includes first to twelfth decoders D1 to D12 in which a positive polarity (P) decoder and a negative polarity (N) decoder are disposed to correspond to the horizontal two dot inversion scheme. In this case, the first to twelfth decoders D1 to D12 are repeatedly arranged in the order of the positive polarity (P) decoder, the negative polarity (N) decoder, the negative polarity (N) decoder, and the positive polarity (P) decoder.

Each of the first, fourth, fifth, and eighth decoders D1, D4, D5, and D8 has a positive red / green upper grayscale voltage PRGV having x supplied from the grayscale voltage generator 120, or The red or green latch data RData is converted into a positive red or green image signal VData using the upper modulation grayscale voltage PRGMV and the positive tricolor common gradation voltage PCV having y pieces.

Each of the second, seventh, tenth, and eleventh decoders D2, D7, D10, and D11 has x negative voltages supplied from the gray voltage generator 120 and has a negative red / green high gray voltage (NRGV). Alternatively, the red or green latch data (RData) is converted into a negative red or green image signal (VData) by using the higher modulation gray voltage (NRGMV) and the negative tricolor common gray voltage (NCV) having y. do.

Each of the ninth and twelfth decoders D9 and D12 has a positive blue upper gray level voltage PBV having x pieces supplied from the gray level voltage generating unit 120 and a positive three-color common gray level voltage having y pieces. PCL) converts the blue latch data RData into a positive blue image signal VData.

Each of the third and sixth decoders D3 and D6 has a negative blue upper gray level voltage (NBV) having x pieces supplied from the gray level voltage generator 120 and a negative three-color common gray level having y pieces. The blue latch data RData is converted into a negative blue image signal VData using the voltage NCV.

The data path controller 300 controls the polarity of the image signal to correspond to the horizontal 1 dot or horizontal 2 dot inversion scheme according to the first and second polarity control signals POL1 and POL2. And first and second data path controllers 310 and 320 for controlling the paths of the latch data RData supplied to the data converter 200 from 11 to Cm.

The first data path controller 310 includes first to tenth data path selectors S1 to S10.

The first data path selector S1 outputs a blue latch data RData supplied to the third or twelfth input channels Cm-9 and Cm according to the second polarity control signal POL2. A second switching unit for outputting blue latch data RData supplied to the ninth or third input channels Cm-3 and Cm-9 according to the unit S1a and the second polarity control signal POL2. S1b). The first switching unit S1a selects and outputs the blue latch data RData of the third input channel Cm-9 according to the second polarity control signal POL2 of the first logic state, and outputs the blue latch data RData of the second logic state. The blue latch data RData of the twelfth input channel Cm is selected and output according to the second polarity control signal POL2. The second switching unit S1b selects and outputs the blue latch data RData of the ninth input channel Cm-3 according to the second polarity control signal POL2 of the first logic state, and outputs the blue latch data RData of the second logic state. The blue latch data RData of the third input channel Cm-9 is selected and output according to the second polarity control signal POL2.

The second data path selector S2 is connected to the red latch data RData or the eleventh input channel Cm-1 supplied to the fourth input channel Cm-8 according to the second polarity control signal POL2. The first switching unit S2a outputting the supplied green latch data RData and the red latch data RData supplied to the tenth input channel Cm-2 according to the second polarity control signal POL2. Or a second switching unit S2b for outputting red latch data RData supplied to the fourth input channel Cm-8. The first switching unit S2a selects and outputs the red latch data RData of the fourth input channel Cm-8 according to the second polarity control signal POL2 of the first logic state, and outputs the red latch data RData of the second logic state. The green latch data RData of the eleventh input channel Cm−1 is selected and output according to the second polarity control signal POL2. The second switching unit S2b selects and outputs the red latch data RData of the tenth input channel Cm-2 according to the second polarity control signal POL2 of the first logic state, and outputs the red latch data RData of the second logic state. The red latch data RData of the fourth input channel Cm-8 is selected and output according to the second polarity control signal POL2.

The third data path selector S3 selects and outputs the green latch data RData of the eleventh input channel Cm-1 according to the second polarity control signal POL2 in the first logic state and outputs the second logic. The red latch data RData of the tenth input channel Cm-2 is selected and output according to the second polarity control signal POL2 in the state.

The fourth data path selector S4 selects and outputs the blue latch data RData of the twelfth input channel Cm according to the second polarity control signal POL2 of the first logic state, and outputs the blue latch data RData of the second logic state. The blue latch data RData of the ninth input channel Cm-3 is selected and output according to the second polarity control signal POL2.

The fifth data path selector S5 is connected to the red latch data RData or the eighth input channel Cm-4, which is supplied to the seventh input channel Cm-5 according to the second polarity control signal POL2. Green latch data RData or seventh of the eighth input channel Cm-4 according to the first switching unit S5a outputting the supplied green latch data RData and the second polarity control signal POL2. And a second switching unit S5b for outputting red latch data RData supplied to the input channel Cm-5. The first switching unit S5a selects and outputs the red latch data RData of the seventh input channel Cm-5 according to the second polarity control signal POL2 of the first logic state, and outputs the red latch data RData of the second logic state. The green latch data RData of the eighth input channel Cm-4 is selected and output according to the second polarity control signal POL2. The second switching unit S5b selects and outputs the green latch data RData of the eighth input channel Cm-4 according to the second polarity control signal POL2 of the first logic state, and outputs the selected data. The red latch data RData of the seventh input channel Cm-5 is selected and output according to the second polarity control signal POL2.

The sixth data path selector S6 may include the red latch data RData of the eighth input channel Cm-4 or the red latch data of the seventh input channel Cm-5 according to the second polarity control signal POL2. The red latch data RData or the eighth input channel Cm-4 of the seventh input channel Cm-5 according to the first switching unit S6a for outputting (RData) and the second polarity control signal POL2. And a second switching unit S6b for outputting the green latch data RData. The first switching unit S6a selects and outputs the green latch data RData of the eighth input channel Cm-4 according to the second polarity control signal POL2 of the first logic state, and outputs the selected data. The red latch data RData of the seventh input channel Cm-5 is selected and output according to the second polarity control signal POL2. The second switching unit S6b selects and outputs the red latch data RData of the seventh input channel Cm-5 according to the second polarity control signal POL2 of the first logic state, and outputs the second latch state S6b. The green latch data RData of the eighth input channel Cm-4 is selected and output according to the second polarity control signal POL2.

The seventh data path selector S7 selects and outputs the blue latch data RData of the third input channel Cm-9 according to the second polarity control signal POL2 in the first logic state, and outputs the second logic. The blue latch data RData of the sixth input channel Cm-6 is selected and output according to the second polarity control signal POL2 in the state.

The eighth data path selector S8 selects and outputs the red latch data RData of the fourth input channel Cm-8 according to the second polarity control signal POL2 of the first logic state, and outputs the second logic. The green latch data RData supplied to the fifth input channel Cm-7 is selected and output according to the second polarity control signal POL2 in the state.

The ninth data path selector S9 includes the green latch data RData of the eleventh input channel Cm-1 or the red latch data of the fourth input channel Cm-8 according to the second polarity control signal POL2. The green latch data RData of the fifth input channel Cm-7 or the eleventh input channel Cm-1 according to the first switching unit S9a for outputting (RData) and the second polarity control signal POL2. And a second switching unit S9b for outputting the green latch data RData. The first switching unit S9a selects and outputs the green latch data RData of the eleventh input channel Cm-1 according to the second polarity control signal POL2 of the first logic state and outputs the second latch state. The red latch data RData of the fourth input channel Cm-8 is selected and output according to the second polarity control signal POL2. The second switching unit S9b selects and outputs the green latch data RData of the fifth input channel Cm-7 according to the second polarity control signal POL2 of the first logic state, and outputs the selected data. The green latch data RData of the eleventh input channel Cm−1 is selected and output according to the second polarity control signal POL2.

The tenth data path selector S10 may include the blue latch data RData of the twelfth input channel Cm or the blue latch data RData of the third input channel Cm-9 according to the second polarity control signal POL2. ) Blue latch data RData of the sixth input channel Cm-6 or blue latch of the twelfth input channel Cm according to the first switching unit S10a and the second polarity control signal POL2. And a second switching unit S10b for outputting data RData. The first switching unit S10a selects and outputs the blue latch data RData of the twelfth input channel Cm according to the second polarity control signal POL2 of the first logic state, and outputs the second latch state of the second logic state. The blue latch data RData of the third input channel Cm-9 is selected and output according to the polarity control signal POL2. The second switching unit S10b selects and outputs the blue latch data RData of the sixth input channel Cm-6 according to the second polarity control signal POL2 of the first logic state, and outputs the blue latch data RData of the second logic state. The blue latch data RData of the twelfth input channel Cm is selected and output according to the second polarity control signal POL2.

The second data path controller 320 includes first to twelfth data selectors M1 to M2.

The first data selector M1 supplies the red latch data RData of the first input channel Cm-11 to the first decoder D1 when the first polarity control signal POL1 is in the first logic state. When the first polarity control signal POL1 is in the second logic state, the green latch data RData of the second input channel Cm-10 is supplied to the first decoder D1.

The second data selector M2 selects the green latch data RData of the second input channel Cm-10 to the second decoder D2 when the first polarity control signal POL1 is in the first logic state. When the first polarity control signal POL1 is in the second logic state, the red latch data RData of the first input channel Cm-11 is supplied to the second decoder D2.

The third data selector M3 is the third or twelfth input supplied from the first switch S1a of the first data path selector S1 when the first polarity control signal POL1 is in the first logic state. When the blue latch data RData of the channels Cm-9 and Cm is supplied to the third decoder D3, and the first polarity control signal POL1 is in the second logic state, the first data path selector S1. The blue latch data RData of the ninth or third input channels Cm-3 and Cm-9 supplied from the second switching unit S1b of the second supply unit S1b is supplied to the third decoder D3.

The fourth data selector M4 is the fourth input channel Cm supplied from the first switch S2a of the second data path selector S2 when the first polarity control signal POL1 is in the first logic state. The red latch data RData of -8) or the green latch data RData of the eleventh input channel Cm-1 is supplied to the fourth decoder D4, and the first polarity control signal POL1 is supplied with the second logic. In the state of the red latch data (RData) or the fourth input channel (Cm-8) of the tenth input channel (Cm-2) supplied from the second switching unit (S2b) of the second data path selector (S2). The red latch data RData is supplied to the fourth decoder D4.

The fifth data selector M5 supplies the green latch data RData of the fifth input channel Cm-7 to the fifth decoder D5 when the first polarity control signal POL1 is in the first logic state. When the first polarity control signal POL1 is in the second logic state, the green latch data RData or the tenth input channel of the eleventh input channel Cm-1 supplied from the third data path selector S3 may be The red latch data RData of Cm-2 is supplied to the fifth decoder D5.

The sixth data selector M6 supplies the blue latch data RData of the sixth input channel Cm-6 to the sixth decoder D6 when the first polarity control signal POL1 is in the first logic state. When the first polarity control signal POL1 is in the second logic state, the blue latch data RData of the twelfth or ninth input channels Cm and Cm-3 supplied from the fourth data path selector S4 is received. The sixth decoder D6 is supplied.

The seventh data selector M7 is the seventh input channel Cm supplied from the first switch S5a of the fifth data path selector S5 when the first polarity control signal POL1 is in the first logic state. The red latch data RData of -5) or the green latch data RData of the eighth input channel Cm-4 is supplied to the seventh decoder D7, and the first polarity control signal POL1 is supplied with the second logic. In the state of the green latch data of the eighth input channel (Cm-4) or the seventh input channel (Cm-5) of the eighth input channel (Cm-4) supplied from the second switching unit (S5b) of the fifth data path selector (S5). The red latch data RData is supplied to the seventh decoder D7.

The eighth data selector M8 is the eighth input channel Cm supplied from the first switch S6a of the sixth data path selector S6 when the first polarity control signal POL1 is in the first logic state. The green latch data RData of -4) or the red latch data RData of the seventh input channel Cm-5 is supplied to the eighth decoder D8, and the first polarity control signal POL1 receives the second polarity control signal POL1. In the logic state, the red latch data RData or the eighth input channel Cm-4 of the seventh input channel Cm-5 supplied from the second switching unit S6b of the sixth data path selector S6. Green latch data RData is supplied to the eighth decoder D8.

The ninth data selector M9 supplies the blue latch data RData of the ninth input channel Cm-3 to the ninth decoder D9 when the first polarity control signal POL1 is in the first logic state. When the first polarity control signal POL1 is in the second logic state, the blue latch data RData of the third or sixth input channels Cm-9 and Cm-6 supplied from the seventh data path selector S7. ) Is supplied to the ninth decoder D9.

The tenth data selector M10 supplies the red latch data RData of the tenth input channel Cm-2 to the tenth decoder D10 when the first polarity control signal POL1 is in the first logic state. When the first polarity control signal POL1 is in the second logic state, the red latch data RData or the fifth channel Cm of the fourth input channel Cm-8 supplied from the eighth data path selector S8. The green latch data RData of -7) is supplied to the tenth decoder D10.

The eleventh data selector M11 is the eleventh input channel Cm supplied from the first switch S9a of the ninth data path selector S9 when the first polarity control signal POL1 is in the first logic state. The green latch data RData of -1) or the red latch data RData of the fourth input channel Cm-8 is supplied to the eleventh decoder D11, and the first polarity control signal POL1 is applied to the second logic. In the state, the green latch data RData of the fifth or eleventh input channels Cm-7 and Cm-1 supplied from the second switching unit S9b of the ninth data path selector S9 is decoded. It supplies to (D11).

The twelfth data selector M12 is a twelfth or third input supplied from the first switch S10a of the tenth data path selector S10 when the first polarity control signal POL1 is in a first logic state. When the blue latch data RData of the channels Cm and Cm-9 is supplied to the twelfth decoder D12 and the first polarity control signal POL1 is in the second logic state, the tenth data path selector S10. The blue latch data RData of the sixth or twelfth input channels Cm-6 and Cm supplied from the second switching unit S10b is supplied to the twelfth decoder D12.

The image signal path controller 400 corresponds to the horizontal 1 dot or horizontal 2 dot inversion scheme according to the first and second polarity control signals POL1 and POL2 of the image signal VData supplied from the data converter 200. The first and second image signal path controllers 410 and 420 which control the path of the image signal VData so as to be supplied to the data output unit 144 may be included.

The first image signal path control unit 410 includes first to tenth image signal path selection units s1 to s10.

The first image signal path selector s1 outputs a blue image signal VData from each of the third or twelfth decoders D3 and D12 according to the second polarity control signal POL2. ) And a second switching unit s1b which outputs a blue image signal VData from each of the ninth or third decoders D9 and D3 in accordance with the second polarity control signal POL2. The first switching unit s1a selects and outputs the negative blue image signal VData supplied from the third decoder D3 according to the second polarity control signal POL2 in the first logic state, and the second logic. According to the second polarity control signal POL2 in the state, the positive blue image signal VData supplied from the twelfth decoder D12 is selected and output. The second switching unit s1b selects and outputs the positive blue image signal VData supplied from the ninth decoder D9 according to the second polarity control signal POL2 of the first logic state, and the second logic state. The blue image signal VData of the negative polarity supplied from the third decoder D3 is selected and output in accordance with the second polarity control signal POL2.

The second image signal path selector s2 is configured to display the red image signal VData from the fourth decoder D4 or the green image signal VData from the eleventh decoder D11 according to the second polarity control signal POL2. The red image signal VData from the tenth decoder D10 or the red image signal VData from the fourth decoder D4 in accordance with the first switching unit s2a and the second polarity control signal POL2. It is configured to include a second switching unit (s2b) for outputting. The first switching unit s2a selects and outputs a positive red image signal VData supplied from the fourth decoder D4 according to the second polarity control signal POL2 of the first logic state and outputs the second logic state. The green image signal VData supplied from the eleventh decoder D11 is selected and output in accordance with the second polarity control signal POL2. The second switching unit s2b selects and outputs the red image signal VData supplied from the tenth decoder D10 according to the second polarity control signal POL2 in the first logic state, and outputs the second logic state in the second logic state. The red image signal VData from the fourth decoder D4 is selected and output in accordance with the two polarity control signals POL2.

The third image signal path selector s3 selects and outputs the negative green image signal VData supplied from the eleventh decoder D11 according to the second polarity control signal POL2 in the first logic state. In response to the second polarity control signal POL2 in the second logic state, the negative red image signal VData supplied from the tenth decoder D10 is selected and output.

The fourth image signal path selector s4 selects and outputs a positive blue image signal VData supplied from the twelfth decoder D12 in accordance with the second polarity control signal POL2 in the first logic state. The blue image signal VData of the positive polarity supplied from the ninth decoder D9 is selected and output in accordance with the second polarity control signal POL2 in the logic state.

The fifth image signal path selector s5 is the red image signal VData from the seventh decoder D7 or the green image signal VData from the eighth decoder D8 in accordance with the second polarity control signal POL2. The green image signal VData from the eighth decoder D8 or the red image signal VData from the seventh decoder D7 according to the first switching unit s5a and the second polarity control signal POL2. It is configured to include a second switching unit (s5b) for outputting. The first switching unit s5a selects and outputs the negative red image signal VData supplied from the seventh decoder D7 according to the second polarity control signal POL2 in the first logic state, and the second logic. According to the second polarity control signal POL2 in the state, the positive green image signal VData supplied from the eighth decoder D8 is selected and output. The second switching unit s5b selects and outputs the positive green image signal VData supplied from the eighth decoder D8 according to the second polarity control signal POL2 of the first logic state, and outputs the second logic state. According to the second polarity control signal POL2, the negative red image signal VData supplied from the seventh decoder D7 is selected and output.

The sixth image signal path selector s6 is provided with the red image signal VData from the eighth decoder D8 or the red image signal VData from the seventh decoder D7 in accordance with the second polarity control signal POL2. The red image signal VData from the seventh decoder D7 or the green image signal VData from the eighth decoder D8 in accordance with the first switching unit s6a and the second polarity control signal POL2. It is configured to include a second switching unit (s6b) for outputting. The first switching unit s6a selects and outputs the positive green image signal VData supplied from the eighth decoder D8 according to the second polarity control signal POL2 of the first logic state, and the second logic state. According to the second polarity control signal POL2, the negative red image signal VData supplied from the seventh decoder D7 is selected and output. The second switching unit s6b selects and outputs a negative red image signal VData supplied from the seventh decoder D7 according to the second polarity control signal POL2 in the first logic state, and the second logic. According to the second polarity control signal POL2 in the state, the positive green image signal VData supplied from the eighth decoder D8 is selected and output.

The seventh image signal path selector s7 selects and outputs a negative blue image signal VData supplied from the third decoder D3 according to the second polarity control signal POL2 in the first logic state. The blue image signal VData of the negative polarity supplied from the sixth decoder D6 is selected and output according to the second polarity control signal POL2 in the second logic state.

The eighth image signal path selector s8 selects and outputs a positive red image signal VData supplied from the fourth decoder D4 according to the second polarity control signal POL2 in the first logic state. The positive green image signal VData supplied to the fifth decoder D5 is selected and output according to the second polarity control signal POL2 in the second logic state.

The ninth image signal path selector s9 is the green image signal VData from the eleventh decoder D11 or the red image signal VData from the fourth decoder D4 in accordance with the second polarity control signal POL2. The green image signal VData from the fifth decoder D5 or the green image signal VData from the eleventh decoder D11 according to the first switching unit s9a and the second polarity control signal POL2. It is configured to include a second switching unit (s9b) for outputting. The first switching unit s9a selects and outputs the negative green image signal VData supplied from the eleventh decoder D11 according to the second polarity control signal POL2 in the first logic state, and the second logic. According to the second polarity control signal POL2 in the state, the positive red image signal VData supplied from the fourth decoder D4 is selected and output. The second switching unit s9b selects and outputs the positive green image signal VData supplied from the fifth decoder D5 according to the second polarity control signal POL2 of the first logic state, and outputs the second logic state. The negative polarity green image signal VData supplied from the eleventh decoder D11 is selected and output according to the second polarity control signal POL2.

The tenth image signal path selector s10 may be a blue image signal VData from the twelfth decoder D12 or a blue image signal VData from the third decoder D3 according to the second polarity control signal POL2. The blue image signal VData from the sixth decoder D6 or the blue image signal VData from the twelfth decoder D12 according to the first switching unit s10a and the second polarity control signal POL2. It is configured to include a second switching unit (s10b) for outputting. The first switching unit s10a selects and outputs a positive blue image signal VData supplied from the twelfth decoder D12 according to the second polarity control signal POL2 of the first logic state, and outputs the second logic state. According to the second polarity control signal POL2, the negative blue image signal VData from the third decoder D3 is selected and output. The second switching unit s10b selects and outputs the negative blue image signal VData supplied from the sixth decoder D6 according to the second polarity control signal POL2 in the first logic state, and the second logic. According to the second polarity control signal POL2 in the state, the positive blue image signal VData supplied from the twelfth decoder D12 is selected and output.

The second image signal path control section 420 includes first to twelfth image signal selection sections m1 to m12.

The first image signal selector m1 outputs a positive red image signal VData supplied from the first decoder D1 when the first polarity control signal POL1 is in the first logic state. The output buffer unit outputs the negative red image signal VData supplied to the first buffer line Im-11 and supplied from the second decoder D2 when the first polarity control signal POL1 is in the second logic state. It is supplied to the first buffer line Im-11 of 144. At this time, the positive or negative red image signal VData supplied to the first buffer line Im-11 is data supplied to the first input channel Cm-11.

The second image signal selector m2 outputs the negative green image signal VData supplied from the second decoder D2 when the first polarity control signal POL1 is in the first logic state. An output buffer unit for supplying the positive green image signal VData supplied to the second buffer line Im-10 of the second buffer line and supplied from the first decoder D1 when the first polarity control signal POL1 is in the second logic state. The second buffer line Im-10 is supplied to the second buffer line Im-10. In this case, the positive or negative green image signal VData supplied to the second buffer line Im-10 is data supplied to the second input channel Cm-10.

When the first polarity control signal POL1 is in the first logic state, the third image signal selector m3 is configured to perform a third decoder D3 through the first switching unit s1a of the first image signal path selector s1. The blue color image signal VData supplied from the negative polarity or the blue color image signal VData supplied from the twelfth decoder D12 is supplied to the third buffer line Im-9 of the output buffer unit 144. When the first polarity control signal POL1 is in the second logic state, the positive blue image supplied from the ninth decoder D9 through the second switching unit s1b of the first image signal path selection unit s1. The blue image signal VData of the negative polarity supplied from the signal VData or the third decoder D3 is supplied to the third buffer line Im-9 of the output buffer unit 144. At this time, the positive or negative blue image signal VData supplied to the third buffer line Im-9 is data supplied to the third input channel Cm-9.

The fourth image signal selector m4 is configured to pass through the fourth decoder D4 through the first switching unit s2a of the second image signal path selector s2 when the first polarity control signal POL1 is in the first logic state. ) Is supplied to the fourth buffer line Im-8 of the output buffer unit 144 by the positive red image signal VData supplied from the negative polarity or the red image signal VData supplied from the eleventh decoder D11. When the first polarity control signal POL1 is in the second logic state, the negative polarity supplied from the tenth decoder D10 through the second switching unit s2b of the second image signal path selection unit s2 is negative. The positive red image signal VData supplied from the red image signal VData or the fourth decoder D4 is supplied to the fourth buffer line Im-8 of the output buffer unit 144. In this case, the positive or negative red image signal VData supplied to the fourth buffer line Im-8 is data supplied to the fourth input channel Cm-8.

The fifth image signal selector m5 may output the positive green image signal VData supplied from the fifth decoder D5 when the first polarity control signal POL1 is in the first logic state. Supplied to the fifth buffer line Im-7 and supplied from the eleventh decoder D11 through the third image signal path selector s3 when the first polarity control signal POL1 is in the second logic state. The polarity green image signal VData or the negative red image signal VData supplied from the tenth decoder D10 is supplied to the fifth buffer line Im-7 of the output buffer unit 144. At this time, the positive or negative green image signal VData supplied to the fifth buffer line Im-7 is data supplied to the fifth input channel Cm-7.

The sixth image signal selector m6 outputs the negative blue image signal VData supplied from the sixth decoder D6 when the first polarity control signal POL1 is in the first logic state. Supplied to the sixth buffer line Im-6 and supplied from the twelfth decoder D12 through the fourth image signal path selection unit s4 when the first polarity control signal POL1 is in the second logic state. The positive blue image signal VData or the positive blue image signal VData supplied from the ninth decoder D9 is supplied to the sixth buffer line Im-6 of the output buffer unit 144. In this case, the positive or negative blue image signal VData supplied to the sixth buffer line Im-6 is data supplied to the sixth input channel Cm-6.

When the first polarity control signal POL1 is in the first logic state, the seventh image signal selector m7 may operate the seventh decoder D7 through the first switching unit s5a of the fifth image signal path selector s5. ) Is supplied to the seventh buffer line Im-5 of the output buffer unit 144 by the negative red image signal VData supplied from the negative polarity or the red image signal VData supplied from the eighth decoder D8. And the red image of the positive polarity supplied from the eighth decoder D8 through the second switching unit s5b of the fifth image signal path selection unit s5 when the first polarity control signal POL1 is in the second logic state. The signal VData or the negative red image signal VData supplied from the seventh decoder D7 is supplied to the seventh buffer line Im-5 of the output buffer unit 144. At this time, the positive or negative red image signal VData supplied to the seventh buffer line Im-5 is data supplied to the seventh input channel Cm-5.

When the first polarity control signal POL1 is in the first logic state, the eighth image signal selector m8 may include the eighth decoder D8 through the first switching unit s6a of the sixth image signal path selector s6. The green image signal VData supplied from the positive polarity or the green image signal VData supplied from the seventh decoder D7 is supplied to the eighth buffer line Im-4 of the output buffer unit 144. When the first polarity control signal POL1 is in the second logic state, the negative green color supplied from the seventh decoder D7 through the second switching unit s6b of the sixth image signal path selection unit s6 The positive green image signal VData supplied from the image signal VData or the eighth decoder D8 is supplied to the eighth buffer line Im-4 of the output buffer unit 144. At this time, the positive or negative green image signal VData supplied to the eighth buffer line Im-4 is data supplied to the eighth input channel Cm-4.

The ninth image signal selector m9 outputs the positive blue image signal VData supplied from the ninth decoder D9 when the first polarity control signal POL1 is in the first logic state. Supplied to the ninth buffer line Im-3 and supplied from the third decoder D3 through the seventh image signal path selector s7 when the first polarity control signal POL1 is in the second logic state. The blue image signal VData having the polarity or the blue image signal VData having the negative polarity supplied from the sixth decoder D6 is supplied to the ninth buffer line Im-3 of the output buffer unit 144. At this time, the positive or negative blue image signal VData supplied to the ninth buffer line Im-3 is data supplied to the ninth input channel Cm-3.

The tenth image signal selector m10 may output the red image signal VData supplied from the tenth decoder D10 when the first polarity control signal POL1 is in the first logic state, to the tenth image of the output buffer unit 144. The positive red color supplied to the buffer line Im-2 and supplied from the fourth decoder D4 through the eighth image signal path selector s8 when the first polarity control signal POL1 is in the second logic state. The positive red image signal VData supplied from the image signal VData or the fifth decoder D5 is supplied to the tenth buffer line Im-2 of the output buffer unit 144. At this time, the positive or negative red image signal VData supplied to the tenth buffer line Im-2 is data supplied to the tenth input channel Cm-2.

When the first polarity control signal POL1 is in the first logic state, the eleventh image signal selector m11 receives the eleventh decoder D11 through the first switching unit s9a of the ninth image signal path selector s9. Negative green image signal VData supplied from the PDP or the positive green image signal VData supplied from the fourth decoder D4 to the eleventh buffer line Im-1 of the output buffer unit 144. And the positive green color supplied from the fifth decoder D5 through the second switching unit s9b of the ninth image signal path selection unit s9 when the first polarity control signal POL1 is in the second logic state. The negative green image signal VData supplied from the image signal VData or the eleventh decoder D11 is supplied to the eleventh buffer line Im-1 of the output buffer unit 144. At this time, the positive or negative green image signal VData supplied to the eleventh buffer line Im-1 is data supplied to the eleventh input channel Cm-1.

The twelfth image signal selector m12 uses the first switch unit s10a of the tenth image signal path selector s10 when the first polarity control signal POL1 is in a first logic state, to allow the twelfth decoder D12 to operate. ) Is supplied to the twelfth buffer line Im of the output buffer unit 144 by supplying the positive blue image signal VData supplied from the PDP or the negative blue image signal VData supplied from the third decoder D3, When the first polarity control signal POL1 is in the second logic state, the negative blue image signal supplied from the sixth decoder D6 through the second switching unit s10b of the tenth image signal path selection unit s10 The positive blue image signal VData supplied from (VData) or the twelfth decoder D12 is supplied to the twelfth buffer line Im of the output buffer unit 144. At this time, the positive or negative blue image signal VData supplied to the twelfth buffer line Im is data supplied to the twelfth input channel Cm.

As described above, the digital-to-analog converter 142 uses the data path controller 300 and the image signal path controller 400 according to the logic states of the first and second polarity control signals POL1 and POL2. The latch data RData is converted into an image signal VData to be supplied to the output buffer unit 144 so as to have a polar pattern of a horizontal 1 dot or horizontal 2 dot inversion scheme by controlling the path of.

For example, when the first and second polarity control signals POL1 and POL2 both have a first logic state, the digital-to-analog converter 142 of the image signal VData, as shown in FIG. The polarity pattern is converted into a horizontal two-dot inversion method and supplied to the output buffer unit 144. At this time, the polarity pattern of the horizontal two-dot inversion type has the polarity reversed in units of two input channels in the horizontal direction except for the first input channel Cm-11, and thus "+-++-++- It has the form + ".

In addition, when the first polarity control signal POL1 has a second logic state and the second polarity control signal POL2 has a first logic state, the digital-to-analog converter 142 is illustrated in FIG. 7B. As described above, the polarity pattern of the image signal VData is converted into an inverted horizontal two-dot inversion scheme and supplied to the output buffer unit 144. At this time, the polarized pattern of the inverted horizontal two-dot inversion type has the polarity inverted in units of two input channels in the horizontal direction except for the first input channel Cm-11, and thus the "-++-++- ++-"

In addition, when the first polarity control signal POL1 has a first logic state and the second polarity control signal POL2 has a second logic state, the digital-to-analog converter 142 is illustrated in FIG. 7C. As described above, the polarity pattern of the image signal VData is converted into the horizontal one-dot inversion method and supplied to the output buffer unit 144. At this time, the polarity pattern of the horizontal 1 dot inversion type has a shape such as "+-+-+-+-+-+-" because the polarity is inverted in each input channel unit in the horizontal direction.

In addition, when the first and second polarity control signals POL1 and POL2 have a second logic state, the digital-to-analog converter 142 may have a polarity pattern of the image signal VData as shown in FIG. 7D. Is converted into an inverted horizontal 1 dot inversion scheme and supplied to the output buffer unit 144. At this time, the polarized pattern of the inverted horizontal 1 dot inversion method has a shape such as "-+-+-+-+-+-+" because the polarity is inverted for each input channel unit in the horizontal direction.

As a result, the digital-to-analog converter 142 performs a path for each of the data and image signals so as to correspond to the horizontal two-dot or horizontal one-dot inversion scheme according to the logic states of the first and second polarity control signals POL1 and POL2. By controlling, the number of decoders is configured equal to the number of output channels.

The output buffer unit 144 buffers the image signal VData of each channel supplied from the digital-to-analog converter 142 and outputs the result to the outside through the final output channel. At this time, the output buffer unit 144 amplifies and outputs the image signal VData in consideration of an external load.

As such, the data driver 100 according to the first embodiment of the present invention separately separates the upper gray voltages PBV and NBV for blue and the upper gray voltages PRGV, NRGV or PRGMV, and NRGMV for red / green. In addition, the color temperature according to the gray level is kept constant while the upper and lower gray level voltages (PRGV, NRGV) or the higher modulation gray level voltages (PRGMV, NRGMV) for green / green are alternately controlled on a frame basis. May be minimized and the size of the gray voltage generator 120 may be reduced. Specifically, as shown in FIG. 8, the data driving apparatus 100 according to the first embodiment of the present invention controls the first frame in the first logical state in the odd-numbered frame (section A of FIG. 4) among the frames. By using the signal FCS1 and the second frame control signal FCS2 in the second logic state, the blue gray voltage and the red / green gray voltage are set equal to each other to obtain an image signal having an uneven color temperature such as curve A. In the even-numbered frame (section B of FIG. 4), the gray gray voltage and the red gray voltage are used by using the first frame control signal FCS1 in the second logic state and the second frame control signal FCS2 in the first logic state. The green gradation voltage is set differently to generate an image signal having a uniform color temperature, such as curve B, but with reduced luminance according to color temperature correction. Therefore, the data driving apparatus 100 according to the first embodiment of the present invention alternately repeats the correction of the color temperature and the non-correction of the color temperature in units of frames, thereby correcting the color temperature such as the curve C and decreasing the luminance. Generates a minimized image signal.

Furthermore, the present invention can reduce the size of the data driver 100 by configuring the number of decoders of the digital-to-analog converter 142 equal to the number of output channels of the data driver 100.

Meanwhile, in the data driving apparatus according to the first embodiment of the present invention, the upper gray levels of the blue gray voltages PBV_x and NBV_x and the red / green gray voltages PRGV_x and NRGV_x are independently separated and individually controlled. However, the present invention is not limited thereto, and as described below, the lower gray levels may be separated and individually controlled.

9 is a block diagram schematically illustrating a gray scale generator of a data driving apparatus according to a second exemplary embodiment of the present invention.

9, the data driving apparatus 100 according to the second exemplary embodiment of the present invention has the same configuration as that of the first exemplary embodiment of the present invention illustrated in FIG. 2 except for the gray scale generator 120. Has Accordingly, the description of the other components except the description of the gray scale generator 120 will be replaced with the above description.

The gray scale generator 120 of the data driving apparatus 100 according to the second embodiment of the present invention includes first to third divided resistance strings 2122, 2124, and 2126.

The first divided resistor row 2122 includes first to g-th divided resistors R_1 to R_g connected in series between the driving power source VDD and the base power source VSS. The first divided resistor string 2122 is divided into first and second common regions 2122c1 and 2122c2 and first and second regions 2122a and 2122b according to a voltage generated by voltage division using a resistor. .

The first common area 2122c1 includes the first to cc (but cc is a natural number larger than c and smaller than d) voltage-dividing resistors R_1 to R_cc connected in series. The first to r1-1 (where r1 is a natural number greater than k1 and less than j / 2) of the j reference gamma voltages GMA_j is included in the divided node in the middle of the first common area 2122c1. Voltages GMA_1 to GMA_r1-1 are supplied. For example, the first reference gamma voltage GMA_1 is supplied to the divided nodes R_1 and R_2 that generate the three-color common i gray level voltage PCV_i among the divided nodes of the first common area 2122c1. The second reference gamma voltage GMA_2 may or may not be supplied to the divided nodes R_2 and R_3 that generate the tricolor common i-1 grayscale voltage PCV_i-1. In addition, the k1th reference gamma voltage GMA_k1 is supplied to the divided nodes R_c-1 and R_c generating the three-color common h-th gray voltage PCV_h. In addition, each of the k1 + 1 to r1-1 reference gamma voltages GMA_k1 + 1 to GMA_r1-1 may include the c + 1 to cc divided voltage resistances of the first common region 2122c1 so as to have equal or boiling intervals. It is supplied to any partial pressure node among the partial pressure nodes between (R_c + 1 to R_cc).

The first common region 2122c1 includes the i-th to v + 1 th gray voltages PCV_i to PCV_v + generated by voltage division at each divided node formed between the first to cc divided voltage resistors R_1 to R_cc. The common three-color common gradation voltage PCV_y having y pieces including 1) is supplied to the analog processor 140. Here, when the number of bits of the data signal is 8, the first common area 2122c1 generates 192 positive tricolor common gradation voltages PCV_y including the positive 64 th to 255 th gradation voltages PCV_64 to PCV_255. do.

The first region 2122a includes the cc to d + 1 voltage divider R_cc to R_d + 1 connected in series. The r th through j / 2 reference gamma voltages GMA_r1 through GMA_j / 2 of the j reference gamma voltages GMA_j are supplied to the divided node in the middle of the first region 2122a. Each of the r1 to j / 2 reference gamma voltages GMA_r1 to GMA_j / 2 may include any of the first regions 2122a such that the r1 to j / 2 reference gamma voltages GMA_r1 to GMA_j / 2 have equal intervals or boiling intervals according to the electro-optical, color temperature, and gamma characteristics of the liquid crystal. It can be supplied to a partial pressure node. For example, the j / 2 reference gamma voltage GMA_j / 2 is supplied to the divided node which generates the positive zeroth gray voltage PBV_0 among the divided nodes of the first region 2122a, and receives the j / th The 2-1 reference gamma voltage GMA_j / 2-1 may or may not be supplied to the divided node that generates the first blue gray level voltage PBV_1 of the divided voltage node of the first region 2122a. In addition, the r1 reference gamma voltage GMA_r1 is supplied to the divided node which generates the positive blue th gray gray voltage PBV_v among the divided nodes of the first region 2122a. In addition, each of the r1 + 1 to j / 2-2 reference gamma voltages GMA_r1 + 1 to GMA_j / 2-2 has a cc + 2 to a th field of the first region 2122a so as to have an equal interval or a boiling interval. d is supplied to any of the divided nodes between the divided voltage resistors R_cc + 2 to R_d.

The first region 2122a includes the v th to 0 th gray voltages PBV_v to PBV_0 generated by voltage division at each divided node formed between the cc to d th divided resistors R_cc to R_d. The blue positive gray level voltage PBV_x having x pieces is supplied to the analog processor 140. Here, when the number of bits of the data signal is 8, the first region 2122a generates 64 positive blue lower gray level voltages PBV_x including the zeroth to 63rd gray voltages PBV_0 to PBV_63 of the positive polarity. .

The second area 2122b includes the voltage-dividing resistors R_dd to R_f connected in series dd (where dd is a natural number greater than d and less than ff) to f (where f is a natural number greater than dd and less than ff). It is configured by. The divided voltage node in the middle of the second region 2122b is based on the j / 2 + 1 to r2 (where r2 is greater than j / 2 and less than k2) of j reference gamma voltages GMA_j. Gamma voltages GMA_j / 2 + 1 to GMA_r2 are supplied. Each of the second j / 2 + 1 to r2 reference gamma voltages GMA_j / 2 + 1 to GMA_r2 includes the second region 2122b to have an equal interval or a boiling interval according to the electro-optical characteristics, the color temperature characteristics, and the gamma characteristics of the liquid crystal. Can be supplied to any partial pressure node of For example, the j / 2 + 1 reference gamma voltage GMA_j / 2 + 1 is applied to the divided node which generates the zero gray level voltage NBV_0 for the negative polarity among the divided nodes of the second region 2122b. The j / 2 + 2 reference gamma voltage GMA_j / 2 + 2 is supplied to the divided node which generates the first gray-level voltage NBV_1 for negative blue among the divided nodes of the second region 2122b, or May not be supplied. Further, the j / 2 + 3 to r2-1 reference gamma voltages GMA_j / 2 + 3 to GMA_r2-1 may have the dd + 1 to f th regions of the second region 2122b so as to have an equal interval or a boiling interval. -2 is supplied to any of the divided nodes between the divided resistors R_dd + 1 to R_f-2. The r2 reference gamma voltage GMA_r2 is supplied to the voltage dividing node generating the blue-th gray level voltage NBV_v of the negative polarity among the voltage dividing nodes in the second region 2122b.

The second region 2122b includes the negative zeroth to vth gray voltages NBV_v generated by voltage division at each divided node formed between the dd to fth divided resistors R_dd to R_f. The blue negative gray voltage NBV_x having x of the negative polarity is supplied to the analog processor 140. Here, when the number of bits of the data signal is 8, the second region 2122b may include 64 negative gray level gray level voltages NBV_x including the 0th to 63rd gray voltages NBV_0 to NBV_63 of the negative polarity. Create

Meanwhile, at least one dummy resistor (not shown) may be connected between the first and second regions 2122a and 2122b.

The second common area 2122c2 includes the f-th to g-th voltage divider resistors R_f to R_g connected in series. The r-th +1 th -j th reference gamma voltages GMA_r2 + 1 to GMA_j of the j reference gamma voltages GMA_j are supplied to the divided nodes in the middle of the second common region 2122c2. For example, each of the r2 + 1 to k2-1 reference gamma voltages GMA_r2 + 1 to GMA_k2-1 may have the same f or 1 st to ff th of the second common area 2122c2 so as to have an equal interval or a boiling interval. A divided node that is supplied to any one of the divided nodes between the -1 divided resistors R_f + 1 to R_ff-1, and the k2th reference gamma voltage GMA_k2 generates the three-color common h-th grayscale voltage NCV_h. (Between R_ff and R_ff + 1). In addition, the j-1 reference gamma voltage GMA_j-1 corresponds to the divided nodes R_g-2 and R_g-1 generating the three-color common i-1 grayscale voltage NCV_i-1 of the second common area 2122c2. May or may not be supplied. The j-th reference gamma voltage GMA_j is supplied to the divided nodes R_g-1 and R_g generating the three-color common i-th gray voltage NCV_i among the divided nodes of the second common area 2122c2. Here, k2 may be set to a natural number larger than j / 2 and smaller than j, for example, j-1 or j-2.

The second common area 2122c2 may include the v + 1 to i-th grayscale voltages NCV_v + 1 to V1 which are generated by voltage division at each divided node formed between the f to g th divided resistors R_f to R_g. The negative three-color common gradation voltage NCV_y having y pieces including NCV_i is supplied to the analog processor 140. Here, when the number of bits of the data signal is 8, the second common area 2122c2 includes 192 negative tricolor common gradation voltages NCV_y including the negative 64 th to 255 th gradation voltages NCV_64 to NCV_255. Create

The first divided resistance string 2122 generates the positive and negative blue low gray level voltages PBV_x and NBV_x through the first and second regions 2122a and 2122b. Through the first and second common areas 2122c1 and 2122c2, three common color gray-level voltages PCV_y and NCV_y having positive and negative polarities are generated and supplied to the analog processor 140.

The second divided resistance string 2124 is connected in series between the positive external gradation external voltage PEVv and the base power supply VSS and is connected to the positive red / violet in accordance with the first and second frame control signals FCS1 and FCS2. And the first to c-th voltage divider Rr_cc to Rr_d + 1 for the positive / lower red / green for generating the green low grayscale voltage PRGV_x or the positive red / green low modulated grayscale voltage PRGMV_x. . In this case, the positive gray level external voltage PEVv may have the same level as the r1 reference gamma voltage GMA_r1.

Each of the first to c divided voltage resistors Rr_cc to Rr_d + 1 for the positive red / green polarity is the cc to d + 1 divided voltage resistor R_cc configured in the first region 2122a of the first divided voltage resistance row 2122. To R_d + 1).

The first and second frame control signals FCS1 and FCS2 and at least one positive external voltage PEV1 are supplied to the divided node in the middle of the second divided resistor row 2124. For example, among the voltage dividing nodes of the second voltage dividing resistor row 2124, the first voltage dividing node RB_cc and Rr_cc + 1 generating the fourth gray level voltage PRGV_v is connected to the first through the first resistor R1. The frame control signal FCS1 is supplied, and the second frame control signal FCS2 is supplied to the divided node Rr_d + 1 and VSS generating the zeroth gray voltage PRGV_0 through the second resistor R2. . The first gray level positive external voltage PEV1 is supplied to the divided voltage node Rr_d and Rr_d + 1 that generate the first gray voltage PRGV_1 among the divided voltage nodes of the second divided resistor row 2124. May not be supplied.

Since the first and second frame control signals FCS1 and FCS2 are shown in FIG. 4 and are the same as those of the first embodiment of the present invention, the description will be made with reference to FIG. 4 and the above description.

The resistance value of the first resistor R1 of the second divided resistor row 2124 is generated at the v divided voltage node of the second divided resistor row 2124 according to the first frame control signal FCS1 of the first logic state. The positive red / green vth gray voltage PRGV_v has the same voltage level as that of the positive blue vth gray voltage PBV_v, and according to the first frame control signal FCS1 in the second logic state. The positive red / green vth gray voltage PRGV_v generated at the vth divided voltage node of the second divided resistor row 2124 is set to have a voltage level lower than that of the positive blue vth gray voltage PBV_v.

The resistance value of the second resistor R2 of the second divided resistor row 2124 may be set at the zero divided node of the second divided resistor row 2124 according to the second frame control signal FCS2 of the second logic state. The generated zero red / green zero gradation voltage PRGV_0 has the same voltage level as that of the positive blue zero gradation voltage PBV_0 and is applied to the second frame control signal FCS2 in the first logic state. Accordingly, the positive zero / th gray voltage PRGV_0 generated at the zero voltage divider node of the second voltage divider resistor 2124 is set to have a voltage level lower than the zeroth gray voltage PBV_0 for positive blue. do.

The second voltage divider resistor 2124 includes the first to the second polarity red / green colors according to the first frame control signal FCS1 in the first logic state and the second frame control signal FCS2 in the second logic state. c Vth to 0th grayscales having the same voltage level as the blue to Vth to 0th grayscale voltages PBV_v to PBV_0 for the positive polarity due to voltage division at each divided node formed between the divided voltage resistors Rr_cc to Rr_d + 1. The red / green low gray level voltage PRGV_x having x pieces including the voltages PRGV_v to PRGV_0 is generated and supplied to the analog processor 140.

On the other hand, the second voltage divider resistor 2124 includes the first to the red / green positive polarities in accordance with the first frame control signal FCS1 in the second logic state and the second frame control signal FCS2 in the first logic state. Vth to Vth voltages having a lower voltage level than each of the blue to Vth to Vth gray voltages PBV_v to PBV_0 for the positive polarity due to voltage division at each divided node formed between the c divided voltage resistors Rr_cc to Rr_d + 1. The red / green sub-modulation gray voltage PRGMV_x having x pieces including 0 modulation gray voltage is generated and supplied to the analog processor 140.

The third divided resistance string 2126 is connected in series between the negative zero-level external voltage NEV0 and the base power supply VSS, and is connected to the negative voltage according to the first and second frame control signals FCS1 and FCS2. A first to c-th voltage divider Rr_dd to Rr_f for negative red / green to generate a red / green low gray level voltage NRGV_x or a negative red / green low modulation gray voltage NRGMV_x. It is composed. In this case, the negative zeroth gray external voltage NEV0 may have the same level as the j / 2 + 1th reference gamma voltage GMA_j / 2 + 1.

Each of the first to c-th partial voltage resistances Rr_dd to Rr_f for the negative red / green color is the dd to fth partial voltage resistances R_dd to R_f configured in the second region 2122b of the first partial voltage resistance row 2122. ) Has the same resistance value as each.

The first and second frame control signals FCS1 and FCS2 and at least one negative external voltage NEV1 are supplied from the outside to the divided node in the middle of the third divided resistor row 2126. For example, a second frame control is performed through a third resistor R3 to a zero divided voltage node NV1 and Rr_dd that generates a zero gray level voltage NRGV_0 among the divided voltage nodes of the third divided resistor row 2126. The signal FCS2 is supplied, and the first frame control signal FCS1 is supplied to the divided node Rr_f-1 and Rr_f generating the v th gray voltage NRGV_v through the fourth resistor R4. In addition, the first gray-level negative external voltage NEV1 is supplied to the divided voltage node Rr_dd and Rr_dd + 1 that generate the first gray voltage NRGV_1 among the divided voltage nodes of the third divided resistor row 2126. May not be supplied.

The resistance value of the third resistor R3 of the third divided resistor row 2126 is generated at the zero divided node of the third divided resistor row 2126 according to the second frame control signal FCS2 of the second logic state. The negative red / green zero gradation voltage NRGV_0 has the same voltage level as the negative blue zero gradation voltage NBV_0, and is applied to the second frame control signal FCS2 in the first logic state. Accordingly, the negative red / green zeroth gray voltage NRGV_0 generated at the zeroth voltage division node of the third divided resistor row 2126 has a voltage level higher than that of the negative blue zeroth gray voltage NBV_0. It is set to.

The resistance value of the fourth resistor R4 of the third divided resistor row 2126 is determined by the v divided voltage node of the third divided resistor row 2126 according to the first frame control signal FCS1 of the first logic state. The generated negative red / green vth gray voltage NRGV_v has the same voltage level as that of the negative blue vth gray voltage NBV_v, and the first frame control signal FCS1 in the second logic state. The voltage level of the negative red / green v-gradation voltage NRGV_v generated at the v-divided voltage node of the third divided resistor row 2126 is higher than that of the negative blue v-gradation voltage NBV_v. It is set to have.

The third voltage divider resistor 2126 may include the first to third polarity red / green first to third frame control signals FCS1 in the first logic state and the second frame control signal FCS2 in the second logic state. 0th to vth grayscales having the same voltage level as the 0th to vth grayscale voltages NBV_0 to NBV_v for the negative polarity due to voltage distribution in each voltage division node formed between the c-th voltage divider Rr_dd to Rr_f A negative red / green low gray level voltage NRGV_x having x pieces including voltages NRGV_0 to NRGV_v is generated and supplied to the analog processor 140.

On the other hand, the third divided resistor string 2126 has a negative red / green first polarity according to the first frame control signal FCS1 in the second logic state and the second frame control signal FCS2 in the first logic state. 0 th to th rd having a voltage level higher than each of the 0th to v th gray voltages NBV_0 to NBV_v for the negative polarity by voltage distribution in each divided node formed between the c th to d voltage resistors Rr_dd to Rr_f. The negative red / green sub-modulation gradation voltage NRGMV_x having x pieces including the v modulation gradation voltage is generated and supplied to the analog processor 140.

Meanwhile, in the gray scale generator 3120 of the data driving apparatus 100 according to the second embodiment of the present invention, the g-th voltage divider Rr_g of the third voltage divider resistor string 2126 is the base power VSS. 5, it may be connected to the divided voltage node (between R_g-1 and R_g) which generates the negative gradation voltage NBV_i among the divided voltage nodes of the first divided resistance string 2122 as shown in FIG. 5. have.

As described above, the gray voltage generator 120 uses the first voltage divider resistor 2122 for the positive and negative blue lower gray voltages (PBV_x, NBV_x) and the positive and negative three-color common gray voltages. (PCV_y, NCV_y) and positive / negative red / green according to the first and second frame control signals FCS1 and FCS2 using the second and third voltage divider resistors 2124 and 2126. The low gray level voltages PRGV_x and NRGV_x or the red and green low modulation gray level voltages PRGMV_x and NRGMV_x are generated. At this time, in order to compensate for the color temperature in every two frame units, that is, even-numbered frames, each of the positive blue lower gray level voltages PBV_x is relatively constant than each of the positive red / green lower modulation gray level voltages PRGMV_x. In addition to having a high voltage level, each of the negative blue lower gray voltages NBV_x has a voltage level lower than that of each of the negative red / green low modulation gray voltages NRGMV_x.

As such, the data driver 100 according to the second embodiment of the present invention separately separates the lower gray voltages PBV and NBV for blue and the lower gray voltages PRGV, NRGV or PRGMV, and NRGMV for red / green. In addition, by controlling the gray level and maintaining the color temperature according to the gray level by alternately generating the red / green low gray level voltage (PRGV, NRGV) or the low modulation gray level voltage (PRGMV, NRGMV) on a frame basis. May be minimized and the size of the gray voltage generator 120 may be reduced.

In the data driving apparatus according to the first and second embodiments of the present invention described above, the upper and lower gray levels of the blue gray voltages PBV and NBV and the red / green gray voltages PRGV and NRGV are independently separated from each other. Although individually controlled, the present invention is not limited thereto, and as described below, the upper and lower gray scales may be separated and independently controlled.

10 is a block diagram schematically illustrating a data driving device 100 according to a third embodiment of the present invention.

Referring to FIG. 10, the data driving apparatus 100 according to the third embodiment of the present invention is the first embodiment of the present invention shown in FIG. 2 except for the gray scale generator 3120 and the analog processor 3140. Has the same configuration as Accordingly, the description of the other components except the description of the gray scale generator 3120 will be replaced with the above description.

As shown in FIG. 11, the gray scale generator 3120 includes first to fifth divided resistance strings 3122, 3124, 3125, 3126, and 3127. Since the gray scale generator 3120 is configured by combining the first embodiment of the present invention shown in FIG. 3 and the second embodiment of the present invention shown in FIG. 9, a detailed description thereof will be replaced with the above description. Hereinafter, only schematic functions will be described.

The first divided resistor row 3122 includes first to fourth regions 3122a1, 3122a2, 3122b1, and 3122b2, and first and second common regions 3122c1 and 3122c2.

The first region 3122a1 is substantially the same as the first region 122a of the gray scale generator 120 shown in FIG. 3 except for the reference numerals. Accordingly, the first region 3122a1 generates the positive blue upper grayscale voltage PBUV_x having x pieces including the positive i th to h gray voltages PBV_i to PBV_h to the analog processor 3140. Supply.

The first common area 3122c1 is configured substantially the same as the positive region of the common area 122c of the gray scale generator 120 shown in FIG. Accordingly, the first common area 3122c1 receives the positive tricolor common gradation voltage PCV_y having y pieces including the positive h-1 to v + 1 gradation voltages PCV_h-1 to PCV_v + 1. It generates and supplies it to the analog processor 3140.

The second region 3122a2 is configured substantially the same as the first region 2122a of the gradation generator 120 shown in FIG. 9 except for the reference numerals. Accordingly, the second region 3122a2 generates the positive blue low gray level voltage PBLV_z having z including the positive zeroth to zeroth gray voltages PBV_v to PBV_0 and supplies it to the analog processor 3140. do.

The third region 3122b1 is substantially the same as the second region 122b of the gray scale generator 120 illustrated in FIG. 3 except for the reference numerals. Accordingly, the third region 3122b1 generates the negative blue upper grayscale voltage NBUV_x having x pieces including the negative h th to i th gray voltages NBV_h to NBV_i, and thus the analog processing unit 3140. To feed.

The second common area 3122c2 is configured substantially the same as the negative region of the common area 122c of the gradation generating unit 120 shown in FIG. Accordingly, the second common area 3122c2 has the negative tricolor common gradation voltage NCV_y having y pieces including the negative v + 1 to h-1 gradation voltages NCV_v + 1 to NCV_h-1. ) Is generated and supplied to the analog processor 3140.

The fourth region 3122b2 is substantially the same as the second region 2122b of the gray scale generator 120 shown in FIG. 9 except for the reference numerals. Accordingly, the fourth region 3122b2 generates the negative blue low gray level voltage NBLV_z having z including the negative zero to v gray voltages NBV_0 to NBV_v and generates the analog processing unit 3140. To feed.

The second divided resistor string 3124 is substantially the same as the second divided resistor row 124 of the gray scale generator 120 shown in FIG. 3 except for the reference numerals. Accordingly, the second voltage divider resistor 3124 includes x positive red lines having positive i th to h gray voltages PRGV_i to PRGV_h according to the first and second frame control signals FCS1 and FCS2. The green / high gray level voltage PRGUV_x or the red / green high gray level modulation voltage PRGUMV_x having x pieces is generated and supplied to the analog processor 3140.

The third divided resistor string 3125 is configured substantially the same as the third divided resistor row 126 of the gray scale generator 120 shown in FIG. Accordingly, the third divided resistor string 3125 has x negative electrodes including the negative h th to i th gray voltages NRGV_h to NRGV_i according to the first and second frame control signals FCS1 and FCS2. The red / green upper gray level voltage (NRGUV_x) or the negative red / green upper modulation gray level voltage (NRGUMV_x) having x is generated and supplied to the analog processor 3140.

The fourth divided resistor row 3126 is configured substantially the same as the second divided resistor row 2124 of the gray scale generator 120 shown in FIG. 9 except for the reference numerals. Accordingly, the fourth divided resistor string 3126 has z positive polarities including zero to zero grayscale voltages PRGV_v to PRGV_0 according to the first and second frame control signals FCS1 and FCS2. The low / low green gray level modulation voltage PRGLV_z or z positive red / green low modulation gray level voltage PRGLMV_z is generated and supplied to the analog processor 3140.

The fifth divided resistor string 3127 is substantially the same as the third divided resistor row 2126 of the gray scale generator 120 illustrated in FIG. 9 except for the reference numerals. Accordingly, the fifth divided resistance string 3127 includes z negative polarities including the zeroth to vth gray voltages NRGV_0 to NRGV_v according to the first and second frame control signals FCS1 and FCS2. The red / green low gray level voltage NRGLV_z or the negative red / green low gray level voltage NRGLMV_z having z are generated and supplied to the analog processing unit 3140.

As described above, the gray scale generator 3120 uses the first divided resistance string 3122 to display the upper and lower gray voltages PBUV_x, PBLV_z, NBUV_x, and NBLV_z for the positive and negative polarities, and the positive and negative polarities. In addition to generating the three-color common gradation voltages PCV_y and NCV_y, the positive red / The green upper and lower gray level voltages (PRGUV_x, NRGLV_z) or positive red / green upper and lower modulation gray level voltages (PRGUMV_x, NRGLMV_z) are generated, and the fourth and fifth voltage divider resistors 3126 and 3127 are used. Upper and lower gray level voltages (NRGUV_x, NRGLV_z) for negative red / green or upper and lower modulation gray level voltages (NRGUMV_x, NRGLMV_z) for negative red / green according to the first and second frame control signals FCS1 and FCS2. ).

In FIG. 10, the analog processor 3140 includes a digital analog converter 3142 and an output buffer unit 144.

As illustrated in FIG. 12, the digital-to-analog converter 3314 may provide the gray scale voltages PBUV, PBLV, NBUV, NBLV, PCV, NCV, PRGUV or PRGUMV, PRGLV, or PRGLMV, NRGUV, which are supplied to the data converter 200. Or NRGUMV, NRGLV or NRGLMV) has the same configuration as the first embodiment of the present invention shown in FIG. Therefore, the description of the data converter 200 except the gray voltage supplied to the data converter 200 will be replaced with the description of FIG. 6.

In FIG. 12, the first, fourth, fifth, and eight decoders D1, D4, D5, and D8 each have a positive red / green upper and lower gray level voltage PRGUV, PRGLV or positive electrode from the gray level voltage generator 3120. The upper and lower modulated gradation voltages (PRGUMV, PRGLMV) for red / green of the polarity and the positive tricolor common gradation voltages (PCV) are supplied. Each of the first, fourth, fifth and eighth decoders D1, D4, D5, and D8 is red or green for positive red / green and tricolor common gray voltages (PRGUV or PRGUMV, PRGLV or PRGLMV, PCV). The green latch data RData is converted into a positive red or green image signal VData.

Each of the second, seven, ten, and eleven decoders D2, D7, D10, and D11 has a negative red / green upper and lower gray level voltage (NRGUV, NRGLV) or a negative red color from the gray voltage generator 3120. The upper and lower modulated gradation voltages (NRGUMV, NRGLMV) for green / green, and the three-color common gradation voltages (NCV) of negative polarity are supplied. Each of the second, seven, ten, and eleven decoders D2, D7, D10, and D11 is red using negative red / green and three-color common gray voltages (NRGUV or NRGUMV, NRGLV, or NRGLMV, NCV). Alternatively, the green latch data RData is converted into a negative red or green image signal VData.

Each of the ninth and twelfth decoders D9 and D12 is supplied from the gray voltage generator 3120 to the upper and lower gray voltages PBUV and PBLV for the positive polarity and the three-color common gray voltage PCV for the positive polarity. Each of the ninth and twelfth decoders D9 and D12 converts the blue latch data RData into the positive blue image signal VData using the positive blue gray voltages PBUV, PBLV, and PCV.

Each of the third and sixth decoders D3 and D6 is supplied with the upper and lower gray level voltages NBUV and NBLV for the negative polarity and the three-color common gray level voltage NCV from the gray voltage generator 120. do. Each of the third and sixth decoders D3 and D6 converts the blue latch data RData into the negative blue image signal VData using the negative blue gray-level voltages NBUV, NBLV, and NCV. do.

As described above with reference to FIGS. 6 and 7A through 7D, the digital-to-analog converter 3314 controls the first and second polarity using the data path controller 300 and the image signal path controller 400. By controlling the paths of the data and image signals according to the logic states of the signals POL1 and POL2, the latch data RData is converted into the image signal VData so as to have a polar pattern of a horizontal 1 dot or horizontal 2 dot inversion method. The output buffer unit 144 is supplied.

The output buffer unit 144 buffers the image signal VData of each channel supplied from the digital-to-analog converter 3314 and outputs the result to the outside through the final output channel. At this time, the output buffer unit 144 amplifies and outputs the image signal VData in consideration of an external load.

As such, the data driving apparatus 100 according to the third exemplary embodiment of the present invention may include the upper and lower gray voltages PBUV, PBLV, NBUV, and NBLV for blue and upper and lower gray voltages PRGUV, NRGUV, or red / green. Separately control PRGUMV, NRGUMV) and control the upper and lower gray level voltage (PRGUV, PRGLV, NRGUV, NRGLV) or upper and lower modulation gray level voltage (PRGUMV, PRGLMV, NRGUMV, NRGLMV) By alternately generating, the color temperature according to the gradation can be kept constant, the brightness can be minimized, and the size of the gradation voltage generator 3120 can be reduced.

Meanwhile, in the gray scale generator 3120 of the data driving apparatus 100 according to the third exemplary embodiment of the present invention, the first divided resistor Rr_1 of the second divided resistor string 3124 is connected to the driving power supply VDD. Instead of being connected, as shown in FIG. 5, it may be connected to a voltage divider node R_1 and R_2 that generate a positive i th gray voltage PBV_i among the voltage divider nodes of the first voltage divider resistor 3122. In addition, the g-th voltage divider Rr_g of the third voltage divider resistor 3126 is not connected to the base power supply VSS, and as shown in FIG. 5, the negative polarity of the voltage dividing node of the first voltage divider resistor 3122 is negative. It may be connected to the divided node R_g-1 and R_g generating the i th gray voltage NBV_i.

13 is a block diagram schematically illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 13, a liquid crystal display according to an exemplary embodiment of the present invention includes an image display unit having a plurality of pixel cells P formed in each region defined by a plurality of data lines DL and gate lines GL. (2); A gate driver 4 which drives the gate line GL of the image display unit 2; A data driver 6 for supplying an image signal to the data line DL of the image display unit 2; A timing controller 8 for supplying data signals R, G, and B to the data driver 6 and controlling the data driver 6 and the gate driver 4; And a reference gamma voltage generator 10 generating a plurality of reference gray voltages GMA1 to GMAj and supplying them to the data driver 8.

The image display unit 2 includes a spacer (not shown) for maintaining a constant cell gap between the upper substrate (not shown) and the lower substrate (not shown) bonded to each other; And a liquid crystal layer (not shown) formed in the liquid crystal space provided by the spacer.

The upper substrate includes at least three color filters including red, green, and blue; A black matrix for separating pixel filters and defining pixel cells; And a common electrode to which the common voltage Vcom is supplied. Here, the common electrode may be formed on the lower substrate according to the mode of the liquid crystal.

The lower substrate may include a thin film transistor formed in each pixel cell P region defined by the data lines DL and the gate lines GL; And a pixel electrode connected to the thin film transistor. The thin film transistor switches the image signal supplied from the data line DL to the pixel electrode in response to the gate-on voltage supplied from the gate line GL.

The timing controller 8 arranges the image data Data from the outside and supplies them to the data driver 6. In addition, the timing controller 8 uses a gate using at least one of an external synchronization signal, for example, a data enable signal DE for notifying a valid section of data and a dot clock DCLK for determining a transmission frequency of data. The gate control signal GCS controlling the driver 4 and the data control signal DCCS controlling the data driver 6 are generated. In this case, the timing controller 8 may further generate the gate and data control signals GCS and DCS by using at least one of an external horizontal synchronization signal Hsync and a vertical synchronization signal Vsync. The data control signal DCS includes a source output signal SOE for controlling the data output period of the data driver 6, a source start pulse SSP for instructing the start of data sampling, and a source shift clock for controlling the sampling timing of data. (SSC) and a polarity control signal POL for controlling the voltage polarity of the data. The gate control signal GCS includes the gate output signal GOE for controlling the output of the gate driver 4, that is, the output of the gate-on voltage, the gate start pulse GSP for instructing the driving of the gate driver 4, and And a gate shift clock GSC that specifies a period of the gate on voltage.

In addition, the timing controller 8 uses the first and second frame control signals FCS1 and FCS2 that are inverted from each other in units of frames by using any one of external synchronization signals, for example, a vertical synchronization signal Vsync. ) Is supplied to the data driver 6. In this case, each of the first and second frame control signals FCS1 and FCS2 has a shape as shown in FIG. 4.

The gate driver 4 generates a gate-on voltage according to the gate control signal GCS from the timing controller 8 and sequentially supplies the gate-on voltage to the gate lines GL. Accordingly, the gate lines GL of the image display unit 2 are sequentially driven by the gate-on voltage from the gate driver 4. Meanwhile, the gate driver 4 may be formed on a substrate on which the image display unit 2 is formed at the same time as the manufacturing process of the thin film transistor and connected to the gate line GL.

The reference gamma voltage generator 10 generates a plurality of reference gamma voltages GMA1 to GMAj having different voltage levels by using the divided resistance series connected in series and supplies them to the data driver 8.

The data driver 6 includes at least one data driver. Each of the data driving devices has the same configuration as any one of the data driving devices 100 according to the first to third embodiments of the present invention. Accordingly, the description of each data driver of the data driver 6 will be replaced with the description of the data driver 100 according to the embodiment of the present invention.

Meanwhile, the first polarity control signal POL1 supplied to each data driver of the data driver 6 is the same as the polarity control signal included in the data control signal DCS generated by the timing controller 8. The polarity control signal POL2 may be fixed to the first logic state or the second logic state according to the characteristics of the image display unit 2. Of course, the first and second polarity control signals POL1 and POL2 supplied to the data driving apparatuses 100 of the data driving unit 6 may vary according to the characteristics of the image data or the image display unit 2. Can be generated).

In addition, a plurality of reference gamma voltages GMA1 to GMAj may be provided from the reference gamma voltage generator 10 to the gamma buffer units 125 of the data driving apparatuses 100 according to the first to third embodiments of the present invention. Is supplied.

As described above, the liquid crystal display according to the exemplary embodiment of the present invention separately controls the upper gray voltage for blue and the upper gray voltage for red / green, and separately controls the red / green gray voltage or the red / green color for each frame. By alternately generating the modulated gradation voltages, the color temperature according to the gradations can be kept constant, the luminance deterioration can be minimized, and the size of the gradation voltage generation unit can be reduced.

In addition, the liquid crystal display according to the exemplary embodiment of the present invention includes a digital analog converter configured to have the number of decoders for converting digital data into image signals to be equal to the number of output channels of the data driving apparatus. By reducing it, it becomes easier to cope with the enlargement.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

1 is a graph showing color temperature according to a conventional gradation;

2 is a block diagram schematically showing a data driving apparatus according to a first embodiment of the present invention;

3 is a circuit diagram schematically showing a gray scale generator shown in FIG. 2;

4 is a waveform diagram showing first and second frame control signals shown in FIGS. 2 and 3;

FIG. 5 is a circuit diagram schematically illustrating a gray scale generator according to another exemplary embodiment shown in FIG. 2; FIG.

FIG. 6 is a block diagram schematically showing a digital analog converter shown in FIG. 2; FIG.

FIG. 7A is a diagram illustrating a path of data and image signals corresponding to a horizontal two dot inversion scheme according to first and second polarity control signals according to an embodiment of the present disclosure; FIG.

FIG. 7B is a diagram illustrating data and image signal paths corresponding to an inverted horizontal two-dot inversion scheme according to first and second polarity control signals according to an embodiment of the present disclosure; FIG.

FIG. 7C is a diagram illustrating a path of data and image signals corresponding to the horizontal one dot inversion scheme according to the first and second polarity control signals according to an embodiment of the present disclosure; FIG.

FIG. 7D illustrates a path of data and image signals corresponding to the inverted horizontal 1 dot inversion scheme according to the first and second polarity control signals according to an embodiment of the present disclosure; FIG.

8 is a graph showing color temperature according to gray scale in a data driver and a liquid crystal display according to an exemplary embodiment of the present invention;

9 is a circuit diagram schematically illustrating a gray scale generator of a data driver according to a second exemplary embodiment of the present invention;

10 is a block diagram schematically showing a data driving apparatus according to a second embodiment of the present invention;

FIG. 11 is a circuit diagram schematically illustrating a gray scale generator shown in FIG. 10; FIG.

12 is a block diagram schematically showing a digital-analog converter shown in FIG. 10; And

13 is a block diagram schematically illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

Claims (26)

A digital processor configured to latch input red, green, and blue data; By using the plurality of reference gamma voltages and the first and second power supplies, blue and gray color voltages for positive and negative polarities are generated, and positive and negative voltages are generated according to the first and second frame control signals. A gray voltage generator configured to generate negative red / green gray voltages or red / green modulated gray voltages; And Red and green latch data supplied from the digital processor using the positive / negative red / green gradation voltages or the red / green modulation gradation voltages and the three-color common gradation voltages of the positive and negative polarities. The blue latch data supplied from the digital processing unit is converted using the blue and gray gray voltages of the positive and negative polarities and the three common color gradation voltages of the positive and negative polarities, respectively. And an analog processing unit for converting into a blue image signal. The method of claim 1, Each of the first and second frame control signals has an inverted form and is inverted in a frame unit. The method of claim 2, Each of the positive gray gray voltages has a higher voltage level than each of the positive red / green modulation gray voltages. And each of the negative gray gray voltages has a lower voltage level than each of the negative red / green modulation gray voltages. The method of claim 3, wherein The gray gradation voltages are i to h (where h is a natural number less than i) of the total i gradations corresponding to the number of bits of the data, and / or v (where v is a natural number less than h). To zeroth gray voltage, The red / green gradation voltages or the red / green gradation voltages are i th to h th gradation voltages and / or v th to 0 th gradation voltages among the i th gradations, The three color common gradation voltages may be a 0th to h-1 gradation voltage or a v + 1 to i gradation voltage or a v + 1 to h-1 gradation voltage among the total i gradation numbers. . The method of claim 4, wherein The gray voltage generator; A first voltage divider resistor for generating the positive and negative blue i-h gray voltages and the positive and negative tri-color common zero-h-1 gray voltages; Separated from the first voltage divider resistor string, the positive red / green i-h gray voltages or the positive red / green i-h modulated gray voltages are generated according to the first and second frame control signals. A second partial pressure resistance heat; And Separated from the first voltage divider resistor string, the negative red / green first to h gray voltages or the negative red / green first to h modulated gray voltages are applied according to the first and second frame control signals. And a third voltage divider resistor string to generate. The method of claim 5, wherein The first voltage divider resistor string includes a plurality of first voltage divider resistors connected in series between the first power source and the second power source; The plurality of first voltage divider resistors, A first region for generating the i-th to h-gradation voltages for the blue positive polarity; A first common area for generating the positive tricolor common 0 to h-1 gray voltages; A second common area for generating the negative tricolor common 0 to h-1 gray voltages; And And a second area for generating the negative blue first to h gray voltages. The method of claim 5, wherein The second voltage divider resistor string includes a plurality of second voltage divider resistors connected in series between the first power source and the second power source; The first frame control signal is supplied to a divided node for generating the i th gray voltage among the plurality of second divided resistors through a first resistor, and a second resistor is supplied to the divided node for generating the h th gray voltage. And the second frame control signal is supplied through the data driving device. The method of claim 5, wherein The third voltage divider resistor string includes a plurality of third voltage divider resistors connected in series between a negative external voltage for h-th gray and the second power supply. The second frame control signal is supplied to a divided node for generating the h-th gray voltage among the plurality of third divided resistors through a third resistor, and a fourth resistor is applied to the divided node for generating the i-th gray voltage. And the first frame control signal is supplied through the data driving device. The method of claim 4, wherein The gray voltage generator; A first voltage divider string for generating the positive and negative tricolor common colors i to v + 1 gray voltages and the blue to zero gray voltages for the positive and negative polarities; Separated from the first voltage divider resistor string to generate the positive red / green zeroth to zero gray voltage or the positive red / green zeroth to gray modulation gray voltage according to the first and second frame control signals. A second partial pressure resistance heat; And The negative divided red / green zeroth to zero gray voltage or the negative divided red / green zeroth to zero modulation gray voltage according to the first and second frame control signals are separated from the first voltage divider resistor string. And a third voltage divider resistor string to generate. The method of claim 9, The first voltage divider resistor string includes a plurality of first voltage divider resistors connected in series between the first power source and the second power source; The plurality of first voltage divider resistors, A first common area for generating the positive tricolor common i to v + 1 gray voltages; A first region for generating the blue to zero gray level voltages of the positive polarity; A second region generating the zeroth to vth gray voltages for the negative blue color; And And a second common region for generating the negative tricolor common v + 1 to i gray voltages. The method of claim 9, The second voltage divider resistor string includes a plurality of second voltage divider resistors connected in series between the first power source and the second power source. The first frame control signal is supplied to the divided node for generating the vth gray voltage among the plurality of second divided resistors through a first resistor, and the second resistor is provided for the divided node for generating the zero gray voltage. And the second frame control signal is supplied through the data driving device. The method of claim 9, The third voltage dividing resistor column includes a plurality of third voltage dividing resistors connected in series between a negative external gray level voltage and the second power supply. The second frame control signal is supplied to the divided node generating the zeroth gray voltage among the plurality of third divided resistors through a third resistor, and a fourth resistor is supplied to the divided node generating the vth gray voltage. And the first frame control signal is supplied through the data driving device. The method of claim 4, wherein The gray voltage generator; The i-h gray voltages for the positive and negative blue colors, the v-th zeroth gray voltages for the positive and negative blue colors, and the v + 1-h- tri-color common agents for the positive and negative polarities A first divided resistor string for generating one gray scale voltage; Separated from the first voltage divider resistor string, the positive red / green i-h gray voltages or the positive red / green i-h modulated gray voltages are generated according to the first and second frame control signals. A second partial pressure resistance heat; Separated from the first voltage divider resistor string, the negative red / green first to h gray voltages or the negative red / green first to h modulated gray voltages are applied according to the first and second frame control signals. Generating a third partial pressure resistance heat; Separated from the first voltage divider resistor string to generate the positive red / green zeroth to zero gray voltage or the positive red / green zeroth to gray modulation gray voltage according to the first and second frame control signals. Fourth partial pressure resistance heat; And The negative divided red / green zeroth to zero gray voltage or the negative divided red / green zeroth to zero modulation gray voltage according to the first and second frame control signals are separated from the first voltage divider resistor string. And a fifth divided resistance string to be generated. The method of claim 13, The first voltage divider resistor string includes a plurality of first voltage divider resistors connected in series between the first power source and the second power source; The plurality of first voltage divider resistors, A first region for generating the i-th to h-gradation voltages for the blue positive polarity; A first common region for generating the positive tricolor common h-1 to v + 1 gray voltages; A second region for generating the blue to zero gray level voltages of the positive polarity; A third region for generating the negative blue first to h gray voltages; A second common region for generating the negative tricolor common h-1 to v + 1 gray voltages; And And a fourth region for generating the negative blue to zeroth to zero gray voltages. The method of claim 13, The second voltage divider resistor string includes a plurality of second voltage divider resistors connected in series between the first power source and the second power source; The first frame control signal is supplied to a divided node for generating the i th gray voltage among the plurality of second divided resistors through a first resistor, and a second resistor is supplied to the divided node for generating the h th gray voltage. And the second frame control signal is supplied through the data driving device. The method of claim 13, The third voltage dividing resistance train is between the negative voltage of the h-th grayscale voltage and the second power supply. A plurality of third voltage divider resistors connected in series; The second frame control signal is supplied to a divided node for generating the h th gray voltage among the plurality of third divided resistors through a third resistor, and a fourth resistor is provided for the divided node for generating the i th gray voltage. And the first frame control signal is supplied through the data driving device. The method of claim 13, The fourth divided resistor row includes a plurality of fourth divided resistors connected in series between the first power source and the second power source; The first frame control signal is supplied to a divided node generating the v th gray voltage among the plurality of fourth divided resistors through a fifth resistor, and a sixth resistor is supplied to the divided node generating the zero th gray voltage. And the second frame control signal is supplied through the data driving device. The method of claim 13, The fifth voltage divider resistor string includes a plurality of fifth voltage divider resistors connected in series between a negative external gray level voltage and the second power supply. The second frame control signal is supplied to a divided node generating the zeroth gray voltage among the plurality of fifth divided resistors through a seventh resistor, and an eighth resistor is supplied to the divided node generating the vth gray voltage. And the first frame control signal is supplied through the data driving device. The method of claim 4, wherein The analog processing unit; The positive / negative red / green gradation voltages or the red / green modulation gradation voltages, the positive and negative tri-color common gradation voltages, and the positive and negative blue gradation voltages And a digital-to-analog converter for converting the latch data into an image signal having a polarity corresponding to the first and second polarity control signals by using the three-color common gradation voltages of the positive and negative polarities. And And an output buffer unit for buffering the image signal supplied from the digital analog converter. The method of claim 19, The digital-to-analog converter includes a plurality of data conversion blocks having 12 channels repeatedly arranged in the order of red, green, and blue, each data conversion block comprising: a plurality of data conversion blocks; The positive / negative red / green gradation voltages or the red / green modulation gradation voltages, the positive and negative tri-color common gradation voltages, and the positive and negative blue gradation voltages And a data converter converting the red, green, and blue latch data into red, green, and blue image signals using the three common gray voltages of the positive and negative polarities. A data path controller configured to control a path of each of the red, green, and blue latch data supplied from the digital processor to the data converter through the first through twelfth input channels according to the first and second polarity control signals; And And an image signal path control unit configured to control paths of the red, green, and blue image signals supplied from the data converter to the output buffer unit according to the first and second polarity control signals. Drive system. The method of claim 20, The data converter; A first to twelfth decoder including a positive decoder for converting the latch data into a positive image signal and a negative decoder for converting the latch data into a negative image signal, And the first to twelfth decoders are arranged to be repeated in the order of the positive polarity, the negative polarity, the negative polarity, and the positive polarity. The method of claim 21, Each of the first, fourth, fifth, and eighth decoders includes the positive red / green gray voltages or the positive red / green modulation gray voltages supplied from the gray voltage generator. 3-color common gradation voltages are supplied, Each of the second, seventh, tenth, and eleventh decoders includes the negative red / green gray voltages or the negative red / green modulation gray voltages from the gray voltage generator and the negative polarity. 3 colors of common gradation voltages are supplied, Each of the ninth and twelfth decoders is supplied with the gray gray voltages of the positive polarity and the three common color gradation voltages of the positive polarity from the gray voltage generator. And each of the third and sixth decoders is supplied with the negative gray gray voltages and the negative three color common gray voltages from the gray voltage generator. The method of claim 22, The data path control unit; A first data path controller configured to control a path of the latch data supplied through the second to twelfth input channels according to the second polarity control signal; And The first, second, fifth, sixth, ninth, and tenth input channels and the path of the latch data supplied through the first data path controller are controlled according to the first polarity control signal. And a second data path control unit for supplying each to the twelfth decoder. The method of claim 22, The image signal path control section; A first image signal path control unit which controls the path of the image signal supplied from the second to twelfth decoders according to the second polarity control signal; And The paths of the image signals supplied from the first, second, fifth, sixth, ninth and tenth decoders and the image signals supplied through the first image signal path control unit are converted into the first polarity control signal. And a second image signal path control section for controlling accordingly and supplying the output buffer section to each of the buffer sections. An image display unit having a plurality of pixel cells formed for each region defined by a plurality of data lines and gate lines; A gate driver for driving a gate line of the image display unit; A data driver for supplying an image signal to a data line of the image display unit; A timing controller which supplies a data signal to the data driver and controls the data driver and the gate driver; And A reference gamma voltage generator configured to generate a plurality of reference gray voltages and supply them to the data driver; The data driver of claim 1, wherein the data driver comprises the data driver of any one of claims 1 to 24. The method of claim 25, And the timing controller generates the first and second frame control signals that are inverted from each other and is inverted in units of frames and supplies the first and second frame control signals to the data driving devices.

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